mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-29 12:49:57 +00:00
314 lines
12 KiB
HTML
314 lines
12 KiB
HTML
<HTML>
|
|
<HEAD><TITLE>Place & Route Report</TITLE>
|
|
<STYLE TYPE="text/css">
|
|
<!--
|
|
body,pre{
|
|
font-family:'Courier New', monospace;
|
|
color: #000000;
|
|
font-size:88%;
|
|
background-color: #ffffff;
|
|
}
|
|
h1 {
|
|
font-weight: bold;
|
|
margin-top: 24px;
|
|
margin-bottom: 10px;
|
|
border-bottom: 3px solid #000; font-size: 1em;
|
|
}
|
|
h2 {
|
|
font-weight: bold;
|
|
margin-top: 18px;
|
|
margin-bottom: 5px;
|
|
font-size: 0.90em;
|
|
}
|
|
h3 {
|
|
font-weight: bold;
|
|
margin-top: 12px;
|
|
margin-bottom: 5px;
|
|
font-size: 0.80em;
|
|
}
|
|
p {
|
|
font-size:78%;
|
|
}
|
|
P.Table {
|
|
margin-top: 4px;
|
|
margin-bottom: 4px;
|
|
margin-right: 4px;
|
|
margin-left: 4px;
|
|
}
|
|
table
|
|
{
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
border-collapse: collapse;
|
|
}
|
|
th {
|
|
font-weight:bold;
|
|
padding: 4px;
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
vertical-align:top;
|
|
text-align:left;
|
|
font-size:78%;
|
|
}
|
|
td {
|
|
padding: 4px;
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
vertical-align:top;
|
|
font-size:78%;
|
|
}
|
|
a {
|
|
color:#013C9A;
|
|
text-decoration:none;
|
|
}
|
|
|
|
a:visited {
|
|
color:#013C9A;
|
|
}
|
|
|
|
a:hover, a:active {
|
|
text-decoration:underline;
|
|
color:#5BAFD4;
|
|
}
|
|
.pass
|
|
{
|
|
background-color: #00ff00;
|
|
}
|
|
.fail
|
|
{
|
|
background-color: #ff0000;
|
|
}
|
|
.comment
|
|
{
|
|
font-size: 90%;
|
|
font-style: italic;
|
|
}
|
|
|
|
-->
|
|
</STYLE>
|
|
</HEAD>
|
|
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|
Thu Sep 21 05:39:49 2023
|
|
|
|
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
|
|
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
|
|
RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
|
|
//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
|
|
|
|
|
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
|
|
|
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
|
|
Level/ Number Worst Timing Worst Timing Run NCD
|
|
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
|
---------- -------- ----- ------ ----------- ----------- ---- ------
|
|
5_1 * 0 5.578 0 0.304 0 13 Completed
|
|
* : Design saved.
|
|
|
|
Total (real) run time for 1-seed: 13 secs
|
|
|
|
par done!
|
|
|
|
Note: user must run 'Trace' for timing closure signoff.
|
|
|
|
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
|
|
Thu Sep 21 05:39:49 2023
|
|
|
|
|
|
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
|
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
|
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
|
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
|
Placement level-cost: 5-1.
|
|
Routing Iterations: 6
|
|
|
|
Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
|
|
Design name: RAM2GS
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-1200HC
|
|
Package: TQFP100
|
|
Performance: 4
|
|
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
|
Package Status: Final Version 1.44.
|
|
Performance Hardware Data Status: Final Version 34.4.
|
|
License checked out.
|
|
|
|
|
|
Ignore Preference Error(s): True
|
|
|
|
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
|
|
|
PIO (prelim) 63+4(JTAG)/108 62% used
|
|
63+4(JTAG)/80 84% bonded
|
|
IOLOGIC 25/108 23% used
|
|
|
|
SLICE 120/640 18% used
|
|
|
|
EFB 1/1 100% used
|
|
|
|
|
|
Number of Signals: 388
|
|
Number of Connections: 1017
|
|
|
|
Pin Constraint Summary:
|
|
63 out of 63 pins locked (100% locked).
|
|
|
|
The following 2 signals are selected to use the primary clock routing resources:
|
|
RCLK_c (driver: RCLK, clk load #: 47)
|
|
PHI2_c (driver: PHI2, clk load #: 20)
|
|
|
|
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
|
|
|
The following 2 signals are selected to use the secondary clock routing resources:
|
|
nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
|
|
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
|
|
|
WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
|
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
|
No signal is selected as Global Set/Reset.
|
|
Starting Placer Phase 0.
|
|
.........
|
|
Finished Placer Phase 0. REAL time: 0 secs
|
|
|
|
Starting Placer Phase 1.
|
|
....................
|
|
Placer score = 68062.
|
|
Finished Placer Phase 1. REAL time: 7 secs
|
|
|
|
Starting Placer Phase 2.
|
|
.
|
|
Placer score = 67096
|
|
Finished Placer Phase 2. REAL time: 7 secs
|
|
|
|
|
|
|
|
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
|
|
|
|
Global Clock Resources:
|
|
CLK_PIN : 1 out of 8 (12%)
|
|
General PIO: 3 out of 108 (2%)
|
|
PLL : 0 out of 1 (0%)
|
|
DCM : 0 out of 2 (0%)
|
|
DCC : 0 out of 8 (0%)
|
|
|
|
Global Clocks:
|
|
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 47
|
|
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 20
|
|
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 9, ce load = 0, sr load = 0
|
|
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL4A)", clk load = 8, ce load = 0, sr load = 0
|
|
|
|
PRIMARY : 2 out of 8 (25%)
|
|
SECONDARY: 2 out of 8 (25%)
|
|
|
|
Edge Clocks:
|
|
No edge clock selected.
|
|
|
|
|
|
|
|
|
|
I/O Usage Summary (final):
|
|
63 + 4(JTAG) out of 108 (62.0%) PIO sites used.
|
|
63 + 4(JTAG) out of 80 (83.8%) bonded PIO sites used.
|
|
Number of PIO comps: 63; differential: 0.
|
|
Number of Vref pins used: 0.
|
|
|
|
I/O Bank Usage Summary:
|
|
+----------+----------------+------------+-----------+
|
|
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
|
+----------+----------------+------------+-----------+
|
|
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
|
| 1 | 20 / 21 ( 95%) | 3.3V | - |
|
|
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
|
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
|
+----------+----------------+------------+-----------+
|
|
|
|
Total placer CPU time: 6 secs
|
|
|
|
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
|
|
|
0 connections routed; 1017 unrouted.
|
|
Starting router resource preassignment
|
|
|
|
Completed router resource preassignment. Real time: 11 secs
|
|
|
|
Start NBR router at 05:40:00 09/21/23
|
|
|
|
*****************************************************************
|
|
Info: NBR allows conflicts(one node used by more than one signal)
|
|
in the earlier iterations. In each iteration, it tries to
|
|
solve the conflicts while keeping the critical connections
|
|
routed as short as possible. The routing process is said to
|
|
be completed when no conflicts exist and all connections
|
|
are routed.
|
|
Note: NBR uses a different method to calculate timing slacks. The
|
|
worst slack and total negative slack may not be the same as
|
|
that in TRCE report. You should always run TRCE to verify
|
|
your design.
|
|
*****************************************************************
|
|
|
|
Start NBR special constraint process at 05:40:00 09/21/23
|
|
|
|
Start NBR section for initial routing at 05:40:01 09/21/23
|
|
Level 1, iteration 1
|
|
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
|
|
Level 2, iteration 1
|
|
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
|
|
Level 3, iteration 1
|
|
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
|
|
Level 4, iteration 1
|
|
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
|
|
|
Info: Initial congestion level at 75% usage is 0
|
|
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
|
|
|
Start NBR section for normal routing at 05:40:01 09/21/23
|
|
Level 4, iteration 1
|
|
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
|
Level 4, iteration 2
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
|
|
|
Start NBR section for setup/hold timing optimization with effort level 3 at 05:40:01 09/21/23
|
|
|
|
Start NBR section for re-routing at 05:40:01 09/21/23
|
|
Level 4, iteration 1
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
|
|
|
Start NBR section for post-routing at 05:40:01 09/21/23
|
|
|
|
End NBR router with 0 unrouted connection
|
|
|
|
NBR Summary
|
|
-----------
|
|
Number of unrouted connections : 0 (0.00%)
|
|
Number of connections with timing violations : 0 (0.00%)
|
|
Estimated worst slack<setup> : 5.578ns
|
|
Timing score<setup> : 0
|
|
-----------
|
|
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
|
|
|
|
|
|
|
Total CPU time 12 secs
|
|
Total REAL time: 13 secs
|
|
Completely routed.
|
|
End of route. 1017 routed (100.00%); 0 unrouted.
|
|
|
|
Hold time timing score: 0, hold timing errors: 0
|
|
|
|
Timing score: 0
|
|
|
|
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
|
|
|
|
|
All signals are completely routed.
|
|
|
|
|
|
PAR_SUMMARY::Run status = Completed
|
|
PAR_SUMMARY::Number of unrouted conns = 0
|
|
PAR_SUMMARY::Worst slack<setup/<ns>> = 5.578
|
|
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
|
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
|
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
|
PAR_SUMMARY::Number of errors = 0
|
|
|
|
Total CPU time to completion: 13 secs
|
|
Total REAL time to completion: 13 secs
|
|
|
|
par done!
|
|
|
|
Note: user must run 'Trace' for timing closure signoff.
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
|
|
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
</PRE></FONT>
|
|
</BODY>
|
|
</HTML>
|