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c958649a59
RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
Zane Kaminski c958649a59 SPI/LCMXO RC
2024-01-06 21:52:05 -05:00

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<HEAD><TITLE>Lattice TRACE Report</TITLE>
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<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Nov 18 02:06:11 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 147 items scored, 0 timing errors detected.
Report: 47.068MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
Report: 102.312MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
147 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 161.791ns (weighted slack = 323.582ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 10.143ns (25.2% logic, 74.8% route), 5 logic levels.
Constraint Details:
10.143ns physical path delay Din[7]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 161.791ns
Physical Path Details:
Data path Din[7]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
ROUTE 1 1.995 IOL_L2A.IN to R5C6A.C0 Bank[7]
CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 SLICE_90
ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10
CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80
ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367
CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23
ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18
CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77
ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
10.143 (25.2% logic, 74.8% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_L2A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.140ns (weighted slack = 324.280ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 9.935ns (30.7% logic, 69.3% route), 6 logic levels.
Constraint Details:
9.935ns physical path delay Din[7]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 162.140ns
Physical Path Details:
Data path Din[7]_MGIOL to SLICE_17:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
ROUTE 1 1.995 IOL_L2A.IN to R5C6A.C0 Bank[7]
CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 SLICE_90
ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10
CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80
ROUTE 6 1.188 R2C6C.F0 to R5C8D.D1 N_367
CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_11
ROUTE 3 1.102 R5C8D.F1 to R5C5D.C0 CmdEnable16
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_33
ROUTE 1 1.299 R5C5D.F0 to R5C8C.A0 CmdEnable_0_sqmuxa
CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 SLICE_17
ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c)
--------
9.935 (30.7% logic, 69.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_L2A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R5C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[1] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 9.523ns (26.9% logic, 73.1% route), 5 logic levels.
Constraint Details:
9.523ns physical path delay Din[1]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 162.411ns
Physical Path Details:
Data path Din[1]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6D.CLK to IOL_T6D.IN Din[1]_MGIOL (from PHI2_c)
ROUTE 1 1.375 IOL_T6D.IN to R5C6A.D0 Bank[1]
CTOF_DEL --- 0.495 R5C6A.D0 to R5C6A.F0 SLICE_90
ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10
CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80
ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367
CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23
ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18
CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77
ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
9.523 (26.9% logic, 73.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_T6D.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.760ns (weighted slack = 325.520ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[1] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 9.315ns (32.8% logic, 67.2% route), 6 logic levels.
Constraint Details:
9.315ns physical path delay Din[1]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 162.760ns
Physical Path Details:
Data path Din[1]_MGIOL to SLICE_17:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6D.CLK to IOL_T6D.IN Din[1]_MGIOL (from PHI2_c)
ROUTE 1 1.375 IOL_T6D.IN to R5C6A.D0 Bank[1]
CTOF_DEL --- 0.495 R5C6A.D0 to R5C6A.F0 SLICE_90
ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10
CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80
ROUTE 6 1.188 R2C6C.F0 to R5C8D.D1 N_367
CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_11
ROUTE 3 1.102 R5C8D.F1 to R5C5D.C0 CmdEnable16
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_33
ROUTE 1 1.299 R5C5D.F0 to R5C8C.A0 CmdEnable_0_sqmuxa
CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 SLICE_17
ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c)
--------
9.315 (32.8% logic, 67.2% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_T6D.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R5C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.896ns (weighted slack = 325.792ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[2] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 9.038ns (28.3% logic, 71.7% route), 5 logic levels.
Constraint Details:
9.038ns physical path delay Din[2]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 162.896ns
Physical Path Details:
Data path Din[2]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[2]_MGIOL (from PHI2_c)
ROUTE 1 1.753 IOL_T9A.IN to R2C6C.B1 Bank[2]
CTOF_DEL --- 0.495 R2C6C.B1 to R2C6C.F1 SLICE_80
ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80
ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367
CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23
ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18
CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77
ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
9.038 (28.3% logic, 71.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[2]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_T9A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.153ns (weighted slack = 326.306ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 8.781ns (29.1% logic, 70.9% route), 5 logic levels.
Constraint Details:
8.781ns physical path delay Din[6]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 163.153ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 1.496 IOL_L2B.IN to R2C6C.C1 Bank[6]
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_80
ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80
ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367
CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23
ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18
CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77
ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
8.781 (29.1% logic, 70.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_L2B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.245ns (weighted slack = 326.490ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[2] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.830ns (34.6% logic, 65.4% route), 6 logic levels.
Constraint Details:
8.830ns physical path delay Din[2]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 163.245ns
Physical Path Details:
Data path Din[2]_MGIOL to SLICE_17:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[2]_MGIOL (from PHI2_c)
ROUTE 1 1.753 IOL_T9A.IN to R2C6C.B1 Bank[2]
CTOF_DEL --- 0.495 R2C6C.B1 to R2C6C.F1 SLICE_80
ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80
ROUTE 6 1.188 R2C6C.F0 to R5C8D.D1 N_367
CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_11
ROUTE 3 1.102 R5C8D.F1 to R5C5D.C0 CmdEnable16
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_33
ROUTE 1 1.299 R5C5D.F0 to R5C8C.A0 CmdEnable_0_sqmuxa
CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 SLICE_17
ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c)
--------
8.830 (34.6% logic, 65.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[2]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_T9A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R5C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.389ns (weighted slack = 326.778ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[3] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 8.545ns (29.9% logic, 70.1% route), 5 logic levels.
Constraint Details:
8.545ns physical path delay Din[3]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 163.389ns
Physical Path Details:
Data path Din[3]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
ROUTE 1 1.260 IOL_T6C.IN to R2C6C.D1 Bank[3]
CTOF_DEL --- 0.495 R2C6C.D1 to R2C6C.F1 SLICE_80
ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80
ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367
CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23
ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18
CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77
ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
8.545 (29.9% logic, 70.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[3]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_T6C.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.435ns (weighted slack = 326.870ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in CmdValid (to PHI2_c -)
Delay: 8.640ns (29.6% logic, 70.4% route), 5 logic levels.
Constraint Details:
8.640ns physical path delay Din[7]_MGIOL to SLICE_22 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 163.435ns
Physical Path Details:
Data path Din[7]_MGIOL to SLICE_22:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
ROUTE 1 1.995 IOL_L2A.IN to R5C6A.C0 Bank[7]
CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 SLICE_90
ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10
CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80
ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367
CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23
ROUTE 8 0.796 R4C8A.F1 to R4C9D.C0 XOR8MEG18
CTOF_DEL --- 0.495 R4C9D.C0 to R4C9D.F0 SLICE_22
ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 CmdValid_r (to PHI2_c)
--------
8.640 (29.6% logic, 70.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_L2A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R4C9D.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.445ns (weighted slack = 326.890ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[5] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 8.489ns (30.1% logic, 69.9% route), 5 logic levels.
Constraint Details:
8.489ns physical path delay Din[5]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 163.445ns
Physical Path Details:
Data path Din[5]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6B.CLK to IOL_T6B.IN Din[5]_MGIOL (from PHI2_c)
ROUTE 1 1.204 IOL_T6B.IN to R2C6C.A1 Bank[5]
CTOF_DEL --- 0.495 R2C6C.A1 to R2C6C.F1 SLICE_80
ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80
ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367
CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23
ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18
CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77
ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
8.489 (30.1% logic, 69.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.712 8.PADDI to IOL_T6B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Report: 47.068MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
891 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.226ns
The internal maximum frequency of the following component is 102.312 MHz
Logical Details: Cell type Pin name Component name
Destination: EFB WBCLKI ufmefb/EFBInst_0
Delay: 9.774ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 6.245ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[14] (from RCLK_c +)
Destination: FF Data in wb_dati[1] (to RCLK_c +)
Delay: 9.589ns (30.5% logic, 69.5% route), 6 logic levels.
Constraint Details:
9.589ns physical path delay SLICE_3 to SLICE_52 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 6.245ns
Physical Path Details:
Data path SLICE_3 to SLICE_52:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C3D.CLK to R6C3D.Q1 SLICE_3 (from RCLK_c)
ROUTE 19 2.021 R6C3D.Q1 to R3C4C.D1 FS[14]
CTOF_DEL --- 0.495 R3C4C.D1 to R3C4C.F1 SLICE_118
ROUTE 2 1.392 R3C4C.F1 to R4C4C.A0 wb_dati_5_1_iv_0_a2_7[4]
CTOF_DEL --- 0.495 R4C4C.A0 to R4C4C.F0 SLICE_97
ROUTE 1 0.967 R4C4C.F0 to R4C4A.A0 wb_dati_5_1_iv_0_a2_0_2[1]
CTOF_DEL --- 0.495 R4C4A.A0 to R4C4A.F0 SLICE_64
ROUTE 1 1.535 R4C4A.F0 to R2C4B.B0 wb_dati_5_1_iv_0_0[1]
CTOF_DEL --- 0.495 R2C4B.B0 to R2C4B.F0 SLICE_85
ROUTE 1 0.747 R2C4B.F0 to R2C4C.C1 wb_dati_5_1_iv_0_1[1]
CTOF_DEL --- 0.495 R2C4C.C1 to R2C4C.F1 SLICE_52
ROUTE 1 0.000 R2C4C.F1 to R2C4C.DI1 wb_dati_5[1] (to RCLK_c)
--------
9.589 (30.5% logic, 69.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R6C3D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_52:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R2C4C.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.252ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 9.409ns (77.2% logic, 22.8% route), 3 logic levels.
Constraint Details:
9.409ns physical path delay ufmefb/EFBInst_0 to SLICE_45 meets
16.000ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 15.661ns) by 6.252ns
Physical Path Details:
Data path ufmefb/EFBInst_0 to SLICE_45:
Name Fanout Delay (ns) Site Resource
WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c)
ROUTE 1 0.984 EFB.WBDATO0 to R3C3A.C1 wb_dato[0]
CTOF_DEL --- 0.495 R3C3A.C1 to R3C3A.F1 SLICE_111
ROUTE 1 1.157 R3C3A.F1 to R4C6D.D0 n8MEGENe_1_0
CTOF_DEL --- 0.495 R4C6D.D0 to R4C6D.F0 SLICE_45
ROUTE 1 0.000 R4C6D.F0 to R4C6D.DI0 n8MEGENe_0 (to RCLK_c)
--------
9.409 (77.2% logic, 22.8% route), 3 logic levels.
Clock Skew Details:
Source Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.192 63.PADDI to EFB.WBCLKI RCLK_c
--------
2.192 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_45:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R4C6D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.570ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[12] (from RCLK_c +)
Destination: FF Data in wb_dati[1] (to RCLK_c +)
Delay: 9.264ns (31.6% logic, 68.4% route), 6 logic levels.
Constraint Details:
9.264ns physical path delay SLICE_4 to SLICE_52 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 6.570ns
Physical Path Details:
Data path SLICE_4 to SLICE_52:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C3C.CLK to R6C3C.Q1 SLICE_4 (from RCLK_c)
ROUTE 19 1.696 R6C3C.Q1 to R3C4C.C1 FS[12]
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_118
ROUTE 2 1.392 R3C4C.F1 to R4C4C.A0 wb_dati_5_1_iv_0_a2_7[4]
CTOF_DEL --- 0.495 R4C4C.A0 to R4C4C.F0 SLICE_97
ROUTE 1 0.967 R4C4C.F0 to R4C4A.A0 wb_dati_5_1_iv_0_a2_0_2[1]
CTOF_DEL --- 0.495 R4C4A.A0 to R4C4A.F0 SLICE_64
ROUTE 1 1.535 R4C4A.F0 to R2C4B.B0 wb_dati_5_1_iv_0_0[1]
CTOF_DEL --- 0.495 R2C4B.B0 to R2C4B.F0 SLICE_85
ROUTE 1 0.747 R2C4B.F0 to R2C4C.C1 wb_dati_5_1_iv_0_1[1]
CTOF_DEL --- 0.495 R2C4C.C1 to R2C4C.F1 SLICE_52
ROUTE 1 0.000 R2C4C.F1 to R2C4C.DI1 wb_dati_5[1] (to RCLK_c)
--------
9.264 (31.6% logic, 68.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R6C3C.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_52:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R2C4C.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.779ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 8.882ns (72.6% logic, 27.4% route), 3 logic levels.
Constraint Details:
8.882ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets
16.000ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 15.661ns) by 6.779ns
Physical Path Details:
Data path ufmefb/EFBInst_0 to SLICE_30:
Name Fanout Delay (ns) Site Resource
WCLKI2WBDA --- 5.461 EFB.WBCLKI to EFB.WBDATO1 ufmefb/EFBInst_0 (from RCLK_c)
ROUTE 1 1.995 EFB.WBDATO1 to R4C6B.C1 wb_dato[1]
CTOF_DEL --- 0.495 R4C6B.C1 to R4C6B.F1 SLICE_30
ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 LEDEN_6
CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_30
ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 LEDENe_0 (to RCLK_c)
--------
8.882 (72.6% logic, 27.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.192 63.PADDI to EFB.WBCLKI RCLK_c
--------
2.192 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R4C6B.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.810ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in wb_dati[6] (to RCLK_c +)
Delay: 9.024ns (32.4% logic, 67.6% route), 6 logic levels.
Constraint Details:
9.024ns physical path delay SLICE_1 to SLICE_55 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 6.810ns
Physical Path Details:
Data path SLICE_1 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4B.CLK to R6C4B.Q0 SLICE_1 (from RCLK_c)
ROUTE 7 1.729 R6C4B.Q0 to R4C4A.C1 FS[17]
CTOF_DEL --- 0.495 R4C4A.C1 to R4C4A.F1 SLICE_64
ROUTE 12 1.800 R4C4A.F1 to R3C4A.A1 FS_RNIHVJI[15]
CTOF_DEL --- 0.495 R3C4A.A1 to R3C4A.F1 SLICE_84
ROUTE 4 0.643 R3C4A.F1 to R3C4A.D0 wb_dati_5_1_iv_0_a2_13[3]
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 SLICE_84
ROUTE 1 0.626 R3C4A.F0 to R3C4D.D0 wb_dati_5_1_iv_0_0_a2[6]
CTOF_DEL --- 0.495 R3C4D.D0 to R3C4D.F0 SLICE_81
ROUTE 1 1.299 R3C4D.F0 to R2C5B.A0 wb_dati_5_1_iv_0_0_1[6]
CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55
ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c)
--------
9.024 (32.4% logic, 67.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R6C4B.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R2C5B.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.148ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[9] (from RCLK_c +)
Destination: FF Data in wb_dati[1] (to RCLK_c +)
Delay: 8.686ns (33.7% logic, 66.3% route), 6 logic levels.
Constraint Details:
8.686ns physical path delay SLICE_5 to SLICE_52 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 7.148ns
Physical Path Details:
Data path SLICE_5 to SLICE_52:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C3B.CLK to R6C3B.Q0 SLICE_5 (from RCLK_c)
ROUTE 17 1.867 R6C3B.Q0 to R4C4C.B1 FS[9]
CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_97
ROUTE 3 0.643 R4C4C.F1 to R4C4C.D0 wb_dati_5_1_iv_0_o2_0[7]
CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_97
ROUTE 1 0.967 R4C4C.F0 to R4C4A.A0 wb_dati_5_1_iv_0_a2_0_2[1]
CTOF_DEL --- 0.495 R4C4A.A0 to R4C4A.F0 SLICE_64
ROUTE 1 1.535 R4C4A.F0 to R2C4B.B0 wb_dati_5_1_iv_0_0[1]
CTOF_DEL --- 0.495 R2C4B.B0 to R2C4B.F0 SLICE_85
ROUTE 1 0.747 R2C4B.F0 to R2C4C.C1 wb_dati_5_1_iv_0_1[1]
CTOF_DEL --- 0.495 R2C4C.C1 to R2C4C.F1 SLICE_52
ROUTE 1 0.000 R2C4C.F1 to R2C4C.DI1 wb_dati_5[1] (to RCLK_c)
--------
8.686 (33.7% logic, 66.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R6C3B.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_52:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R2C4C.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.149ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in wb_dati[6] (to RCLK_c +)
Delay: 8.685ns (33.7% logic, 66.3% route), 6 logic levels.
Constraint Details:
8.685ns physical path delay SLICE_2 to SLICE_55 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 7.149ns
Physical Path Details:
Data path SLICE_2 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4A.CLK to R6C4A.Q0 SLICE_2 (from RCLK_c)
ROUTE 6 1.390 R6C4A.Q0 to R4C4A.B1 FS[15]
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 SLICE_64
ROUTE 12 1.800 R4C4A.F1 to R3C4A.A1 FS_RNIHVJI[15]
CTOF_DEL --- 0.495 R3C4A.A1 to R3C4A.F1 SLICE_84
ROUTE 4 0.643 R3C4A.F1 to R3C4A.D0 wb_dati_5_1_iv_0_a2_13[3]
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 SLICE_84
ROUTE 1 0.626 R3C4A.F0 to R3C4D.D0 wb_dati_5_1_iv_0_0_a2[6]
CTOF_DEL --- 0.495 R3C4D.D0 to R3C4D.F0 SLICE_81
ROUTE 1 1.299 R3C4D.F0 to R2C5B.A0 wb_dati_5_1_iv_0_0_1[6]
CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55
ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c)
--------
8.685 (33.7% logic, 66.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R6C4A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R2C5B.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.154ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in wb_dati[4] (to RCLK_c +)
Delay: 8.680ns (33.7% logic, 66.3% route), 6 logic levels.
Constraint Details:
8.680ns physical path delay SLICE_1 to SLICE_54 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 7.154ns
Physical Path Details:
Data path SLICE_1 to SLICE_54:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4B.CLK to R6C4B.Q0 SLICE_1 (from RCLK_c)
ROUTE 7 1.729 R6C4B.Q0 to R4C4A.C1 FS[17]
CTOF_DEL --- 0.495 R4C4A.C1 to R4C4A.F1 SLICE_64
ROUTE 12 1.019 R4C4A.F1 to R2C3B.D1 FS_RNIHVJI[15]
CTOF_DEL --- 0.495 R2C3B.D1 to R2C3B.F1 SLICE_87
ROUTE 4 0.994 R2C3B.F1 to R3C4D.D1 wb_dati_5_1_iv_0_a2_12[3]
CTOF_DEL --- 0.495 R3C4D.D1 to R3C4D.F1 SLICE_81
ROUTE 2 1.010 R3C4D.F1 to R3C3A.B0 wb_dati_5_1_iv_0_a2_2[4]
CTOF_DEL --- 0.495 R3C3A.B0 to R3C3A.F0 SLICE_111
ROUTE 1 1.001 R3C3A.F0 to R2C3D.B0 wb_dati_5_1_iv_0_0_1[4]
CTOF_DEL --- 0.495 R2C3D.B0 to R2C3D.F0 SLICE_54
ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_dati_5[4] (to RCLK_c)
--------
8.680 (33.7% logic, 66.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R6C4B.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_54:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R2C3D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.228ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 8.433ns (51.3% logic, 48.7% route), 5 logic levels.
Constraint Details:
8.433ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets
16.000ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 15.661ns) by 7.228ns
Physical Path Details:
Data path ufmefb/EFBInst_0 to SLICE_30:
Name Fanout Delay (ns) Site Resource
WCLKI2WBAC --- 2.343 EFB.WBCLKI to EFB.WBACKO ufmefb/EFBInst_0 (from RCLK_c)
ROUTE 2 1.504 EFB.WBACKO to R3C5C.C0 wb_ack
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_102
ROUTE 1 0.315 R3C5C.F0 to R3C5B.D0 ufmefb/g0_0_a3_2
CTOF_DEL --- 0.495 R3C5B.D0 to R3C5B.F0 SLICE_66
ROUTE 1 1.278 R3C5B.F0 to R4C6D.C1 N_4
CTOF_DEL --- 0.495 R4C6D.C1 to R4C6D.F1 SLICE_45
ROUTE 2 1.013 R4C6D.F1 to R4C6B.B0 un1_FS_38_i
CTOF_DEL --- 0.495 R4C6B.B0 to R4C6B.F0 SLICE_30
ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 LEDENe_0 (to RCLK_c)
--------
8.433 (51.3% logic, 48.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.192 63.PADDI to EFB.WBCLKI RCLK_c
--------
2.192 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R4C6B.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.241ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS[1] (from RCLK_c +)
Destination: FF Data in nRCAS_0io (to RCLK_c +)
Delay: 8.779ns (33.3% logic, 66.7% route), 6 logic levels.
Constraint Details:
8.779ns physical path delay SLICE_27 to nRCAS_MGIOL meets
16.000ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 16.020ns) by 7.241ns
Physical Path Details:
Data path SLICE_27 to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C14D.CLK to R4C14D.Q0 SLICE_27 (from RCLK_c)
ROUTE 7 1.433 R4C14D.Q0 to R5C14C.B1 IS[1]
CTOF_DEL --- 0.495 R5C14C.B1 to R5C14C.F1 SLICE_83
ROUTE 3 0.673 R5C14C.F1 to R5C14D.A0 un1_nRCAS_6_sqmuxa_i_o2
CTOF_DEL --- 0.495 R5C14D.A0 to R5C14D.F0 SLICE_62
ROUTE 2 0.967 R5C14D.F0 to R6C13C.D0 N_48
CTOF_DEL --- 0.495 R6C13C.D0 to R6C13C.F0 SLICE_69
ROUTE 1 0.436 R6C13C.F0 to R6C13C.C1 nRCS_9_u_i_o3_0_0
CTOF_DEL --- 0.495 R6C13C.C1 to R6C13C.F1 SLICE_69
ROUTE 1 0.744 R6C13C.F1 to R6C14C.C1 nRCS_9_u_i_o3_0_2
CTOF_DEL --- 0.495 R6C14C.C1 to R6C14C.F1 SLICE_101
ROUTE 1 1.599 R6C14C.F1 to IOL_R7C.OPOS N_251_i (to RCLK_c)
--------
8.779 (33.3% logic, 66.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.019 63.PADDI to R4C14D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.192 63.PADDI to IOL_R7C.CLK RCLK_c
--------
2.192 (0.0% logic, 100.0% route), 0 logic levels.
Report: 102.312MHz is the maximum frequency for this preference.
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.068 MHz| 5
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage)
--------------------------------------------------------------------------------
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Nov 18 02:06:11 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 147 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
147 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in C1Submitted (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_11 to SLICE_11 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_11 to SLICE_11:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_11 (from PHI2_c)
ROUTE 2 0.132 R5C8D.Q0 to R5C8D.A0 C1Submitted
CTOF_DEL --- 0.101 R5C8D.A0 to R5C8D.F0 SLICE_11
ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 C1Submitted_RNO (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdUFMShift (from PHI2_c -)
Destination: FF Data in CmdUFMShift (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_20 to SLICE_20 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C9A.CLK to R4C9A.Q0 SLICE_20 (from PHI2_c)
ROUTE 2 0.132 R4C9A.Q0 to R4C9A.A0 CmdUFMShift
CTOF_DEL --- 0.101 R4C9A.A0 to R4C9A.F0 SLICE_20
ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 CmdUFMShift_3 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R4C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R4C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.382ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels.
Constraint Details:
0.369ns physical path delay SLICE_10 to SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.382ns
Physical Path Details:
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C7C.CLK to R5C7C.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 0.135 R5C7C.Q0 to R5C7C.D0 ADSubmitted
CTOF_DEL --- 0.101 R5C7C.D0 to R5C7C.F0 SLICE_10
ROUTE 1 0.000 R5C7C.F0 to R5C7C.DI0 ADSubmitted_r_0_0 (to PHI2_c)
--------
0.369 (63.4% logic, 36.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C7C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C7C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.471ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.458ns (51.1% logic, 48.9% route), 2 logic levels.
Constraint Details:
0.458ns physical path delay SLICE_17 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.471ns
Physical Path Details:
Data path SLICE_17 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q0 SLICE_17 (from PHI2_c)
ROUTE 2 0.224 R5C8C.Q0 to R5C8C.B0 CmdEnable
CTOF_DEL --- 0.101 R5C8C.B0 to R5C8C.F0 SLICE_17
ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c)
--------
0.458 (51.1% logic, 48.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.613ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.600ns (55.8% logic, 44.2% route), 3 logic levels.
Constraint Details:
0.600ns physical path delay SLICE_11 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.613ns
Physical Path Details:
Data path SLICE_11 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_11 (from PHI2_c)
ROUTE 2 0.212 R5C8D.Q0 to R5C8B.A0 C1Submitted
CTOF_DEL --- 0.101 R5C8B.A0 to R5C8B.F0 SLICE_76
ROUTE 1 0.053 R5C8B.F0 to R5C8C.D0 un1_CmdEnable20_i
CTOF_DEL --- 0.101 R5C8C.D0 to R5C8C.F0 SLICE_17
ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c)
--------
0.600 (55.8% logic, 44.2% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.616ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdLEDEN (from PHI2_c -)
Destination: FF Data in CmdLEDEN (to PHI2_c -)
Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
Constraint Details:
0.603ns physical path delay SLICE_18 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.616ns
Physical Path Details:
Data path SLICE_18 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C8C.CLK to R4C8C.Q0 SLICE_18 (from PHI2_c)
ROUTE 2 0.212 R4C8C.Q0 to R4C8C.A1 CmdLEDEN
CTOF_DEL --- 0.101 R4C8C.A1 to R4C8C.F1 SLICE_18
ROUTE 1 0.056 R4C8C.F1 to R4C8C.C0 CmdLEDEN_4_u_i_m2_i_0
CTOF_DEL --- 0.101 R4C8C.C0 to R4C8C.F0 SLICE_18
ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 N_17_i (to PHI2_c)
--------
0.603 (55.6% logic, 44.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R4C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R4C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.616ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Cmdn8MEGEN (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
Constraint Details:
0.603ns physical path delay SLICE_24 to SLICE_24 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.616ns
Physical Path Details:
Data path SLICE_24 to SLICE_24:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C8D.CLK to R4C8D.Q0 SLICE_24 (from PHI2_c)
ROUTE 2 0.212 R4C8D.Q0 to R4C8D.A1 Cmdn8MEGEN
CTOF_DEL --- 0.101 R4C8D.A1 to R4C8D.F1 SLICE_24
ROUTE 1 0.056 R4C8D.F1 to R4C8D.C0 Cmdn8MEGEN_4_u_i_m2_i_0
CTOF_DEL --- 0.101 R4C8D.C0 to R4C8D.F0 SLICE_24
ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 N_15_i (to PHI2_c)
--------
0.603 (55.6% logic, 44.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R4C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R4C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.616ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q XOR8MEG (from PHI2_c -)
Destination: FF Data in XOR8MEG (to PHI2_c -)
Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
Constraint Details:
0.603ns physical path delay SLICE_44 to SLICE_44 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.616ns
Physical Path Details:
Data path SLICE_44 to SLICE_44:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C9C.CLK to R5C9C.Q0 SLICE_44 (from PHI2_c)
ROUTE 2 0.212 R5C9C.Q0 to R5C9C.A1 XOR8MEG
CTOF_DEL --- 0.101 R5C9C.A1 to R5C9C.F1 SLICE_44
ROUTE 1 0.056 R5C9C.F1 to R5C9C.C0 N_411
CTOF_DEL --- 0.101 R5C9C.C0 to R5C9C.F0 SLICE_44
ROUTE 1 0.000 R5C9C.F0 to R5C9C.DI0 XOR8MEG_3 (to PHI2_c)
--------
0.603 (55.6% logic, 44.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_44:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C9C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_44:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C9C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.628ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdUFMShift (to PHI2_c -)
Delay: 0.600ns (39.0% logic, 61.0% route), 2 logic levels.
Constraint Details:
0.600ns physical path delay SLICE_17 to SLICE_20 meets
-0.028ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.028ns) by 0.628ns
Physical Path Details:
Data path SLICE_17 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q0 SLICE_17 (from PHI2_c)
ROUTE 2 0.213 R5C8C.Q0 to R4C8A.A1 CmdEnable
CTOF_DEL --- 0.101 R4C8A.A1 to R4C8A.F1 SLICE_23
ROUTE 8 0.153 R4C8A.F1 to R4C9A.CE XOR8MEG18 (to PHI2_c)
--------
0.600 (39.0% logic, 61.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R4C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.628ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdUFMWrite (from PHI2_c -)
Destination: FF Data in CmdUFMWrite (to PHI2_c -)
Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels.
Constraint Details:
0.615ns physical path delay SLICE_21 to SLICE_21 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.628ns
Physical Path Details:
Data path SLICE_21 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C8B.CLK to R4C8B.Q0 SLICE_21 (from PHI2_c)
ROUTE 2 0.224 R4C8B.Q0 to R4C8B.B1 CmdUFMWrite
CTOF_DEL --- 0.101 R4C8B.B1 to R4C8B.F1 SLICE_21
ROUTE 1 0.056 R4C8B.F1 to R4C8B.C0 N_415
CTOF_DEL --- 0.101 R4C8B.C0 to R4C8B.F0 SLICE_21
ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 CmdUFMWrite_3 (to PHI2_c)
--------
0.615 (54.5% logic, 45.5% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R4C8B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.240 8.PADDI to R4C8B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
891 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_12 to SLICE_12 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C8B.CLK to R6C8B.Q0 SLICE_12 (from RCLK_c)
ROUTE 1 0.152 R6C8B.Q0 to R6C8B.M1 CASr (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R6C8B.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R6C8B.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr (from RCLK_c +)
Destination: FF Data in RASr2 (to RCLK_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_32 to SLICE_32 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_32 to SLICE_32:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q0 SLICE_32 (from RCLK_c)
ROUTE 2 0.154 R5C13C.Q0 to R5C13C.M1 RASr (to RCLK_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R5C13C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R5C13C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.311ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PHI2r2 (from RCLK_c +)
Destination: FF Data in PHI2r3 (to RCLK_c +)
Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels.
Constraint Details:
0.292ns physical path delay SLICE_31 to SLICE_31 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.311ns
Physical Path Details:
Data path SLICE_31 to SLICE_31:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C7D.CLK to R4C7D.Q0 SLICE_31 (from RCLK_c)
ROUTE 5 0.159 R4C7D.Q0 to R4C7D.M1 PHI2r2 (to RCLK_c)
--------
0.292 (45.5% logic, 54.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R4C7D.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R4C7D.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.318ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_adr[7] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.304ns (43.8% logic, 56.3% route), 1 logic levels.
Constraint Details:
0.304ns physical path delay SLICE_50 to ufmefb/EFBInst_0 meets
-0.068ns WBADRI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.014ns) by 0.318ns
Physical Path Details:
Data path SLICE_50 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C2B.CLK to R2C2B.Q1 SLICE_50 (from RCLK_c)
ROUTE 1 0.171 R2C2B.Q1 to EFB.WBADRI7 wb_adr[7] (to RCLK_c)
--------
0.304 (43.8% logic, 56.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_50:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R2C2B.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c
--------
0.705 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.333ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_adr[2] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels.
Constraint Details:
0.306ns physical path delay SLICE_48 to ufmefb/EFBInst_0 meets
-0.081ns WBADRI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.027ns) by 0.333ns
Physical Path Details:
Data path SLICE_48 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q0 SLICE_48 (from RCLK_c)
ROUTE 2 0.173 R2C2C.Q0 to EFB.WBADRI2 wb_adr[2] (to RCLK_c)
--------
0.306 (43.5% logic, 56.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R2C2C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c
--------
0.705 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.347ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_dati[3] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels.
Constraint Details:
0.306ns physical path delay SLICE_53 to ufmefb/EFBInst_0 meets
-0.095ns WBDATI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.041ns) by 0.347ns
Physical Path Details:
Data path SLICE_53 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C3C.CLK to R2C3C.Q1 SLICE_53 (from RCLK_c)
ROUTE 2 0.173 R2C3C.Q1 to EFB.WBDATI3 wb_dati[3] (to RCLK_c)
--------
0.306 (43.5% logic, 56.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_53:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R2C3C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c
--------
0.705 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.350ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_dati[4] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels.
Constraint Details:
0.307ns physical path delay SLICE_54 to ufmefb/EFBInst_0 meets
-0.097ns WBDATI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.043ns) by 0.350ns
Physical Path Details:
Data path SLICE_54 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C3D.CLK to R2C3D.Q0 SLICE_54 (from RCLK_c)
ROUTE 2 0.174 R2C3D.Q0 to EFB.WBDATI4 wb_dati[4] (to RCLK_c)
--------
0.307 (43.3% logic, 56.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_54:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R2C3D.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c
--------
0.705 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.355ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr2 (from RCLK_c +)
Destination: FF Data in S[1] (to RCLK_c +)
Delay: 0.298ns (44.6% logic, 55.4% route), 1 logic levels.
Constraint Details:
0.298ns physical path delay SLICE_32 to SLICE_43 meets
-0.057ns LSR_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.057ns) by 0.355ns
Physical Path Details:
Data path SLICE_32 to SLICE_43:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q1 SLICE_32 (from RCLK_c)
ROUTE 10 0.165 R5C13C.Q1 to R5C13B.LSR RASr2 (to RCLK_c)
--------
0.298 (44.6% logic, 55.4% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R5C13C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_43:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R5C13B.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.358ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_adr[3] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels.
Constraint Details:
0.307ns physical path delay SLICE_48 to ufmefb/EFBInst_0 meets
-0.105ns WBADRI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.051ns) by 0.358ns
Physical Path Details:
Data path SLICE_48 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q1 SLICE_48 (from RCLK_c)
ROUTE 2 0.174 R2C2C.Q1 to EFB.WBADRI3 wb_adr[3] (to RCLK_c)
--------
0.307 (43.3% logic, 56.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R2C2C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c
--------
0.705 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[0] (from RCLK_c +)
Destination: FF Data in FS[0] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C2A.CLK to R6C2A.Q1 SLICE_0 (from RCLK_c)
ROUTE 3 0.132 R6C2A.Q1 to R6C2A.A1 FS[0]
CTOF_DEL --- 0.101 R6C2A.A1 to R6C2A.F1 SLICE_0
ROUTE 1 0.000 R6C2A.F1 to R6C2A.DI1 FS_s[0] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R6C2A.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.651 63.PADDI to R6C2A.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage)
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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