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204 lines
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<HEAD><TITLE>I/O Timing Report</TITLE>
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body,pre{
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color: #000000;
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font-size:88%;
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background-color: #ffffff;
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}
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h1 {
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font-weight: bold;
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margin-top: 24px;
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border-bottom: 3px solid #000; font-size: 1em;
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}
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h2 {
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font-weight: bold;
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margin-top: 18px;
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margin-bottom: 5px;
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font-size: 0.90em;
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}
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h3 {
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font-weight: bold;
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margin-top: 12px;
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margin-bottom: 5px;
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font-size: 0.80em;
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}
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p {
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font-size:78%;
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}
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P.Table {
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margin-top: 4px;
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margin-bottom: 4px;
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margin-right: 4px;
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margin-left: 4px;
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}
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table
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{
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border-width: 1px 1px 1px 1px;
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border-style: solid solid solid solid;
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border-color: black black black black;
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border-collapse: collapse;
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}
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th {
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font-weight:bold;
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padding: 4px;
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border-width: 1px 1px 1px 1px;
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border-style: solid solid solid solid;
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border-color: black black black black;
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vertical-align:top;
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text-align:left;
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font-size:78%;
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}
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td {
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padding: 4px;
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border-width: 1px 1px 1px 1px;
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border-style: solid solid solid solid;
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border-color: black black black black;
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vertical-align:top;
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font-size:78%;
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}
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a {
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color:#013C9A;
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text-decoration:none;
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}
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a:visited {
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color:#013C9A;
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}
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a:hover, a:active {
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text-decoration:underline;
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color:#5BAFD4;
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}
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.pass
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{
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background-color: #00ff00;
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}
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.fail
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{
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background-color: #ff0000;
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}
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.comment
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{
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font-size: 90%;
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font-style: italic;
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}
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<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
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Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO256C
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Package: TQFP100
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Performance: 4
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Package Status: Final Version 1.19.
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Performance Hardware Data Status: Version 1.124.
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Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO256C
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Package: TQFP100
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Performance: 5
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Package Status: Final Version 1.19.
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Performance Hardware Data Status: Version 1.124.
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Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO256C
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Package: TQFP100
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Performance: M
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Package Status: Final Version 1.19.
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Performance Hardware Data Status: Version 1.124.
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// Design: RAM2GS
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// Package: TQFP100
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// ncd File: ram2gs_lcmxo256c_impl1.ncd
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// Version: Diamond (64-bit) 3.12.1.454
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// Written on Tue Aug 15 05:03:30 2023
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// M: Minimum Performance Grade
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// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
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I/O Timing Report (All units are in ns)
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Worst Case Results across Performance Grades (M, 5, 4, 3):
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// Input Setup and Hold Times
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Port Clock Edge Setup Performance_Grade Hold Performance_Grade
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----------------------------------------------------------------------
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CROW[0] nCRAS F -0.006 M 1.907 3
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CROW[1] nCRAS F -0.006 M 1.907 3
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Din[0] PHI2 F 5.992 3 2.081 3
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Din[0] nCCAS F 1.591 3 -0.045 M
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Din[1] PHI2 F 5.388 3 2.863 3
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Din[1] nCCAS F 0.231 3 0.973 3
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Din[2] PHI2 F 4.913 3 2.842 3
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Din[2] nCCAS F 0.265 3 1.112 3
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Din[3] PHI2 F 6.776 3 2.065 3
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Din[3] nCCAS F 0.702 3 0.725 3
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Din[4] PHI2 F 4.191 3 1.807 3
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Din[4] nCCAS F 1.107 3 0.235 3
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Din[5] PHI2 F 7.709 3 0.737 3
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Din[5] nCCAS F 1.192 3 0.184 3
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Din[6] PHI2 F 6.617 3 1.159 3
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Din[6] nCCAS F 0.904 3 0.149 3
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Din[7] PHI2 F 6.864 3 1.300 3
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Din[7] nCCAS F 0.531 3 0.451 3
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MAin[0] PHI2 F 4.802 3 1.029 3
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MAin[0] nCRAS F 1.511 3 0.599 3
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MAin[1] PHI2 F 4.513 3 1.653 3
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MAin[1] nCRAS F 0.340 3 1.609 3
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MAin[2] PHI2 F 4.241 3 1.193 3
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MAin[2] nCRAS F 1.248 3 0.814 3
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MAin[3] PHI2 F 6.748 3 -0.221 M
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MAin[3] nCRAS F 0.375 3 1.589 3
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MAin[4] PHI2 F 7.111 3 -0.295 M
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MAin[4] nCRAS F -0.038 M 2.031 3
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MAin[5] PHI2 F 4.083 3 1.319 3
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MAin[5] nCRAS F -0.126 M 2.320 3
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MAin[6] PHI2 F 8.738 3 -0.639 M
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MAin[6] nCRAS F 0.505 3 1.464 3
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MAin[7] PHI2 F 7.566 3 -0.400 M
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MAin[7] nCRAS F 0.390 3 1.577 3
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MAin[8] nCRAS F -0.017 M 1.932 3
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MAin[9] nCRAS F 1.390 3 0.679 3
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PHI2 RCLK R 4.721 3 -0.539 M
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UFMSDO RCLK R 2.307 3 -0.173 M
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nCCAS RCLK R 3.513 3 -0.441 M
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nCCAS nCRAS F 1.800 3 0.388 3
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nCRAS RCLK R 1.107 3 0.266 3
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nFWE PHI2 F 4.160 3 1.763 3
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nFWE nCRAS F 0.864 3 1.164 3
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// Clock to Output Delay
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Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
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------------------------------------------------------------------------
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LED RCLK R 7.020 3 1.411 M
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LED nCRAS F 10.053 3 2.020 M
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RA[0] RCLK R 8.511 3 1.707 M
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RA[0] nCRAS F 10.448 3 2.067 M
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RA[10] RCLK R 7.422 3 1.486 M
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RA[11] PHI2 R 8.233 3 1.633 M
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RA[1] RCLK R 8.292 3 1.649 M
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RA[1] nCRAS F 10.175 3 2.009 M
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RA[2] RCLK R 8.708 3 1.746 M
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RA[2] nCRAS F 10.512 3 2.079 M
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RA[3] RCLK R 6.982 3 1.404 M
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RA[3] nCRAS F 8.753 3 1.739 M
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RA[4] RCLK R 6.982 3 1.404 M
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RA[4] nCRAS F 9.764 3 1.953 M
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RA[5] RCLK R 6.982 3 1.404 M
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RA[5] nCRAS F 10.635 3 2.140 M
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RA[6] RCLK R 9.127 3 1.839 M
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RA[6] nCRAS F 10.861 3 2.160 M
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RA[7] RCLK R 8.287 3 1.659 M
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RA[7] nCRAS F 10.995 3 2.202 M
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RA[8] RCLK R 8.834 3 1.776 M
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RA[8] nCRAS F 10.930 3 2.181 M
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RA[9] RCLK R 6.729 3 1.353 M
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RA[9] nCRAS F 10.423 3 2.088 M
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RBA[0] nCRAS F 7.746 3 1.538 M
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RBA[1] nCRAS F 9.473 3 1.887 M
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RCKE RCLK R 8.348 3 1.695 M
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RDQMH RCLK R 7.433 3 1.503 M
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RDQML RCLK R 9.061 3 1.821 M
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RD[0] nCCAS F 6.791 3 1.468 M
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RD[1] nCCAS F 7.502 3 1.596 M
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RD[2] nCCAS F 9.015 3 1.924 M
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RD[3] nCCAS F 8.919 3 1.901 M
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RD[4] nCCAS F 7.500 3 1.596 M
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RD[5] nCCAS F 6.791 3 1.468 M
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RD[6] nCCAS F 7.950 3 1.703 M
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RD[7] nCCAS F 7.871 3 1.681 M
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UFMCLK RCLK R 7.767 3 1.567 M
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UFMSDI RCLK R 5.675 3 1.141 M
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nRCAS RCLK R 6.518 3 1.300 M
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nRCS RCLK R 5.675 3 1.141 M
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nRRAS RCLK R 7.469 3 1.503 M
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nRWE RCLK R 5.675 3 1.141 M
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nUFMCS RCLK R 7.873 3 1.593 M
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WARNING: you must also run trce with hold speed: 3
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WARNING: you must also run trce with setup speed: M
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