mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-30 03:49:42 +00:00
156 lines
4.5 KiB
Plaintext
156 lines
4.5 KiB
Plaintext
|
|
Copyright (C) 1994-2021 Synopsys, Inc.
|
|
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
|
|
Build: R-2021.03L-SP1
|
|
Install: C:\lscc\diamond\3.12\synpbase
|
|
OS: Windows 6.2
|
|
|
|
Hostname: ZANEMACWIN11
|
|
|
|
Implementation : impl1
|
|
|
|
# Written on Sat Aug 19 20:57:08 2023
|
|
|
|
##### DESIGN INFO #######################################################
|
|
|
|
Top View: "RAM2GS"
|
|
Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
|
|
|
|
|
|
|
|
|
##### SUMMARY ############################################################
|
|
|
|
Found 0 issues in 0 out of 4 constraints
|
|
|
|
|
|
##### DETAILS ############################################################
|
|
|
|
|
|
|
|
Clock Relationships
|
|
*******************
|
|
|
|
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
|
|
-----------------------------------------------------------------------------------------------------------------------------------
|
|
RCLK RCLK | 16.000 | No paths | No paths | No paths
|
|
RCLK PHI2 | 2.000 | No paths | 1.000 | No paths
|
|
RCLK nCRAS | No paths | No paths | 1.000 | No paths
|
|
PHI2 RCLK | No paths | No paths | No paths | 1.000
|
|
PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000
|
|
nCRAS RCLK | No paths | No paths | No paths | 1.000
|
|
===================================================================================================================================
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
|
|
|
|
|
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
|
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
|
|
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
|
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
|
|
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
|
|
|
|
|
|
Unconstrained Start/End Points
|
|
******************************
|
|
|
|
p:CROW[0]
|
|
p:CROW[1]
|
|
p:Din[0]
|
|
p:Din[1]
|
|
p:Din[2]
|
|
p:Din[3]
|
|
p:Din[4]
|
|
p:Din[5]
|
|
p:Din[6]
|
|
p:Din[7]
|
|
p:Dout[0]
|
|
p:Dout[1]
|
|
p:Dout[2]
|
|
p:Dout[3]
|
|
p:Dout[4]
|
|
p:Dout[5]
|
|
p:Dout[6]
|
|
p:Dout[7]
|
|
p:MAin[0]
|
|
p:MAin[1]
|
|
p:MAin[2]
|
|
p:MAin[3]
|
|
p:MAin[4]
|
|
p:MAin[5]
|
|
p:MAin[6]
|
|
p:MAin[7]
|
|
p:MAin[8]
|
|
p:MAin[9]
|
|
p:RA[0]
|
|
p:RA[1]
|
|
p:RA[2]
|
|
p:RA[3]
|
|
p:RA[4]
|
|
p:RA[5]
|
|
p:RA[6]
|
|
p:RA[7]
|
|
p:RA[8]
|
|
p:RA[9]
|
|
p:RA[10]
|
|
p:RA[11]
|
|
p:RBA[0]
|
|
p:RBA[1]
|
|
p:RCKE
|
|
p:RDQMH
|
|
p:RDQML
|
|
p:RD[0] (bidir end point)
|
|
p:RD[0] (bidir start point)
|
|
p:RD[1] (bidir end point)
|
|
p:RD[1] (bidir start point)
|
|
p:RD[2] (bidir end point)
|
|
p:RD[2] (bidir start point)
|
|
p:RD[3] (bidir end point)
|
|
p:RD[3] (bidir start point)
|
|
p:RD[4] (bidir end point)
|
|
p:RD[4] (bidir start point)
|
|
p:RD[5] (bidir end point)
|
|
p:RD[5] (bidir start point)
|
|
p:RD[6] (bidir end point)
|
|
p:RD[6] (bidir start point)
|
|
p:RD[7] (bidir end point)
|
|
p:RD[7] (bidir start point)
|
|
p:UFMCLK
|
|
p:UFMSDI
|
|
p:UFMSDO
|
|
p:nFWE
|
|
p:nRCAS
|
|
p:nRCS
|
|
p:nRRAS
|
|
p:nRWE
|
|
p:nUFMCS
|
|
|
|
|
|
Inapplicable constraints
|
|
************************
|
|
|
|
(none)
|
|
|
|
|
|
Applicable constraints with issues
|
|
**********************************
|
|
|
|
(none)
|
|
|
|
|
|
Constraints with matching wildcard expressions
|
|
**********************************************
|
|
|
|
(none)
|
|
|
|
|
|
Library Report
|
|
**************
|
|
|
|
|
|
# End of Constraint Checker Report
|