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RAM2GS/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html
Zane Kaminski a59177004e MAX, MachXO, MachXO2 working
2023-08-20 07:10:11 -04:00

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<HTML> <HEAD><TITLE></TITLE> <STYLE TYPE="text/css"> <!-- body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; } --> </STYLE> </HEAD> <BODY> <PRE>Setting log file to 'Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
(VERI-1482) Analyzing Verilog file 'Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v'
INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-410,10) (VERI-9000) elaborating module 'RAM2GS'
Done: design load finished with (0) errors, and (0) warnings
</PRE></BODY></HTML>
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