RAM2GS/CPLD/LCMXO640C/impl1/run_options.txt
2023-08-20 07:10:11 -04:00

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#-- Synopsys, Inc.
#-- Version R-2021.03L-SP1
#-- Project file Y:\Repos\RAM2GS\CPLD\LCMXO640C\impl1\run_options.txt
#-- Written on Sat Aug 19 20:57:05 2023
#project files
add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-SPI.v"
#implementation: "impl1"
impl -add impl1 -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 3
set_option -project_relative_includes 1
set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO640C}
#device options
set_option -technology MACHXO
set_option -part LCMXO640C
set_option -package T100C
set_option -speed_grade -3
set_option -part_companion ""
#compilation/mapping options
set_option -top_module "RAM2GS"
# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0
# mapper_without_write_options
set_option -frequency 70
set_option -srs_instrumentation 1
# mapper_options
set_option -write_verilog 0
set_option -write_structural_verilog 0
set_option -write_vhdl 0
# Lattice XP
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 0
set_option -forcegsr auto
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
set_option -syn_edif_array_rename 1
set_option -Write_declared_clocks_only 1
set_option -seqshift_no_replicate 0
# NFilter
set_option -no_sequential_opt 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./RAM2GS_LCMXO640C_impl1.edi"
#set log file
set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srf"
impl -active "impl1"