Initial checkin

This commit is contained in:
Shawn Quick 2021-10-19 13:55:19 -07:00
parent 892fd36e44
commit c1f2cdae37
4 changed files with 92 additions and 0 deletions

816.vhdl Normal file
View File

@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all;
entity teensy816 is
port (
FPGA_REGADDR: in std_logic;
FPGA_REGRW: in std_logic;
FPGA_DATA: inout std_logic_vector (7 downto 0);
FPGA_BUSY: out std_logic;
FPGA_CLK: in std_logic;
FPGA_DBUS_FAKE: in std_logic_vector (7 downto 0);
CPU_ABUS: out std_logic_vector (15 downto 0);
CPU_DBUS: inout std_logic_vector (7 downto 0);
CPU_ABORT: in std_logic;
CPU_BE: in std_logic;
CPU_ESTATUS: out std_logic;
CPU_IRQ: in std_logic;
CPU_MLOCK: out std_logic;
CPU_MX: out std_logic;
CPU_NMI: in std_logic;
CPU_CLK: in std_logic;
CPU_RW: out std_logic;
CPU_RDY: inout std_logic;
CPU_RESET: in std_logic;
CPU_VDA: out std_logic;
CPU_VPA: out std_logic;
CPU_VPB: out std_logic
end teensy816;
architecture rtl of teensy816 is
CPU_DBUS <= FPGA_DATA when (CPU_BE = '1') else (others => 'Z');
CPU_ABUS <= FPGA_ABUS when (CPU_BE = '1') else (others => 'Z');
end rtl;

Makefile Normal file
View File

@ -0,0 +1,11 @@
all: 816.o
816.o: 816.vhdl
ghdl -i 816.vhdl
ghdl -m teensy816
ghdl --clean

View File

@ -1,2 +1,7 @@
# Teensy816
A Teensy 4.1 based board with onboard FPGA to allow direct access to a W65816 based computer.
The initial version will be tailored to the Apple //gs.
I can't guarantee that this will go anywhere, but the idea is to create a board that will allow a 600MHz Teensy 4.1 board to read/write memory and I/O locations directly from the GS motherboard, and simulate the 65816 processor in realtime. Running at 600Mhz, the CPU on the teensy is expected to be able to accelerate the system by at least a factor of 10x.
Additionally, by using on board RAM from the Teensy, a simulated 8GB memory card would be added to the system.
Eventually, the plan would be to add a larger or second FPGA that would mirror the GS's video memory, and provide an HDMI output for all supported video modes.

ideas.txt Normal file
View File

@ -0,0 +1,38 @@
FPGA_REGADDR=0 allows CPU to write to an internal register (8 bit) that is the address
of the internal register to read when FPGA_REGADDR=1. This allows a single bit to be used instead
of 8 bits for address info on a read/write. REGADDR will increment on each read/write so
successive reads/writes will write to the next register address, and REGADDR will not need to be
FPGA data bus -8
FPGA_RW - read or write to data bus
FPGA internal registers
command: offset 0 (len 4, only LSB = command, others reserved (0), could be used to identify motherboard
memory, or vram memory, etc. Different busses.
data: offset 4 len 4 (to support 32 bit processors)
addr: offset 8 len 4 (to support 32 bit addressing)
mode: offset 12 len 4 (perhaps video mode, CPU type, etc)
FPGA command register - 8
FPGA commands
load a23
load a16
load a8
load a0
load D23
load D16
load D8
load D0
read d32
read d16
read d8
read d0