39 lines
1.1 KiB
VHDL
39 lines
1.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity teensy816 is
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port (
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FPGA_REGADDR: in std_logic;
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FPGA_REGRW: in std_logic;
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FPGA_DATA: inout std_logic_vector (7 downto 0);
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FPGA_BUSY: out std_logic;
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FPGA_CLK: in std_logic;
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FPGA_DBUS_FAKE: in std_logic_vector (7 downto 0);
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CPU_ABUS: out std_logic_vector (15 downto 0);
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CPU_DBUS: inout std_logic_vector (7 downto 0);
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CPU_ABORT: in std_logic;
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CPU_BE: in std_logic;
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CPU_ESTATUS: out std_logic;
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CPU_IRQ: in std_logic;
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CPU_MLOCK: out std_logic;
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CPU_MX: out std_logic;
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CPU_NMI: in std_logic;
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CPU_CLK: in std_logic;
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CPU_RW: out std_logic;
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CPU_RDY: inout std_logic;
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CPU_RESET: in std_logic;
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CPU_VDA: out std_logic;
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CPU_VPA: out std_logic;
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CPU_VPB: out std_logic
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);
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end teensy816;
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architecture rtl of teensy816 is
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begin
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CPU_RW <= FPGA_REGRW;
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CPU_DBUS <= FPGA_DATA when (CPU_BE = '1') else (others => 'Z');
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CPU_ABUS <= FPGA_ABUS when (CPU_BE = '1') else (others => 'Z');
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end rtl;
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