39 lines
983 B
Plaintext
39 lines
983 B
Plaintext
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FPGA_REGADDR=0 allows CPU to write to an internal register (8 bit) that is the address
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of the internal register to read when FPGA_REGADDR=1. This allows a single bit to be used instead
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of 8 bits for address info on a read/write. REGADDR will increment on each read/write so
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successive reads/writes will write to the next register address, and REGADDR will not need to be
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updated.
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FPGA data bus -8
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FPGA_RW - read or write to data bus
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FPGA internal registers
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command: offset 0 (len 4, only LSB = command, others reserved (0), could be used to identify motherboard
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memory, or vram memory, etc. Different busses.
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data: offset 4 len 4 (to support 32 bit processors)
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addr: offset 8 len 4 (to support 32 bit addressing)
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mode: offset 12 len 4 (perhaps video mode, CPU type, etc)
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FPGA command register - 8
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FPGA commands
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load a23
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load a16
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load a8
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load a0
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load D23
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load D16
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load D8
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load D0
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read d32
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read d16
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read d8
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read d0
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readmem
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writemem
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