24 lines
565 B
Bash
Executable File
24 lines
565 B
Bash
Executable File
#!/bin/bash
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set -e
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# specify name of your PLD design and device to run on
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APP=counter
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DEV=ATF1502AS
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PKG=PLCC44
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SPD=15
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## compile Verilog design by yosys
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#../../../yosys/atf15xx_yosys/run_yosys.sh $APP > $APP.log
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## use Atmel fitter to produce .jed file
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#../../yosys/atf15xx_yosys/run_fitter.sh -d $DEV -p $PKG -s $SPD $APP -preassign keep -tdi_pullup on -tms_pullup on -output_fast off -xor_synthesis on $*
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# convert jed to svf
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python3 ./fuseconv.py -d $DEV $APP.jed $APP.svf
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# convert svf to xsvf
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python3 .//svf2xsvf.py $APP.svf $APP.xsvf
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date
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echo "done!" |