mirror of https://github.com/JorjBauer/aiie.git
building local driver
This commit is contained in:
Jorj Bauer
parent
a3db2e5c20
commit
12a84422c9
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@ -470,7 +470,7 @@ uint8_t AppleMMU::readSwitches(uint16_t address)
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return slots[i]->readSwitches(address & ~(0xC080 | (i<<4)));
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}
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else
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return FLOATING;
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return _FLOATINGBUS;
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}
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}
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}
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@ -505,7 +505,7 @@ uint8_t AppleMMU::readSwitches(uint16_t address)
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// by even read access
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preWriteFlag = (address & 0x01);
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC00C: // CLR80VID disable 80-col video mode
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if (switches & S_80COL) {
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@ -575,32 +575,32 @@ uint8_t AppleMMU::readSwitches(uint16_t address)
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// loop b/c the speaker might need attention
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// immediately
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#endif
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC050: // CLRTEXT
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if (switches & S_TEXT) {
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switches &= ~S_TEXT;
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resetDisplay();
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}
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC051: // SETTEXT
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if (!(switches & S_TEXT)) {
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switches |= S_TEXT;
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resetDisplay();
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}
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC052: // CLRMIXED
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if (switches & S_MIXED) {
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switches &= ~S_MIXED;
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resetDisplay();
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}
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC053: // SETMIXED
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if (!(switches & S_MIXED)) {
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switches |= S_MIXED;
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resetDisplay();
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}
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC054: // PAGE1
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if (switches & S_PAGE2) {
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@ -611,7 +611,7 @@ uint8_t AppleMMU::readSwitches(uint16_t address)
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updateMemoryPages();
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}
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}
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC055: // PAGE2
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if (!(switches & S_PAGE2)) {
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@ -622,34 +622,34 @@ uint8_t AppleMMU::readSwitches(uint16_t address)
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updateMemoryPages();
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}
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}
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC056: // CLRHIRES
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if (switches & S_HIRES) {
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switches &= ~S_HIRES;
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resetDisplay();
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}
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC057: // SETHIRES
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if (!(switches & S_HIRES)) {
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switches |= S_HIRES;
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resetDisplay();
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}
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC05E: // DHIRES ON
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if (!(switches & S_DHIRES)) {
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switches |= S_DHIRES;
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resetDisplay();
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}
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return FLOATING;
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return _FLOATINGBUS;
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case 0xC05F: // DHIRES OFF
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if (switches & S_DHIRES) {
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switches &= ~S_DHIRES;
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resetDisplay();
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}
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return FLOATING;
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return _FLOATINGBUS;
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// paddles
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/* Fall through for apple keys; they're just RAM in this model
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@ -665,7 +665,7 @@ uint8_t AppleMMU::readSwitches(uint16_t address)
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g_ram.writeByte((writePages[0xC0] << 8) | 0x64, 0xFF);
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g_ram.writeByte((writePages[0xC0] << 8) | 0x65, 0xFF);
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g_paddles->startReading();
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return FLOATING;
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return _FLOATINGBUS;
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}
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if (address >= 0xc000 && address <= 0xc00f) {
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@ -7,11 +7,11 @@
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#include "mmu.h"
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#include "noslotclock.h"
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// when we read a nondeterministic result, we return FLOATING. Maybe
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// some day we can come back here and figure out how to return what
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// the Apple would have.
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// when we read a nondeterministic result, we return
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// _FLOATINGBUS. Maybe some day we can come back here and figure out
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// how to return what the Apple would have.
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#define FLOATING 0
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#define _FLOATINGBUS 0
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// Switches activated by various memory locations
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enum {
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@ -12,7 +12,7 @@
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#include <time.h>
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#endif
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#include "applemmu.h" // for FLOATING
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#include "applemmu.h" // for _FLOATINGBUS
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#include "globals.h"
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#include "appleui.h"
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@ -273,7 +273,7 @@ uint8_t DiskII::readSwitches(uint8_t s)
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// Any even address read returns the readWriteLatch (UTA2E Table 9.1,
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// p. 9-12, note 2)
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return (s & 1) ? FLOATING : readWriteLatch;
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return (s & 1) ? _FLOATINGBUS : readWriteLatch;
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}
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void DiskII::writeSwitches(uint8_t s, uint8_t v)
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@ -22,8 +22,6 @@
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#include <errno.h>
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#endif
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#include "applemmu.h" // for FLOATING
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#include "serialize.h"
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#include "globals.h"
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@ -1,5 +1,4 @@
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#include "noslotclock.h"
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#include "applemmu.h" // for FLOATING
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#define initSequence 0x5CA33AC55CA33AC5LL
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@ -0,0 +1,269 @@
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#ifndef _RA8875_REGISTERS_H
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#define _RA8875_REGISTERS_H
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#define CENTER 9998
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#define ARC_ANGLE_MAX 360
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#define ARC_ANGLE_OFFSET -90
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#define ANGLE_OFFSET -90
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#define RA8875_PWRR 0x01//Power and Display Control Register
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#define RA8875_PWRR_DISPON 0x80
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#define RA8875_PWRR_DISPOFF 0x00
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#define RA8875_PWRR_SLEEP 0x02
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#define RA8875_PWRR_NORMAL 0x00
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#define RA8875_PWRR_SOFTRESET 0x01
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#define RA8875_MRWC 0x02//Memory Read/Write Command
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#define RA8875_CMDWRITE 0x80
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#define RA8875_CMDREAD 0xC0
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#define RA8875_DATAWRITE 0x00
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#define RA8875_DATAREAD 0x40
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#define RA8875_STATREG 0x40
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#define RA8875_PCSR 0x04//Pixel Clock Setting Register
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#define RA8875_SROC 0x05//Serial Flash/ROM Configuration
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#define RA8875_SFCLR 0x06//Serial Flash/ROM CLK
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#define EXTROM_SFCLSPEED 0b00000011// /4 0b00000010 /2
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#define RA8875_SYSR 0x10//System Configuration Register
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#define RA8875_HDWR 0x14//LCD Horizontal Display Width Register
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#define RA8875_HNDFTR 0x15//Horizontal Non-Display Period Fine Tuning Option Register
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#define RA8875_HNDR 0x16//LCD Horizontal Non-Display Period Register
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#define RA8875_HSTR 0x17//HSYNC Start Position Register
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#define RA8875_HPWR 0x18//HSYNC Pulse Width Register
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#define RA8875_VDHR0 0x19//LCD Vertical Display Height Register 0
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//#define RA8875_VDHR1 0x1A//LCD Vertical Display Height Register 1
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#define RA8875_VNDR0 0x1B//LCD Vertical Non-Display Period Register 0
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//#define RA8875_VNDR1 0x1C//LCD Vertical Non-Display Period Register 1
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#define RA8875_VSTR0 0x1D//VSYNC Start Position Register 0
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//#define RA8875_VSTR1 0x1E//VSYNC Start Position Register 1
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#define RA8875_VPWR 0x1F//VSYNC Pulse Width Register
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#define RA8875_DPCR 0x20//Display Configuration Register
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#define RA8875_FNCR0 0x21//Font Control Register 0
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#define RA8875_FNCR1 0x22//Font Control Register 1
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#define RA8875_CGSR 0x23//CGRAM Select Register
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#define RA8875_HOFS0 0x24//Horizontal Scroll Offset Register 0
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#define RA8875_HOFS1 0x25//Horizontal Scroll Offset Register 1
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#define RA8875_VOFS0 0x26//Vertical Scroll Offset Register 0
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#define RA8875_VOFS1 0x27//Vertical Scroll Offset Register 1
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#define RA8875_FLDR 0x29//Font Line Distance Setting Register
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#define RA8875_F_CURXL 0x2A//Font Write Cursor Horizontal Position Register 0
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#define RA8875_F_CURXH 0x2B//Font Write Cursor Horizontal Position Register 1
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#define RA8875_F_CURYL 0x2C//Font Write Cursor Vertical Position Register 0
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#define RA8875_F_CURYH 0x2D//Font Write Cursor Vertical Position Register 1
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#define RA8875_FWTSET 0x2E//Font Write Type Setting Register
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#define RA8875_SFRSET 0x2F//Serial Font ROM Setting
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#define RA8875_HSAW0 0x30//Horizontal Start Point 0 of Active Window
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//#define RA8875_HSAW1 0x31//Horizontal Start Point 1 of Active Window
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#define RA8875_VSAW0 0x32//Vertical Start Point 0 of Active Window
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//#define RA8875_VSAW1 0x33//Vertical Start Point 1 of Active Window
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#define RA8875_HEAW0 0x34//Horizontal End Point 0 of Active Window
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//#define RA8875_HEAW1 0x35//Horizontal End Point 1 of Active Window
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#define RA8875_VEAW0 0x36//Vertical End Point of Active Window 0
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//#define RA8875_VEAW1 0x37//Vertical End Point of Active Window 1
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#define RA8875_HSSW0 0x38//Horizontal Start Point 0 of Scroll Window
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//#define RA8875_HSSW1 0x39//Horizontal Start Point 1 of Scroll Window
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#define RA8875_VSSW0 0x3A//Vertical Start Point 0 of Scroll Window
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//#define RA8875_VSSW1 0x3B//Vertical Start Point 1 of Scroll Window
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#define RA8875_HESW0 0x3C//Horizontal End Point 0 of Scroll Window
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//#define RA8875_HESW1 0x3D//Horizontal End Point 1 of Scroll Window
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#define RA8875_VESW0 0x3E//Vertical End Point 0 of Scroll Window
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//#define RA8875_VESW1 0x3F//Vertical End Point 1 of Scroll Window
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#define RA8875_MWCR0 0x40//Memory Write Control Register 0
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#define RA8875_MWCR1 0x41//Memory Write Control Register 1
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#define RA8875_BTCR 0x44//Blink Time Control Register
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#define RA8875_MRCD 0x45//Memory Read Cursor Direction
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#define RA8875_CURH0 0x46//Memory Write Cursor Horizontal Position Register 0
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//#define RA8875_CURH1 0x47//Memory Write Cursor Horizontal Position Register 1
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#define RA8875_CURV0 0x48//Memory Write Cursor Vertical Position Register 0
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//#define RA8875_CURV1 0x49//Memory Write Cursor Vertical Position Register 1
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//#define RA8875_RCURH0 0x4A//Memory Read Cursor Horizontal Position Register 0
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//#define RA8875_RCURH1 0x4B//Memory Read Cursor Horizontal Position Register 1
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//#define RA8875_RCURV0 0x4C//Memory Read Cursor Vertical Position Register 0
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//#define RA8875_RCURV1 0x4D//Memory Read Cursor Vertical Position Register 1
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#define RA8875_CURHS 0x4E//Font Write Cursor and Memory Write Cursor Horizontal Size Register
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#define RA8875_CURVS 0x4F//Font Write Cursor Vertical Size Register
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#define RA8875_BECR0 0x50//BTE Function Control Register 0
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#define RA8875_BECR1 0x51//BTE Function Control Register 1
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#define RA8875_LTPR0 0x52//Layer Transparency Register 0
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#define RA8875_LTPR1 0x53//Layer Transparency Register 1
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#define RA8875_HSBE0 0x54//Horizontal Source Point 0 of BTE
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//#define RA8875_HSBE1 0x55//Horizontal Source Point 1 of BTE
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#define RA8875_VSBE0 0x56//Vertical Source Point 0 of BTE
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//#define RA8875_VSBE1 0x57//Vertical Source Point 1 of BTE
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#define RA8875_HDBE0 0x58//Horizontal Destination Point 0 of BTE
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//#define RA8875_HDBE1 0x59//Horizontal Destination Point 1 of BTE
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#define RA8875_VDBE0 0x5A//Vertical Destination Point 0 of BTE
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//#define RA8875_VDBE1 0x5B//Vertical Destination Point 1 of BTE
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#define RA8875_BEWR0 0x5C//BTE Width Register 0
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//#define RA8875_BEWR1 0x5D//BTE Width Register 1
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#define RA8875_BEHR0 0x5E//BTE Height Register 0
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//#define RA8875_BEHR1 0x5F//BTE Height Register 1
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#define RA8875_PTNO 0x66//Pattern Set No for BTE
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#define RA8875_BTEROP_SOURCE 0xC0 //Overwrite dest with source (no mixing) *****THIS IS THE DEFAULT OPTION****
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#define RA8875_BTEROP_BLACK 0xo0 //all black
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#define RA8875_BTEROP_WHITE 0xf0 //all white
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#define RA8875_BTEROP_DEST 0xA0 //destination unchanged
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#define RA8875_BTEROP_ADD 0xE0 //ADD (brighter)
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#define RA8875_BTEROP_SUBTRACT 0x20 //SUBTRACT (darker)
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#define RA8875_BGCR0 0x60//Background Color Register 0 (R)
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//#define RA8875_BGCR1 0x61//Background Color Register 1 (G)
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//#define RA8875_BGCR2 0x62//Background Color Register 2 (B)
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#define RA8875_FGCR0 0x63//Foreground Color Register 0 (R)
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//#define RA8875_FGCR1 0x64//Foreground Color Register 1 (G)
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//#define RA8875_FGCR2 0x65//Foreground Color Register 2 (B)
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#define RA8875_BGTR0 0x67//Background Color Register for Transparent 0 (R)
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//#define RA8875_BGTR1 0x68//Background Color Register for Transparent 1 (G)
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//#define RA8875_BGTR2 0x69//Background Color Register for Transparent 2 (B)
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#define RA8875_TPCR0 0x70//Touch Panel Control Register 0
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//#define RA8875_TPCR0_ENABLE 0x80
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//#define RA8875_TPCR0_DISABLE 0x00
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#define RA8875_TPCR0_WAIT_512CLK 0x00
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#define RA8875_TPCR0_WAIT_1024CLK 0x10
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#define RA8875_TPCR0_WAIT_2048CLK 0x20
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#define RA8875_TPCR0_WAIT_4096CLK 0x30
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#define RA8875_TPCR0_WAIT_8192CLK 0x40
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#define RA8875_TPCR0_WAIT_16384CLK 0x50
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#define RA8875_TPCR0_WAIT_32768CLK 0x60
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#define RA8875_TPCR0_WAIT_65536CLK 0x70
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#define RA8875_TPCR0_WAKEENABLE 0x08
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#define RA8875_TPCR0_WAKEDISABLE 0x00
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#define RA8875_TPCR0_ADCCLK_DIV1 0x00
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#define RA8875_TPCR0_ADCCLK_DIV2 0x01
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#define RA8875_TPCR0_ADCCLK_DIV4 0x02
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#define RA8875_TPCR0_ADCCLK_DIV8 0x03
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#define RA8875_TPCR0_ADCCLK_DIV16 0x04
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#define RA8875_TPCR0_ADCCLK_DIV32 0x05
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#define RA8875_TPCR0_ADCCLK_DIV64 0x06
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#define RA8875_TPCR0_ADCCLK_DIV128 0x07
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#define RA8875_TPCR1 0x71//Touch Panel Control Register 1
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#define RA8875_TPCR1_AUTO 0x00
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#define RA8875_TPCR1_MANUAL 0x40
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#define RA8875_TPCR1_VREFINT 0x00
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#define RA8875_TPCR1_VREFEXT 0x20
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#define RA8875_TPCR1_DEBOUNCE 0x04
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#define RA8875_TPCR1_NODEBOUNCE 0x00
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#define RA8875_TPCR1_IDLE 0x00
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#define RA8875_TPCR1_WAIT 0x01
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#define RA8875_TPCR1_LATCHX 0x02
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#define RA8875_TPCR1_LATCHY 0x03
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#define RA8875_TPXH 0x72//Touch Panel X High Byte Data Register
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#define RA8875_TPYH 0x73//Touch Panel Y High Byte Data Register
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#define RA8875_TPXYL 0x74//Touch Panel X/Y Low Byte Data Register
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//#define RA8875_GCHP0 0x80//Graphic Cursor Horizontal Position Register 0
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//#define RA8875_GCHP1 0x81//Graphic Cursor Horizontal Position Register 1
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//#define RA8875_GCVP0 0x82//Graphic Cursor Vertical Position Register 0
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//#define RA8875_GCVP1 0x83//Graphic Cursor Vertical Position Register 0
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//#define RA8875_GCC0 0x84//Graphic Cursor Color 0
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//#define RA8875_GCC1 0x85//Graphic Cursor Color 1
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#define RA8875_PLLC1 0x88//PLL Control Register 1
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//#define RA8875_PLLC2 0x89//PLL Control Register 2
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#define RA8875_P1CR 0x8A//PWM1 Control Register
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#define RA8875_P1DCR 0x8B//PWM1 Duty Cycle Register
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#define RA8875_P2CR 0x8C//PWM2 Control Register
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#define RA8875_P2DCR 0x8D//PWM2 Control Register
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#define RA8875_PxCR_ENABLE 0x80
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#define RA8875_PxCR_DISABLE 0x00
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#define RA8875_PxCR_CLKOUT 0x10
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#define RA8875_PxCR_PWMOUT 0x00
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#define RA8875_PWM_CLK_DIV1 0x00
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#define RA8875_PWM_CLK_DIV2 0x01
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#define RA8875_PWM_CLK_DIV4 0x02
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#define RA8875_PWM_CLK_DIV8 0x03
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#define RA8875_PWM_CLK_DIV16 0x04
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#define RA8875_PWM_CLK_DIV32 0x05
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#define RA8875_PWM_CLK_DIV64 0x06
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#define RA8875_PWM_CLK_DIV128 0x07
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#define RA8875_PWM_CLK_DIV256 0x08
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#define RA8875_PWM_CLK_DIV512 0x09
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#define RA8875_PWM_CLK_DIV1024 0x0A
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#define RA8875_PWM_CLK_DIV2048 0x0B
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#define RA8875_PWM_CLK_DIV4096 0x0C
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#define RA8875_PWM_CLK_DIV8192 0x0D
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#define RA8875_PWM_CLK_DIV16384 0x0E
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#define RA8875_PWM_CLK_DIV32768 0x0F
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#define RA8875_MCLR 0x8E//Memory Clear Control Register
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#define RA8875_DCR 0x90//Draw Line/Circle/Square Control Register
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#define RA8875_DCR_LINESQUTRI_START 0x80
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#define RA8875_DCR_LINESQUTRI_STOP 0x00
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#define RA8875_DCR_LINESQUTRI_STATUS 0x80
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#define RA8875_DCR_CIRCLE_START 0x40
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#define RA8875_DCR_CIRCLE_STATUS 0x40
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#define RA8875_DCR_CIRCLE_STOP 0x00
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#define RA8875_DCR_FILL 0x20
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#define RA8875_DCR_NOFILL 0x00
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#define RA8875_DCR_DRAWLINE 0x00
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#define RA8875_DCR_DRAWTRIANGLE 0x01
|
||||
#define RA8875_DCR_DRAWSQUARE 0x10
|
||||
#define RA8875_DLHSR0 0x91//Draw Line/Square Horizontal Start Address Register0
|
||||
//#define RA8875_DLHSR1 0x92//Draw Line/Square Horizontal Start Address Register1
|
||||
#define RA8875_DLVSR0 0x93//Draw Line/Square Vertical Start Address Register0
|
||||
//#define RA8875_DLVSR1 0x94//Draw Line/Square Vertical Start Address Register1
|
||||
#define RA8875_DLHER0 0x95//Draw Line/Square Horizontal End Address Register0
|
||||
//#define RA8875_DLHER1 0x96//Draw Line/Square Horizontal End Address Register1
|
||||
#define RA8875_DLVER0 0x97//Draw Line/Square Vertical End Address Register0
|
||||
//#define RA8875_DLVER1 0x98//Draw Line/Square Vertical End Address Register0
|
||||
#define RA8875_DCHR0 0x99//Draw Circle Center Horizontal Address Register0
|
||||
//#define RA8875_DCHR1 0x9A//Draw Circle Center Horizontal Address Register1
|
||||
#define RA8875_DCVR0 0x9B//Draw Circle Center Vertical Address Register0
|
||||
//#define RA8875_DCVR1 0x9C//Draw Circle Center Vertical Address Register1
|
||||
#define RA8875_DCRR 0x9D//Draw Circle Radius Register
|
||||
#define RA8875_ELLIPSE 0xA0//Draw Ellipse/Ellipse Curve/Circle Square Control Register
|
||||
#define RA8875_ELLIPSE_STATUS 0x80
|
||||
#define RA8875_ELL_A0 0xA1//Draw Ellipse/Circle Square Long axis Setting Register0
|
||||
//#define RA8875_ELL_A1 0xA2//Draw Ellipse/Circle Square Long axis Setting Register1
|
||||
#define RA8875_ELL_B0 0xA3//Draw Ellipse/Circle Square Short axis Setting Register0
|
||||
//#define RA8875_ELL_B1 0xA4//Draw Ellipse/Circle Square Short axis Setting Register1
|
||||
#define RA8875_DEHR0 0xA5//Draw Ellipse/Circle Square Center Horizontal Address Register0
|
||||
//#define RA8875_DEHR1 0xA6//Draw Ellipse/Circle Square Center Horizontal Address Register1
|
||||
#define RA8875_DEVR0 0xA7//Draw Ellipse/Circle Square Center Vertical Address Register0
|
||||
//#define RA8875_DEVR1 0xA8//Draw Ellipse/Circle Square Center Vertical Address Register1
|
||||
#define RA8875_DTPH0 0xA9//Draw Triangle Point 2 Horizontal Address Register0
|
||||
//#define RA8875_DTPH1 0xAA//Draw Triangle Point 2 Horizontal Address Register1
|
||||
#define RA8875_DTPV0 0xAB//Draw Triangle Point 2 Vertical Address Register0
|
||||
//#define RA8875_DTPV1 0xAC//Draw Triangle Point 2 Vertical Address Register1
|
||||
#define RA8875_SSAR0 0xB0//Source Starting Address REG 0
|
||||
//#define RA8875_SSAR1 0xB1//Source Starting Address REG 1
|
||||
//#define RA8875_SSAR2 0xB2//Source Starting Address REG 2
|
||||
//#define RA8875_???? 0xB3//???????????
|
||||
#define RA8875_DTNR0 0xB4//Block Width REG 0(BWR0) / DMA Transfer Number REG 0
|
||||
#define RA8875_BWR1 0xB5//Block Width REG 1
|
||||
#define RA8875_DTNR1 0xB6//Block Height REG 0(BHR0) /DMA Transfer Number REG 1
|
||||
#define RA8875_BHR1 0xB7//Block Height REG 1
|
||||
#define RA8875_DTNR2 0xB8//Source Picture Width REG 0(SPWR0) / DMA Transfer Number REG 2
|
||||
#define RA8875_SPWR1 0xB9//Source Picture Width REG 1
|
||||
#define RA8875_DMACR 0xBF//DMA Configuration REG
|
||||
#define RA8875_GPIOX 0xC7
|
||||
#define RA8875_KSCR1 0xC0 //Key-Scan Control Register 1 (KSCR1)
|
||||
#define RA8875_KSCR2 0xC1 //Key-Scan Controller Register 2 (KSCR2)
|
||||
#define RA8875_KSDR0 0xC2 //Key-Scan Data Register (KSDR0)
|
||||
#define RA8875_KSDR1 0xC3 //Key-Scan Data Register (KSDR1)
|
||||
#define RA8875_KSDR2 0xC4 //Key-Scan Data Register (KSDR2)
|
||||
#define RA8875_INTC1 0xF0//Interrupt Control Register1
|
||||
#define RA8875_INTC2 0xF1//Interrupt Control Register2
|
||||
#define RA8875_INTCx_KEY 0x10
|
||||
#define RA8875_INTCx_DMA 0x08
|
||||
#define RA8875_INTCx_TP 0x04
|
||||
#define RA8875_INTCx_BTE 0x02
|
||||
#define RA8875_ENABLE_INT_TP ((uint8_t)(1<<2))
|
||||
#define RA8875_DISABLE_INT_TP ((uint8_t)(0<<2))
|
||||
#define TP_ENABLE ((uint8_t)(1<<7))
|
||||
#define TP_DISABLE ((uint8_t)(0<<7))
|
||||
#define TP_MODE_AUTO ((uint8_t)(0<<6))
|
||||
#define TP_MODE_MANUAL ((uint8_t)(1<<6))
|
||||
#define TP_DEBOUNCE_OFF ((uint8_t)(0<<2))
|
||||
#define TP_DEBOUNCE_ON ((uint8_t)(1<<2))
|
||||
#define TP_ADC_CLKDIV_1 0
|
||||
#define TP_ADC_CLKDIV_2 1
|
||||
#define TP_ADC_CLKDIV_4 2
|
||||
#define TP_ADC_CLKDIV_8 3
|
||||
#define TP_ADC_CLKDIV_16 4
|
||||
#define TP_ADC_CLKDIV_32 5
|
||||
#define TP_ADC_CLKDIV_64 6
|
||||
#define TP_ADC_CLKDIV_128 7
|
||||
#define TP_ADC_SAMPLE_512_CLKS ((uint8_t)(0<<4))
|
||||
#define TP_ADC_SAMPLE_1024_CLKS ((uint8_t)(1<<4))
|
||||
#define TP_ADC_SAMPLE_2048_CLKS ((uint8_t)(2<<4))
|
||||
#define TP_ADC_SAMPLE_4096_CLKS ((uint8_t)(3<<4))
|
||||
#define TP_ADC_SAMPLE_8192_CLKS ((uint8_t)(4<<4))
|
||||
#define TP_ADC_SAMPLE_16384_CLKS ((uint8_t)(5<<4))
|
||||
#define TP_ADC_SAMPLE_32768_CLKS ((uint8_t)(6<<4))
|
||||
#define TP_ADC_SAMPLE_65536_CLKS ((uint8_t)(7<<4))
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,267 @@
|
|||
#include "RA8875_t4.h"
|
||||
#include "RA8875_registers.h"
|
||||
|
||||
RA8875_t4::RA8875_t4(const uint8_t cs_pin, const uint8_t rst_pin, const uint8_t mosi_pin, const uint8_t sck_pin, const uint8_t miso_pin)
|
||||
{
|
||||
_mosi = mosi_pin;
|
||||
_miso = miso_pin;
|
||||
_cs = cs_pin;
|
||||
_rst = rst_pin;
|
||||
_sck = sck_pin;
|
||||
_interruptStates = 0b00000000;
|
||||
|
||||
_pspi = NULL;
|
||||
}
|
||||
|
||||
RA8875_t4::~RA8875_t4()
|
||||
{
|
||||
}
|
||||
|
||||
void RA8875_t4::begin(uint32_t spi_clock, uint32_t spi_clock_read)
|
||||
{
|
||||
_interruptStates = 0b00000000;
|
||||
_spi_clock = spi_clock;
|
||||
_spi_clock_read = spi_clock_read;
|
||||
_clock = 4000000UL; // start at low speed
|
||||
|
||||
// figure out which SPI bus we're using
|
||||
if (SPI.pinIsMOSI(_mosi) && ((_miso == 0xff) || SPI.pinIsMISO(_miso)) && SPI.pinIsSCK(_sck)) {
|
||||
_pspi = &SPI;
|
||||
_spi_num = 0;
|
||||
_pimxrt_spi = &IMXRT_LPSPI4_S;
|
||||
} else if (SPI1.pinIsMOSI(_mosi) && ((_miso == 0xff) || SPI1.pinIsMISO(_miso)) && SPI1.pinIsSCK(_sck)) {
|
||||
_pspi = &SPI1;
|
||||
_spi_num = 1;
|
||||
_pimxrt_spi = &IMXRT_LPSPI3_S;
|
||||
} else if (SPI2.pinIsMOSI(_mosi) && ((_miso == 0xff) || SPI2.pinIsMISO(_miso)) && SPI2.pinIsSCK(_sck)) {
|
||||
_pspi = &SPI2;
|
||||
_spi_num = 2;
|
||||
_pimxrt_spi = &IMXRT_LPSPI1_S;
|
||||
} else {
|
||||
Serial.println("Pins given are not valid SPI bus pins");
|
||||
return;
|
||||
}
|
||||
|
||||
_pspi->setMOSI(_mosi);
|
||||
_pspi->setSCK(_sck);
|
||||
if (_miso != 0xff) _pspi->setMISO(_miso);
|
||||
uint32_t *pa = (uint32_t *)_pspi;
|
||||
_spi_hardware = (SPIClass::SPI_Hardware_t *)pa[1];
|
||||
|
||||
_pspi->begin();
|
||||
|
||||
_csport = portOutputRegister(_cs);
|
||||
_cspinmask = digitalPinToBitMask(_cs);
|
||||
pinMode(_cs, OUTPUT);
|
||||
// DIRECT_WRITE_HIGH(_csport, _cspinmask);
|
||||
digitalWrite(_cs, HIGH);
|
||||
|
||||
|
||||
/*
|
||||
pending_rx_count = 0; // Make sure it is zero if we we do a second begin...
|
||||
_spi_tcr_current = _pimxrt_spi->TCR; // get the current TCR value
|
||||
|
||||
// TODO: Need to setup DC to actually work.
|
||||
if (_pspi->pinIsChipSelect(_dc)) {
|
||||
uint8_t dc_cs_index = _pspi->setCS(_dc);
|
||||
_dcport = 0;
|
||||
_dcpinmask = 0;
|
||||
// will depend on which PCS but first get this to work...
|
||||
dc_cs_index--; // convert to 0 based
|
||||
_tcr_dc_assert = LPSPI_TCR_PCS(dc_cs_index);
|
||||
_tcr_dc_not_assert = LPSPI_TCR_PCS(3);
|
||||
} else {
|
||||
_dcport = portOutputRegister(_dc);
|
||||
_dcpinmask = digitalPinToBitMask(_dc);
|
||||
pinMode(_dc, OUTPUT);
|
||||
DIRECT_WRITE_HIGH(_dcport, _dcpinmask);
|
||||
_tcr_dc_assert = LPSPI_TCR_PCS(0);
|
||||
_tcr_dc_not_assert = LPSPI_TCR_PCS(1);
|
||||
}
|
||||
maybeUpdateTCR(_tcr_dc_not_assert | LPSPI_TCR_FRAMESZ(7));
|
||||
*/
|
||||
|
||||
_initializeTFT();
|
||||
}
|
||||
|
||||
void RA8875_t4::_initializeTFT()
|
||||
{
|
||||
// toggle RST low to reset
|
||||
if (_rst < 255) {
|
||||
pinMode(_rst, OUTPUT);
|
||||
digitalWrite(_rst, HIGH);
|
||||
delay(10);
|
||||
digitalWrite(_rst, LOW);
|
||||
delay(220);
|
||||
digitalWrite(_rst, HIGH);
|
||||
delay(300);
|
||||
} else {
|
||||
// Try a soft reset
|
||||
writeCommand(RA8875_PWRR);
|
||||
_writeData(RA8875_PWRR_SOFTRESET);
|
||||
delay(20);
|
||||
_writeData(RA8875_PWRR_NORMAL);
|
||||
delay(200);
|
||||
}
|
||||
|
||||
// Set the sysclock
|
||||
_writeRegister(RA8875_PLLC1, 0x07); // same as default value: %0000 0111 == pre /=1; input /=7
|
||||
delay(1);
|
||||
_writeRegister(RA8875_PLLC1+1, 0x03); // same as default value: %0000 0011 == output /8
|
||||
delay(1);
|
||||
_writeRegister(RA8875_PCSR, 0x81); // pixel clock setting register: %1000 0001 == PDAT at PCLK falling edge; PCLK period is 2* system clock period
|
||||
delay(1);
|
||||
|
||||
// colorspace
|
||||
_writeRegister(RA8875_SYSR, 0x0C); // 65k
|
||||
|
||||
_writeRegister(RA8875_HDWR, 0x63); // LCD horizontal display width == (v+1)*8
|
||||
_writeRegister(RA8875_HNDFTR, 0x00); // Horizontal non-display period fine tuning
|
||||
_writeRegister(RA8875_HNDR, 0x03); // LCD Horizontal non-display period register; period (in pixels) = (v+1)*8 + HNDFTR+2 == 32
|
||||
_writeRegister(RA8875_HSTR, 0x03); // HSYNC start position register; start position (in pixels) = (v+1)*8 == 24
|
||||
_writeRegister(RA8875_HPWR, 0x0B); // HSYNC pulse width register; %0000 1011 == HSYNC low active, hsync pulse width = ((v&32)+1)*8 = 88
|
||||
_writeRegister(RA8875_VDHR0, 0xDF); // LCD Vertical display height register 0 (low byte of height, where height = this value + 1)
|
||||
_writeRegister(RA8875_VDHR0+1, 0x01); // LCD Vertical display height register 1 (high byte of height)
|
||||
_writeRegister(RA8875_VNDR0, 0x1F); // LCD vertical non-display period register 0 (low byte of non-display period in lines, where period=(VNDR+1) == 32)
|
||||
_writeRegister(RA8875_VNDR0+1, 0x00); // LCD vertical non-display period register 1 (high byte of non-display period in lines)
|
||||
_writeRegister(RA8875_VSTR0, 0x16); // VSYNC start position register 0; low byte, where start pos(line) = (VSTR+1) == 23
|
||||
_writeRegister(RA8875_VSTR0+1, 0x00); // VSYNC start position register 1; high byte
|
||||
_writeRegister(RA8875_VPWR, 0x01); // VSYNC pulse width register; %0000 0001 == low active, pulse width (in lines) = (v&0x7F)+1 == 2
|
||||
|
||||
// Set the entire screen as the active window
|
||||
_writeRegister(RA8875_HSAW0, 0x00); // horizontal start point of active window
|
||||
_writeRegister(RA8875_HSAW0+1, 0x00);
|
||||
_writeRegister(RA8875_HEAW0, (RA8875_WIDTH-1) & 0xFF);
|
||||
_writeRegister(RA8875_HEAW0+1, (RA8875_WIDTH-1) >> 8); // horizontal end point of active window
|
||||
_writeRegister(RA8875_VSAW0, 0x00); // vertical start point of active window
|
||||
_writeRegister(RA8875_VSAW0+1, 0x00);
|
||||
_writeRegister(RA8875_VEAW0, (RA8875_HEIGHT-1) & 0xFF); // vertical end point of active window
|
||||
_writeRegister(RA8875_VEAW0+1, (RA8875_HEIGHT-1) >> 8);
|
||||
|
||||
delay(10);
|
||||
|
||||
// Update the sysclock
|
||||
_writeRegister(RA8875_PLLC1, 0x0B); // %0000 1011 == pre-drive /1; input /11
|
||||
delay(1);
|
||||
_writeRegister(RA8875_PLLC1+1, 0x02); // %0000 0010 == PLL output /4
|
||||
delay(1);
|
||||
_writeRegister(RA8875_PCSR, 0x81); // %1000 0001 == PDAT at PCLK falling edge; PCLK period is 2* system clock period
|
||||
delay(1);
|
||||
|
||||
_clock = _spi_clock; // speed up to full speed now
|
||||
|
||||
// Set up the gpio
|
||||
_writeRegister(RA8875_GPIOX, true);
|
||||
}
|
||||
|
||||
void RA8875_t4::setFrameBuffer(uint16_t *frame_buffer)
|
||||
{
|
||||
}
|
||||
|
||||
bool RA8875_t4::asyncUpdateActive()
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool RA8875_t4::updateScreenAsync(bool update_cont)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void RA8875_t4::fillWindow(uint16_t color)
|
||||
{
|
||||
// Set the color
|
||||
_writeRegister(RA8875_FGCR0,((color & 0xF800) >> 11)); // 5 bits red
|
||||
_writeRegister(RA8875_FGCR0+1,((color & 0x07E0) >> 5)); // 6 bits green
|
||||
_writeRegister(RA8875_FGCR0+2,((color & 0x001F) )); // 5 bits blue
|
||||
|
||||
// Send fill
|
||||
writeCommand(RA8875_DCR); // draw control register
|
||||
_writeData(0xB0); // %1011 0000 == start draw; stop circle; fill shape; draw square; draw square (yes two different bits for draw square)
|
||||
|
||||
// Wait for completion (when DCR_LINESQUTRI_STATUS bit it set in read result, before TIMEOUT happens)
|
||||
_waitPoll(RA8875_DCR, RA8875_DCR_LINESQUTRI_STATUS, _RA8875_WAITPOLL_TIMEOUT_DCR_LINESQUTRI_STATUS);
|
||||
}
|
||||
|
||||
void RA8875_t4::drawPixel(int16_t x, int16_t y, uint16_t color)
|
||||
{
|
||||
// FIXME: bounds checking
|
||||
|
||||
// Set Y
|
||||
_writeRegister(RA8875_CURV0, y & 0xFF); // cursor vertical location
|
||||
_writeRegister(RA8875_CURV0+1, y >> 8);
|
||||
// Set X
|
||||
_writeRegister(RA8875_CURH0, x & 0xFF); // cursor horiz location
|
||||
_writeRegister(RA8875_CURH0+1, (x >> 8));
|
||||
|
||||
// Send pixel data
|
||||
writeCommand(RA8875_MRWC); // write to wherever MWCR1 says (which we expect to be default graphics layer)
|
||||
writeData16(color);
|
||||
}
|
||||
|
||||
uint32_t RA8875_t4::frameCount()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void RA8875_t4::writeCommand(const uint8_t d)
|
||||
{
|
||||
_startSend();
|
||||
_pspi->transfer(RA8875_CMDWRITE);
|
||||
_pspi->transfer(d);
|
||||
_endSend();
|
||||
}
|
||||
|
||||
void RA8875_t4::writeData16(uint16_t data)
|
||||
{
|
||||
_startSend();
|
||||
_pspi->transfer(RA8875_DATAWRITE);
|
||||
_pspi->transfer16(data);
|
||||
_endSend();
|
||||
}
|
||||
|
||||
void RA8875_t4::_writeData(uint8_t data)
|
||||
{
|
||||
_startSend();
|
||||
_pspi->transfer(RA8875_DATAWRITE);
|
||||
_pspi->transfer(data);
|
||||
_endSend();
|
||||
}
|
||||
|
||||
uint8_t RA8875_t4::_readData(bool stat)
|
||||
{
|
||||
_startSend();
|
||||
_pspi->transfer(stat ? RA8875_CMDREAD : RA8875_DATAREAD);
|
||||
_pspi->transfer(0x00);
|
||||
_endSend();
|
||||
}
|
||||
|
||||
void RA8875_t4::_writeRegister(const uint8_t reg, uint8_t val)
|
||||
{
|
||||
writeCommand(reg);
|
||||
_writeData(val);
|
||||
}
|
||||
|
||||
uint8_t RA8875_t4::_readRegister(const uint8_t reg)
|
||||
{
|
||||
writeCommand(reg);
|
||||
return _readData(false);
|
||||
}
|
||||
|
||||
boolean RA8875_t4::_waitPoll(uint8_t regname, uint8_t waitflag, uint8_t timeout)
|
||||
{
|
||||
uint8_t temp;
|
||||
unsigned long start_time = millis();
|
||||
|
||||
while (1) {
|
||||
temp = _readRegister(regname);
|
||||
if (!(temp & waitflag)) {
|
||||
return true;
|
||||
}
|
||||
if ((millis() - start_time) > timeout) {
|
||||
// timeout
|
||||
return false;
|
||||
}
|
||||
}
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
#ifndef _RA8875_T4_H
|
||||
#define _RA8875_T4_H
|
||||
|
||||
#define SCREEN_DMA_NUM_SETTINGS 3
|
||||
|
||||
#include <Arduino.h>
|
||||
#include <SPI.h>
|
||||
#include <DMAChannel.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#define RA8875_WIDTH 800
|
||||
#define RA8875_HEIGHT 480
|
||||
|
||||
#define _RA8875_WAITPOLL_TIMEOUT_DCR_LINESQUTRI_STATUS 20
|
||||
|
||||
enum {
|
||||
RA8875_DMA_INIT=0x01,
|
||||
RA8875_DMA_EVER_INIT=0x08,
|
||||
RA8875_DMA_CONT=0x02,
|
||||
RA8875_DMA_FINISH=0x04,
|
||||
RA8875_DMA_ACTIVE=0x80
|
||||
};
|
||||
|
||||
class RA8875_t4 {
|
||||
public:
|
||||
RA8875_t4(const uint8_t cs_pin, const uint8_t rst_pin, const uint8_t mosi_pin, const uint8_t sck_pin, const uint8_t miso_pin);
|
||||
~RA8875_t4();
|
||||
|
||||
void begin(uint32_t spi_clock=30000000u, uint32_t spi_clock_read=2000000);
|
||||
|
||||
void fillWindow(uint16_t color = 0x0000);
|
||||
|
||||
void setFrameBuffer(uint16_t *frame_buffer);
|
||||
|
||||
bool asyncUpdateActive();
|
||||
bool updateScreenAsync(bool update_cont = false);
|
||||
|
||||
void drawPixel(int16_t x, int16_t y, uint16_t color);
|
||||
uint32_t frameCount();
|
||||
|
||||
private:
|
||||
void _initializeTFT();
|
||||
|
||||
// These are the old style RA8875 calls -- replace them ***
|
||||
void writeCommand(const uint8_t d);
|
||||
void writeData16(uint16_t data);
|
||||
|
||||
void _writeData(uint8_t data);
|
||||
void _writeRegister(const uint8_t reg, uint8_t val);
|
||||
|
||||
uint8_t _readData(bool stat);
|
||||
uint8_t _readRegister(const uint8_t reg);
|
||||
|
||||
|
||||
boolean _waitPoll(uint8_t regname, uint8_t waitflag, uint8_t timeout);
|
||||
|
||||
protected:
|
||||
uint8_t _cs, _miso, _mosi, _sck, _rst;
|
||||
volatile uint8_t _interruptStates;
|
||||
|
||||
SPIClass *_pspi;
|
||||
IMXRT_LPSPI_t *_pimxrt_spi;
|
||||
SPIClass::SPI_Hardware_t *_spi_hardware;
|
||||
uint8_t _spi_num;
|
||||
uint32_t _spi_clock; // desired clock
|
||||
uint32_t _spi_clock_read;
|
||||
uint32_t _clock; // current clock, used in starting transactions (b/c we have to slow down sometimes)
|
||||
volatile uint32_t *_csport;
|
||||
uint32_t _cspinmask;
|
||||
|
||||
protected:
|
||||
void DIRECT_WRITE_LOW(volatile uint32_t * base, uint32_t mask) __attribute__((always_inline)) {
|
||||
*(base+34) = mask;
|
||||
}
|
||||
void DIRECT_WRITE_HIGH(volatile uint32_t * base, uint32_t mask) __attribute__((always_inline)) {
|
||||
*(base+33) = mask;
|
||||
}
|
||||
|
||||
/* These are old-style function names, but with new-style contents */
|
||||
void _startSend() __attribute__((always_inline)) {
|
||||
_pspi->beginTransaction(SPISettings(_clock, MSBFIRST, SPI_MODE3));
|
||||
/* _spi_tcr_current = _pimxrt_spi->TCR; -- do we need this? related to the _dc line... */
|
||||
// DIRECT_WRITE_LOW(_csport, _cspinmask);
|
||||
digitalWrite(_rst, LOW);
|
||||
}
|
||||
|
||||
void _endSend() __attribute__((always_inline)) {
|
||||
// DIRECT_WRITE_HIGH(_csport, _cspinmask);
|
||||
digitalWrite(_rst, HIGH);
|
||||
_pspi->endTransaction();
|
||||
}
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -1,5 +1,4 @@
|
|||
#include <ctype.h> // isgraph
|
||||
#include <DMAChannel.h>
|
||||
|
||||
#include "teensy-display.h"
|
||||
#include "iocompat.h"
|
||||
|
|
@ -16,8 +15,12 @@ extern const unsigned char interface_glyphs[256];
|
|||
#include "globals.h"
|
||||
#include "applevm.h"
|
||||
|
||||
#ifndef RA8875_HEIGHT
|
||||
#define RA8875_HEIGHT 480
|
||||
#endif
|
||||
|
||||
#include <SPI.h>
|
||||
#define _clock 50000000
|
||||
//#define _clock 50000000
|
||||
|
||||
|
||||
#define PIN_RST 8
|
||||
|
|
@ -49,32 +52,20 @@ const uint16_t loresPixelColors[16] = { 0x0000, // 0 black
|
|||
0xFFFF // 15 white
|
||||
};
|
||||
|
||||
// This definition can't live in the class header because of the
|
||||
// DMAMEM adornment
|
||||
DMAMEM uint16_t dmaBuffer[480][800];
|
||||
|
||||
#define RGBto565(r,g,b) ((((r) & 0xF8) << 8) | (((g) & 0xFC) << 3) | ((b) >> 3))
|
||||
#define _565toR(c) ( ((c) & 0xF800) >> 8 )
|
||||
#define _565toG(c) ( ((c) & 0x07E0) >> 3 )
|
||||
#define _565toB(c) ( ((c) & 0x001F) << 3 )
|
||||
#define luminanceFromRGB(r,g,b) ( ((r)*0.2126) + ((g)*0.7152) + ((b)*0.0722) )
|
||||
|
||||
RA8875 tft = RA8875(PIN_CS, PIN_RST, PIN_MOSI, PIN_SCK, PIN_MISO);
|
||||
|
||||
DMAChannel dmatx;
|
||||
DMASetting dmaSetting;
|
||||
|
||||
RA8875_t4 tft = RA8875_t4(PIN_CS, PIN_RST, PIN_MOSI, PIN_SCK, PIN_MISO);
|
||||
|
||||
TeensyDisplay::TeensyDisplay()
|
||||
{
|
||||
memset(dmaBuffer, 0x80, sizeof(dmaBuffer));
|
||||
|
||||
tft.begin(_clock);
|
||||
tft.setRotation(3);
|
||||
tft.setFrameBuffer((uint16_t *)dmaBuffer);
|
||||
tft.useFrameBuffer(true);
|
||||
tft.fillScreen(ILI9341_BLACK);
|
||||
|
||||
// tft.begin(Adafruit_800x480);
|
||||
tft.begin();
|
||||
tft.fillWindow();
|
||||
|
||||
driveIndicator[0] = driveIndicator[1] = false;
|
||||
driveIndicatorDirty = true;
|
||||
}
|
||||
|
|
@ -85,7 +76,7 @@ TeensyDisplay::~TeensyDisplay()
|
|||
|
||||
void TeensyDisplay::flush()
|
||||
{
|
||||
// Nothing to flush, b/c the DMA driver is regularly flushing everything
|
||||
// Nothing to flush, b/c there's no DMA in this driver and we draw it all in real-time. (Eww.)
|
||||
}
|
||||
|
||||
void TeensyDisplay::redraw()
|
||||
|
|
@ -104,29 +95,24 @@ void TeensyDisplay::drawImageOfSizeAt(const uint8_t *img,
|
|||
{
|
||||
uint8_t r, g, b;
|
||||
|
||||
// FIXME this needs to scale with TEENSYDISPLAY_SCALE
|
||||
for (uint16_t y=0; y<sizey; y++) {
|
||||
for (uint16_t x=0; x<sizex; x++) {
|
||||
r = pgm_read_byte(&img[(y*sizex + x)*3 + 0]);
|
||||
g = pgm_read_byte(&img[(y*sizex + x)*3 + 1]);
|
||||
b = pgm_read_byte(&img[(y*sizex + x)*3 + 2]);
|
||||
dmaBuffer[y+wherey][x+wherex] = RGBto565(r,g,b);
|
||||
tft.drawPixel(x+wherex, y+wherey, RGBto565(r,g,b));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void TeensyDisplay::blit()
|
||||
{
|
||||
// Start DMA transfers if they aren't running
|
||||
if (!tft.asyncUpdateActive())
|
||||
tft.updateScreenAsync(true);
|
||||
|
||||
// draw overlay, if any, occasionally
|
||||
{
|
||||
static uint32_t nextMessageTime = 0;
|
||||
if (millis() >= nextMessageTime) {
|
||||
if (overlayMessage[0]) {
|
||||
drawString(M_SELECTDISABLED, 1, TEENSYDISPLAY_HEIGHT - (16 + 12)*TEENSYDISPLAY_SCALE, overlayMessage);
|
||||
drawString(M_SELECTDISABLED, 1, RA8875_HEIGHT - (16 + 12), overlayMessage);
|
||||
}
|
||||
nextMessageTime = millis() + 10; // DEBUGGING FIXME make 1000 again
|
||||
}
|
||||
|
|
@ -135,13 +121,11 @@ void TeensyDisplay::blit()
|
|||
|
||||
void TeensyDisplay::blit(AiieRect r)
|
||||
{
|
||||
// Nothing to do here, since we're regularly blitting the whole screen via DMA
|
||||
}
|
||||
|
||||
void TeensyDisplay::drawUIPixel(uint16_t x, uint16_t y, uint16_t color)
|
||||
{
|
||||
// These pixels are just cached in the buffer; they're not drawn directly.
|
||||
dmaBuffer[y][x] = color;
|
||||
tft.drawPixel(x, y, color);
|
||||
}
|
||||
|
||||
void TeensyDisplay::drawPixel(uint16_t x, uint16_t y, uint16_t color)
|
||||
|
|
@ -214,20 +198,14 @@ void TeensyDisplay::drawString(uint8_t mode, uint16_t x, uint16_t y, const char
|
|||
void TeensyDisplay::clrScr(uint8_t coloridx)
|
||||
{
|
||||
if (coloridx == c_black) {
|
||||
memset(dmaBuffer, 0x00, sizeof(dmaBuffer));
|
||||
tft.fillWindow();
|
||||
} else if (coloridx == c_white) {
|
||||
memset(dmaBuffer, 0xFF, sizeof(dmaBuffer));
|
||||
tft.fillWindow();
|
||||
} else {
|
||||
uint16_t color16 = loresPixelColors[c_black];
|
||||
if (coloridx < 16)
|
||||
color16 = loresPixelColors[coloridx];
|
||||
// This could be faster - make one line, then memcpy the line to the other
|
||||
// lines?
|
||||
for (uint16_t y=0; y<TEENSYDISPLAY_HEIGHT; y++) {
|
||||
for (uint16_t x=0; x<TEENSYDISPLAY_WIDTH; x++) {
|
||||
dmaBuffer[y][x] = color16;
|
||||
}
|
||||
}
|
||||
tft.fillWindow();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -255,56 +233,19 @@ inline uint16_t blendColors(uint16_t a, uint16_t b)
|
|||
|
||||
}
|
||||
|
||||
// This was called with the expectation that it can draw every one of
|
||||
// the 560x192 pixels that could be addressed. If TEENSYDISPLAY_SCALE
|
||||
// is 1, then we have half of that horizontal resolution - so we need
|
||||
// to be creative and blend neighboring pixels together.
|
||||
void TeensyDisplay::cachePixel(uint16_t x, uint16_t y, uint8_t color)
|
||||
{
|
||||
#if TEENSYDISPLAY_SCALE == 1
|
||||
// This is the case where we need to blend together neighboring
|
||||
// pixels, because we don't have enough physical screen resoultion.
|
||||
if (x&1) {
|
||||
uint16_t origColor = dmaBuffer[y+SCREENINSET_Y][(x>>1)*TEENSYDISPLAY_SCALE+SCREENINSET_X];
|
||||
uint16_t newColor = (uint16_t) loresPixelColors[color];
|
||||
if (g_displayType == m_blackAndWhite) {
|
||||
// There are four reasonable decisions here: if either pixel
|
||||
// *was* on, then it's on; if both pixels *were* on, then it's
|
||||
// on; and if the blended value of the two pixels were on, then
|
||||
// it's on; or if the blended value of the two is above some
|
||||
// certain overall brightness, then it's on. This is the last of
|
||||
// those - where the brightness cutoff is defined in the bios as
|
||||
// g_luminanceCutoff.
|
||||
uint16_t blendedColor = blendColors(origColor, newColor);
|
||||
uint16_t luminance = luminanceFromRGB(_565toR(blendedColor),
|
||||
_565toG(blendedColor),
|
||||
_565toB(blendedColor));
|
||||
cacheDoubleWidePixel(x>>1,y,(uint16_t)((luminance >= g_luminanceCutoff) ? 0xFFFF : 0x0000));
|
||||
} else {
|
||||
cacheDoubleWidePixel(x>>1,y,color);
|
||||
// Else if it's black, we leave whatever was in the other pixel.
|
||||
}
|
||||
} else {
|
||||
// The even pixels always draw.
|
||||
cacheDoubleWidePixel(x>>1,y,color);
|
||||
for (int yoff=0; yoff<2; yoff++) {
|
||||
tft.drawPixel(x+SCREENINSET_X, (y*2)+SCREENINSET_Y+yoff, color);
|
||||
}
|
||||
#else
|
||||
// we have enough resolution to show all the pixels, so just do it
|
||||
x = (x * TEENSYDISPLAY_SCALE)/2;
|
||||
for (int yoff=0; yoff<TEENSYDISPLAY_SCALE; yoff++) {
|
||||
for (int xoff=0; xoff<TEENSYDISPLAY_SCALE; xoff++) {
|
||||
dmaBuffer[y*TEENSYDISPLAY_SCALE+yoff+SCREENINSET_Y][x+xoff+SCREENINSET_X] = color;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void TeensyDisplay::cacheDoubleWidePixel(uint16_t x, uint16_t y, uint16_t color16)
|
||||
{
|
||||
for (int yoff=0; yoff<TEENSYDISPLAY_SCALE; yoff++) {
|
||||
for (int xoff=0; xoff<TEENSYDISPLAY_SCALE; xoff++) {
|
||||
dmaBuffer[(y*TEENSYDISPLAY_SCALE+yoff+SCREENINSET_Y)][x*TEENSYDISPLAY_SCALE+xoff+SCREENINSET_X] = color16;
|
||||
for (int yoff=0; yoff<2; yoff++) {
|
||||
for (int xoff=0; xoff<2; xoff++) {
|
||||
tft.drawPixel((x*2)+SCREENINSET_X+xoff, (y*2)+SCREENINSET_Y+yoff, color16);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -315,10 +256,10 @@ void TeensyDisplay::cacheDoubleWidePixel(uint16_t x, uint16_t y, uint8_t color)
|
|||
{
|
||||
uint16_t color16;
|
||||
color16 = loresPixelColors[(( color & 0x0F ) )];
|
||||
|
||||
for (int yoff=0; yoff<TEENSYDISPLAY_SCALE; yoff++) {
|
||||
for (int xoff=0; xoff<TEENSYDISPLAY_SCALE; xoff++) {
|
||||
dmaBuffer[(y*TEENSYDISPLAY_SCALE+yoff+SCREENINSET_Y)][x*TEENSYDISPLAY_SCALE+xoff+SCREENINSET_X] = color16;
|
||||
|
||||
for (int yoff=0; yoff<2; yoff++) {
|
||||
for (int xoff=0; xoff<2; xoff++) {
|
||||
tft.drawPixel((x*2)+SCREENINSET_X+xoff, (y*2)+SCREENINSET_Y+yoff, color16);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -329,10 +270,10 @@ void TeensyDisplay::cacheDoubleWidePixel(uint16_t x, uint16_t y, uint8_t color)
|
|||
void TeensyDisplay::cache2DoubleWidePixels(uint16_t x, uint16_t y,
|
||||
uint8_t colorA, uint8_t colorB)
|
||||
{
|
||||
for (int yoff=0; yoff<TEENSYDISPLAY_SCALE; yoff++) {
|
||||
for (int xoff=0; xoff<TEENSYDISPLAY_SCALE; xoff++) {
|
||||
dmaBuffer[(y*TEENSYDISPLAY_SCALE+yoff+SCREENINSET_Y)][x*TEENSYDISPLAY_SCALE+2*xoff+SCREENINSET_X] = loresPixelColors[colorA];
|
||||
dmaBuffer[(y*TEENSYDISPLAY_SCALE+yoff+SCREENINSET_Y)][x*TEENSYDISPLAY_SCALE+1+2*xoff+SCREENINSET_X] = loresPixelColors[colorB];
|
||||
for (int yoff=0; yoff<2; yoff++) {
|
||||
for (int xoff=0; xoff<2; xoff++) {
|
||||
tft.drawPixel((x*2)+SCREENINSET_X+xoff, (y*2)+SCREENINSET_Y+yoff, colorA);
|
||||
tft.drawPixel((x+1)*2+SCREENINSET_X+xoff, (y*2)+SCREENINSET_Y+yoff, colorB);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -342,10 +283,8 @@ inline double logfn(double x)
|
|||
// At a value of x=255, log(base 1.022)(x) is 254.636.
|
||||
return log(x)/log(1.022);
|
||||
}
|
||||
|
||||
|
||||
|
||||
uint32_t TeensyDisplay::frameCount()
|
||||
{
|
||||
return tft.frameCount();
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,8 @@
|
|||
#define __TEENSY_DISPLAY_H
|
||||
|
||||
#include <Arduino.h>
|
||||
#include <RA8875.h>
|
||||
#include <SPI.h>
|
||||
#include "RA8875_t4.h"
|
||||
|
||||
#include "physicaldisplay.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -115,8 +115,6 @@ int16_t TeensyFileManager::readDir(const char *where, const char *suffix, char *
|
|||
while (e.openNext(&outerDir, O_RDONLY)) {
|
||||
|
||||
// Skip MAC fork files
|
||||
// FIXME: strncpy
|
||||
strcpy(outputFN, e.name()); // and we need maxlen-1 for trailing '/' on directories
|
||||
e.getName(outputFN, maxlen-1); // -1 for trailing '/' on directories
|
||||
|
||||
if (outputFN[0] == '.') {
|
||||
|
|
@ -240,7 +238,7 @@ int TeensyFileManager::write(int8_t fd, const void *buf, int nbyte)
|
|||
uint32_t pos = fileSeekPositions[fd];
|
||||
|
||||
if (!cacheFile.seek(pos)) {
|
||||
printf("can't seek to %d\n", pos);
|
||||
printf("can't seek to %d\n", (int)pos);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue