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more audio cleanup
This commit is contained in:
Jorj Bauer
parent
89a6450a91
commit
5d85c2204a
181
apple/sy6522.cpp
181
apple/sy6522.cpp
@ -1,181 +0,0 @@
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#include "sy6522.h"
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#include <stdio.h>
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#include "globals.h"
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SY6522::SY6522()
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{
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ORB = ORA = 0;
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DDRB = DDRA = 0x00;
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T1_CTR = T2_CTR = 0;
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T1_CTR_LATCH = T2_CTR_LATCH = 0;
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ACR = 0x20; // free-running; FIXME: constant?
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PCR = 0xB0; // FIXME: ?
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IFR = 0x00; // FIXME: ?
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IER = 0x90; // FIXME: ?
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}
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uint8_t SY6522::read(uint8_t address)
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{
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switch (address) {
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case SY_ORB:
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return ORB;
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case SY_ORA:
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return ORA;
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case SY_DDRB:
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return DDRB;
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case SY_DDRA:
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return DDRA;
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case SY_TMR1L:
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IFR &= ~SY_IR_TIMER1;
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return (T1_CTR & 0xFF);
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case SY_TMR1H:
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return (T1_CTR >> 8);
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case SY_TMR1LL:
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return (T1_CTR_LATCH & 0xFF);
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case SY_TMR1HL:
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return (T1_CTR_LATCH >> 8);
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case SY_TMR2L:
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IFR &= ~SY_IR_TIMER2;
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return (T2_CTR & 0xFF);
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case SY_TMR2H:
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return (T2_CTR >> 8);
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case SY_SS:
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// FIXME: floating
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return 0xFF;
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case SY_ACR:
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return ACR;
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case SY_PCR:
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return PCR;
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case SY_IFR:
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return IFR;
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case SY_IER:
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return 0x80 | IER;
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case SY_ORANOHS:
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return ORA;
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}
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return 0xFF;
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}
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void SY6522::write(uint8_t address, uint8_t val)
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{
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switch (address) {
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case SY_ORB:
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val &= DDRB;
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ORB = val;
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ay8910[0].write(val, ORA & DDRA);
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return;
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case SY_ORA:
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ORA = val & DDRA;
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return;
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case SY_DDRB:
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DDRB = val;
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return;
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case SY_DDRA:
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DDRA = val;
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return;
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case SY_TMR1L:
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case SY_TMR1LL:
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T1_CTR_LATCH = (T1_CTR_LATCH & 0xFF00) | val;
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return;
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case SY_TMR1H:
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IFR &= SY_IR_TIMER1;
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// Update IFR?
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IFR &= 0x7F;
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if (IFR & IER) {
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// an interrupt is happening; keep the IE flag on
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IFR |= 0x80;
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}
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// FIXME: clear interrupt flag
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T1_CTR_LATCH = (T1_CTR_LATCH & 0x00FF) | (val << 8);
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T1_CTR = T1_CTR_LATCH;
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// FIXME: start timer?
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return;
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case SY_TMR1HL:
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T1_CTR_LATCH = (T1_CTR_LATCH & 0x00FF) | (val << 8);
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// FIXME: clear interrupt flag
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return;
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case SY_TMR2L:
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T2_CTR_LATCH = (T2_CTR_LATCH & 0xFF00) | val;
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return;
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case SY_TMR2H:
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// FIXME: clear timer2 interrupt flag
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T2_CTR_LATCH = (T2_CTR_LATCH & 0x00FF) | (val << 8);
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T2_CTR = T2_CTR_LATCH;
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return;
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case SY_SS:
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// FIXME: what is this for?
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return;
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case SY_ACR:
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ACR = val;
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break;
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case SY_PCR:
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PCR = val;
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break;
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case SY_IFR:
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// Clear whatever low bits are set in IFR.
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val |= 0x80;
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val ^= 0x7F;
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IFR &= val;
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break;
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case SY_IER:
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if (val & 0x80) {
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// Set bits based on val
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val &= 0x7F;
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IER |= val;
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// FIXME: start timer if necessary?
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} else {
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// Clear whatever low bits are set in IER.
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val |= 0x80;
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val ^= 0x7F;
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IER &= val;
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// FIXME: stop timer if it's running?
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}
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return;
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case SY_ORANOHS:
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// FIXME: what is this for?
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return;
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}
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}
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void SY6522::update(uint32_t cycles)
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{
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/* Update 6522 timers */
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// ...
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/*
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SY_IR_CA2 = 1,
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SY_IR_CA1 = 2,
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SY_IR_SHIFTREG = 4,
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SY_IR_CB2 = 8,
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SY_IR_CB1 = 16,
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SY_IR_TIMER2 = 32,
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SY_IR_TIMER1 = 64,
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SY_IER_SETCLEAR = 128,
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SY_IFR_IRQ = 128
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*/
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/* Check for 6522 interrupts */
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if (IFR & 0x80) {
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g_cpu->stageIRQ();
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}
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/* Update the attached 8910 chip(s) */
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ay8910[0].update(cycles);
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}
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@ -1,67 +0,0 @@
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#ifndef __SY6522_H
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#define __SY6522_H
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#include <stdint.h>
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#include "ay8910.h"
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// 6522 interface registers
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enum {
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SY_ORB = 0x00, // ORB
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SY_ORA = 0x01, // ORA
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SY_DDRB = 0x02, // DDRB
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SY_DDRA = 0x03, // DDRA
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SY_TMR1L = 0x04, // TIMER1L_COUNTER
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SY_TMR1H = 0x05, // TIMER1H_COUNTER
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SY_TMR1LL = 0x06, // TIMER1L_LATCH
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SY_TMR1HL = 0x07, // TIMER1H_LATCH
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SY_TMR2L = 0x08, // TIMER2L
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SY_TMR2H = 0x09, // TIMER2H
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SY_SS = 0x0a, // SERIAL_SHIFT
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SY_ACR = 0x0b, // ACR
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SY_PCR = 0x0c, // PCR
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SY_IFR = 0x0d, // IFR
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SY_IER = 0x0e, // IER
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SY_ORANOHS = 0x0f // ORA_NO_HS
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};
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// IFR and IER share the names of all but the high bit
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enum {
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SY_IR_CA2 = 1,
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SY_IR_CA1 = 2,
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SY_IR_SHIFTREG = 4,
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SY_IR_CB2 = 8,
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SY_IR_CB1 = 16,
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SY_IR_TIMER2 = 32,
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SY_IR_TIMER1 = 64,
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SY_IER_SETCLEAR = 128,
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SY_IFR_IRQ = 128
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};
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class SY6522 {
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public:
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SY6522();
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uint8_t read(uint8_t address);
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void write(uint8_t address, uint8_t val);
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void update(uint32_t cycles);
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private:
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uint8_t ORB; // port B
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uint8_t ORA; // port A
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uint8_t DDRB; // data direction register
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uint8_t DDRA; //
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uint16_t T1_CTR; // counters
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uint16_t T1_CTR_LATCH;
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uint16_t T2_CTR;
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uint16_t T2_CTR_LATCH;
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uint8_t ACR; // Aux Control Register
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uint8_t PCR; // Peripheral Control Register
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uint8_t IFR; // Interrupt Flag Register
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uint8_t IER; // Interrupt Enable Register
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AY8910 ay8910[1]; // FIXME: an array in case we support more than one ... ?
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};
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#endif
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@ -1 +0,0 @@
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../apple/sy6522.cpp
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@ -1 +0,0 @@
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../apple/sy6522.h
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@ -226,7 +226,6 @@ void runCPU()
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((AppleVM *)g_vm)->cpuMaintenance(g_cpu->cycles);
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g_speaker->maintainSpeaker(g_cpu->cycles);
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// The CPU of the Apple //e ran at 1.023 MHz. Adjust when we think
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// the next instruction should run based on how long the execution
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// was ((1000/1023) * numberOfCycles) - which is about 97.8%.
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@ -252,6 +251,19 @@ void loop()
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// Only redraw if the CPU is caught up; and then we'll suspend the
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// CPU to draw a full frame.
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// Note that this breaks audio, b/c it's real-time and requires the
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// CPU running to change the audio line's value. So we need to EITHER
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//
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// - delay the audio line by at least the time it takes for one
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// display update, OR
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// - lock display updates so the CPU can update the memory, but we
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// keep drawing what was going to be displayed
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//
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// The Timer1.stop()/start() is bad. Using it, the display doesn't
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// tear; but the audio is also broken. Taking it out, audio is good
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// but the display tears.
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Timer1.stop();
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g_vm->vmdisplay->needsRedraw();
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AiieRect what = g_vm->vmdisplay->getDirtyRect();
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