mirror of https://github.com/JorjBauer/aiie.git
cleaned up bank switching; confirmed against ITA2E and UTA2E
This commit is contained in:
Jorj Bauer
parent
c2e117745f
commit
7293bd42e6
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@ -101,10 +101,11 @@ void AppleMMU::write(uint16_t address, uint8_t v)
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}
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// Don't allow writes to ROM
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// Hard ROM, I/O, slots, whatnot
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if (address >= 0xC100 && address <= 0xCFFF)
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return;
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// Bank-switched ROM/RAM areas
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if (address >= 0xD000 && address <= 0xFFFF && !writebsr) {
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// memory-protected, so don't allow writes
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return;
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}
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@ -147,11 +148,9 @@ void AppleMMU::handleMemorySwitches(uint16_t address, uint16_t lastSwitch)
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case 0xC000: // CLR80STORE
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switches &= ~S_80STORE;
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updateMemoryPages();
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break;
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case 0xC001: // SET80STORE
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switches |= S_80STORE;
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updateMemoryPages();
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break;
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case 0xC002: // CLRAUXRD read from main 48k RAM
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auxRamRead = false;
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@ -184,62 +183,53 @@ void AppleMMU::handleMemorySwitches(uint16_t address, uint16_t lastSwitch)
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slot3rom = true;
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break;
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// these are probably read/write ?
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case 0xC080: // READBSR2 and shadow copy
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case 0xC084:
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bank1 = false; // LC RAM bank2, Read and Write-prot RAM
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readbsr = true; // read from bank2
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writebsr = false; // write-protected
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break;
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case 0xC081: // ROMIN
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case 0xC085:
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bank1 = false; // LC RAM bank2, read ROM, write-enable RAM
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readbsr = false; // if it's read twice in a row
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writebsr = writebsr || ((lastSwitch & 0xF3) == (address & 0xF3));
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break;
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// Registers C080 - C08F control bank switching.
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case 0xC080:
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case 0xC081:
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case 0xC082:
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case 0xC083:
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case 0xC084:
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case 0xC085:
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case 0xC086:
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bank1 = false; // LC RAM bank2, Read ROM instead of RAM,
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readbsr = false; // WR-protect RAM
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writebsr = false;
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break;
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case 0xC083: // READWRBSR2
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case 0xC087:
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bank1 = false;
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readbsr = true;
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writebsr = writebsr || ((lastSwitch & 0xF3) == (address & 0xF3));
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break;
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case 0xC088: // READBSR1
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case 0xC088:
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case 0xC089:
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case 0xC08A:
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case 0xC08B:
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case 0xC08C:
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bank1 = true;
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readbsr = true;
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writebsr = false;
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break;
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case 0xC089: // WRITEBSR1
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case 0xC08D:
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bank1 = true;
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readbsr = false;
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writebsr = writebsr || ((lastSwitch & 0xF3) == (address & 0xF3));
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break;
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case 0xC08A: // OFFBSR1
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case 0xC08E:
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bank1 = true;
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readbsr = false;
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writebsr = false;
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break;
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case 0xC08B: // READWRBSR1
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case 0xC08F:
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bank1 = true;
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readbsr = true;
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writebsr = writebsr || ((lastSwitch & 0xF3) == (address & 0xF3));
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// Per ITA2E, p. 286:
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// (address & 0x08) controls whether or not we are selecting from bank2. Per table 8-2,
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// bank2 is active if address & 0x08 is zero. So if the bit is on, it's bank 1.
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bank2 = (address & 0x08) ? false : true;
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// (address & 0x04) is unused.
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// (address & 0x02) is read-select: if it is set the same as
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// (address & 0x01) then readbsr is true.
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readbsr = ((address & 0x02) >> 1) == (address & 0x01);
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// (address & 0x01) is write-select: if 1, we write BSR RAM; if 0, we write ROM.
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// But it's a little more complicated than readbsr.
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// Per UTA2E p. 5-23:
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// "Writing to high RAM is enabled when the HRAMWRT' soft switch
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// is reset. ... It is reset by even read access or any write
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// access in the $C08X range. HRAMWRT' is reset by odd read
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// access in the $C08X range when PRE-WRITE is set. It is set by
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// even access in the CC08X range. Any other type of access
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// causes HRAMWRT' to hold its current state."
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if (address & 0x01) {
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if (preWriteFlag)
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writebsr = 1;
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// Per UTA2E, p. 5-23: any other preWriteFlag leaves writebsr unchanged.
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} else {
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writebsr = false;
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}
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break;
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}
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@ -325,6 +315,11 @@ uint8_t AppleMMU::readSwitches(uint16_t address)
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case 0xC08F:
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// but read does affect these, same as write
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handleMemorySwitches(address, lastReadSwitch);
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// UTA2E, p. 5-23: preWrite is set by odd read access, and reset
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// by even read access
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preWriteFlag = (address & 0x01);
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break;
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case 0xC00C: // CLR80VID disable 80-col video mode
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@ -349,7 +344,7 @@ uint8_t AppleMMU::readSwitches(uint16_t address)
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case 0xC011: // RDLCBNK2
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return bank1 ? 0x00 : 0x80;
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return bank2 ? 0x80 : 0x00;
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case 0xC012: // RDLCRAM
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return readbsr ? 0x80 : 0x00;
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case 0xC013: // RDRAMRD
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@ -606,18 +601,6 @@ void AppleMMU::writeSwitches(uint16_t address, uint8_t v)
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writePages[0xC0][0x64] = writePages[0xC0][0x65] = 0xFF;
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break;
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case 0xC000:
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case 0xC001:
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case 0xC002:
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case 0xC003:
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case 0xC004:
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case 0xC005:
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case 0xC006:
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case 0xC007:
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case 0xC008:
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case 0xC009:
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case 0xC00A:
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case 0xC00B:
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case 0xC080:
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case 0xC081:
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case 0xC082:
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@ -634,6 +617,21 @@ void AppleMMU::writeSwitches(uint16_t address, uint8_t v)
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case 0xC08D:
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case 0xC08E:
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case 0xC08F:
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// UTA2E, p. 5-23: preWrite is reset by any write access to these
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preWriteFlag = 0;
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// fall through...
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case 0xC000:
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case 0xC001:
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case 0xC002:
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case 0xC003:
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case 0xC004:
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case 0xC005:
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case 0xC006:
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case 0xC007:
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case 0xC008:
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case 0xC009:
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case 0xC00A:
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case 0xC00B:
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handleMemorySwitches(address, lastWriteSwitch);
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break;
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@ -679,13 +677,19 @@ void AppleMMU::resetRAM()
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{
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switches = S_TEXT;
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bank1 = true;
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// Per UTA2E, p. 5-23:
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// When a system reset occurs, all MMU soft switches are reset (turned off).
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bank2 = false;
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auxRamRead = auxRamWrite = false;
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readbsr = writebsr = false;
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altzp = false;
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intcxrom = false;
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slot3rom = false;
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preWriteFlag = false;
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// Clear all the pages
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for (uint8_t i=0; i<0xFF; i++) {
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for (uint8_t j=0; j<5; j++) {
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if (ramPages[i][j]) {
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@ -694,42 +698,42 @@ void AppleMMU::resetRAM()
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}
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}
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}
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// and set our expectation of what we're reading from/writing to
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readPages[i] = writePages[i] = ramPages[i][0];
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}
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// Load ROM
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// Load system ROM
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for (uint16_t i=0x80; i<=0xFF; i++) {
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for (uint16_t k=0; k<0x100; k++) {
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uint16_t idx = ((i-0x80) << 8) | k;
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#ifdef TEENSYDUINO
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for (uint16_t i=0x80; i<=0xFF; i++) {
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for (uint16_t k=0; k<0x100; k++) {
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uint16_t idx = ((i-0x80) << 8) | k;
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uint8_t v = pgm_read_byte(&romData[idx]);
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for (uint8_t j=0; j<5; j++) {
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if (ramPages[i][j]) {
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ramPages[i][j][k] = v;
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}
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}
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}
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}
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#else
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for (uint16_t i=0x80; i<=0xFF; i++) {
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for (uint16_t k=0; k<0x100; k++) {
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uint16_t idx = ((i-0x80) << 8) | k;
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uint8_t v = romData[idx];
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for (uint8_t j=0; j<5; j++) {
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if (ramPages[i][j]) {
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ramPages[i][j][k] = v;
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#endif
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for (int j=0; j<5; j++) {
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// FIXME: not sure why this has to update pages [0] and [1] to
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// work; find out what the //e really did
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for (uint8_t j=0; j<2; j++) {
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if (ramPages[i][j]) {
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ramPages[i][j][k] = v;
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}
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}
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}
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}
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}
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#endif
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// have each slot load its ROM
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for (uint8_t slotnum = 0; slotnum <= 7; slotnum++) {
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if (slots[slotnum]) {
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slots[slotnum]->loadROM(ramPages[0xC0 + slotnum][0]);
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}
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}
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// update the memory read/write flags &c. Not strictly necessary, if
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// we're really setting all the RAM flags to the right default
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// settings above - but better safe than sorry?
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updateMemoryPages();
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}
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void AppleMMU::setSlot(int8_t slotnum, Slot *peripheral)
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@ -820,6 +824,7 @@ void AppleMMU::updateMemoryPages()
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}
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}
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// set zero-page & stack pages based on altzp flag
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if (altzp) {
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for (uint8_t idx = 0x00; idx < 0x02; idx++) {
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readPages[idx] = ramPages[idx][1];
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@ -832,33 +837,42 @@ void AppleMMU::updateMemoryPages()
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}
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}
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// Set bank-switched ram reading from readbsr & bank2
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if (readbsr) {
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if (bank1) {
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// 0xD0 - 0xE0 has 4 possible banks:
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if (!bank2) {
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// Bank 1 RAM: either in main RAM (1) or in the extended memory
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// card (3):
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for (uint8_t idx = 0xd0; idx < 0xe0; idx++) {
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readPages[idx] = ramPages[idx][altzp ? 2 : 1];
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readPages[idx] = ramPages[idx][altzp ? 3 : 1];
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}
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} else {
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// Bank 2 RAM: either in main RAM (2) or in the extended memory
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// card (4):
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for (uint8_t idx = 0xd0; idx < 0xe0; idx++) {
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readPages[idx] = ramPages[idx][altzp ? 4 : 3];
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readPages[idx] = ramPages[idx][altzp ? 4 : 2];
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}
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}
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// ... but 0xE0 - 0xFF has just the motherboard RAM (1) and
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// extended memory card RAM (2):
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for (uint16_t idx = 0xe0; idx < 0x100; idx++) {
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readPages[idx] = ramPages[idx][altzp ? 2 : 1];
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}
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} else {
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// Built-in ROM
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for (uint16_t idx = 0xd0; idx < 0x100; idx++) {
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readPages[idx] = ramPages[idx][0];
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}
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}
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if (writebsr) {
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if (bank1) {
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if (!bank2) {
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for (uint8_t idx = 0xd0; idx < 0xe0; idx++) {
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writePages[idx] = ramPages[idx][altzp ? 2 : 1];
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writePages[idx] = ramPages[idx][altzp ? 3 : 1];
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}
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} else {
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for (uint8_t idx = 0xd0; idx < 0xe0; idx++) {
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writePages[idx] = ramPages[idx][altzp ? 4 : 3];
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writePages[idx] = ramPages[idx][altzp ? 4 : 2];
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}
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}
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for (uint16_t idx = 0xe0; idx < 0x100; idx++) {
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@ -66,13 +66,15 @@ class AppleMMU : public MMU {
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public: // 'public' for debugging
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bool auxRamRead;
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bool auxRamWrite;
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bool bank1;
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bool bank2;
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bool readbsr;
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bool writebsr;
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bool altzp;
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bool intcxrom;
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bool slot3rom;
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bool preWriteFlag; // see UTA2E p. 5-23
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Slot *slots[8]; // slots 0-7
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uint8_t *ramPages[0x100][5];
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