2023-01-07 07:15:21 +00:00
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; This program consists of 3 state machines communicating using state machine IRQs
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; - hsync generates the hsync signal and drives the vsync and data state machines
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; - vsync generates the vsync signal and drives the data state machine
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; - data generates the pixel data stream, synchronized with the hsync and vsync IRQs
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; generated by their respective timing state machine
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;
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; Overall timing (in pixel times)
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;
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; Time | hsync action | vsync action | data action
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; ------------------------------------------------------------------------------------------------
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; 0 | assert lineclk IRQ | |
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; 8 | | wait & reset lineclk IRQ |
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; 16 | set hsync signal low | set vsync signal high/low |
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; 112 | set hsync signal high | |
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; 144 | | assert vsync IRQ |
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; 144.5 | | | 'wait irq vsync' completes
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; 152 | assert hsync IRQ | |
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; 152.5 | | | 'wait irq hsync' completes
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; 160 | deassert hsync IRQ | | first pixel RGB data out
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; 161 | | | second pixel RGB data out
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; 216 | | deassert vsync IRQ |
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.define LINECLK_IRQ_NUM 4
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.define HSYNC_IRQ_NUM 5
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.define VSYNC_IRQ_NUM 6
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; Run at 4 * pixel frequency
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.program vga_data
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.origin 0
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.wrap_target
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pixel_out:
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out PINS, 9
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out PC, 7
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public wait_vsync:
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wait 0 irq VSYNC_IRQ_NUM
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public wait_hsync:
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2023-01-17 01:36:00 +00:00
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wait 0 irq HSYNC_IRQ_NUM [1]
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2023-01-07 07:15:21 +00:00
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public extend_7:
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nop [1]
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public extend_6:
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nop [1]
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public extend_5:
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nop [1]
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public extend_4:
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nop [1]
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public extend_3:
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nop [1]
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public extend_2:
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nop [1]
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public extend_1:
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nop [1]
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.wrap
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; Run at pixel frequency / 8
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.program vga_hsync
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pull ; load timing loop count from the CPU
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.wrap_target
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irq set LINECLK_IRQ_NUM [1] ; (0) assert lineclk IRQ
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set PINS, 0 [11] ; (16) set hsync signal low
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set PINS, 1 [4] ; (112) set hsync signal high
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irq clear HSYNC_IRQ_NUM ; (152) assert hsync IRQ
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irq set HSYNC_IRQ_NUM ; (160) deassert hsync IRQ
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; Wait until the next hsync should be generated
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mov X, OSR
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skip_loop:
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jmp X--, skip_loop
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.wrap
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; Run at pixel frequency / 8
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.program vga_vsync
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pull ; load timing loop count from the CPU
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.wrap_target
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wait 1 irq LINECLK_IRQ_NUM ; (8) wait & reset lineclk IRQ
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set pins, 0 [15] ; (16) set vsync signal low
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irq clear VSYNC_IRQ_NUM [8] ; (144) assert vsync IRQ
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irq set VSYNC_IRQ_NUM ; (216) deassert vsync IRQ
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wait 1 irq LINECLK_IRQ_NUM
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wait 1 irq LINECLK_IRQ_NUM ; (8) wait for lineclk & reset
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set pins, 1 ; (16) set vsync signal high
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; Skip the remaining scanlines
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mov X, OSR
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skip_loop:
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wait 1 irq LINECLK_IRQ_NUM
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jmp X--, skip_loop
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.wrap
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; Pixel Frequency: 25.175MHz
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;
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; Horizontal timing
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;
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; 640x480@60Hz and 640x400@70Hz (pulse low)
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; Scanline part | Pixels | Time [µs]
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; ------------------------------------------
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; Visible area | 640 | 25.422045680238
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; Front porch | 16 | 0.63555114200596
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; Sync pulse | 96 | 3.8133068520357
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; Back porch | 48 | 1.9066534260179
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; Whole line | 800 | 31.777557100298
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;
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; Vertical timing
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;
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; [640x480@60Hz (pulse low)] || [640x400@70Hz (pulse high)]
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; Frame part | Lines | Time [ms] || Lines | Time [ms]
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;------------------------------------------------------------------------
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; Visible area | 480 | 15.253227408143 || 400 | 12.711022840119
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; Front porch | 10 | 0.31777557100298 || 12 | 0.38133068520357
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; Sync pulse | 2 | 0.063555114200596 || 2 | 0.063555114200596
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; Back porch | 33 | 1.0486593843098 || 35 | 1.1122144985104
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; Whole frame | 525 | 16.683217477656 || 449 | 14.268123138034
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