mirror of
https://github.com/V2RetroComputing/analog.git
synced 2024-06-06 04:29:32 +00:00
d9be2ed9cd
New autodetect routines for Apple II+, IIe (Platinum), IIgs (ROM03). Timing tweaks to improve compatibility on IIgs and IIe. Corrected text rendering on all supported machines. Initial Super HiRes support (not recommended to use at this time) Monochrome DHGR and HGR support activated with IIgs MONOCOLOR or NEWVID registers. 80 Column mode on IIe and IIgs.
96 lines
3.2 KiB
C
96 lines
3.2 KiB
C
#include <string.h>
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#include <hardware/pio.h>
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#include "common/config.h"
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#include "common/buffers.h"
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#include "abus.pio.h"
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#include "fs/businterface.h"
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#include "fs/fs.h"
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static inline void __time_critical_func(shadow_memory)(uint32_t address, uint32_t value) {
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// Shadow parts of the Apple's memory by observing the bus write cycles
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if((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0) {
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if(address < 0x200) {
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if((soft_switches & (SOFTSW_80STORE | SOFTSW_AUXZP)) == (SOFTSW_80STORE | SOFTSW_AUXZP)) {
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private_memory[address] = value & 0xff;
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} else {
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apple_memory[address] = value & 0xff;
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}
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} else if((address < 0xC000) || (address >= 0xD000)) {
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if((soft_switches & (SOFTSW_80STORE | SOFTSW_AUX_WRITE)) == (SOFTSW_80STORE | SOFTSW_AUX_WRITE)) {
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private_memory[address] = value & 0xff;
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} else {
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apple_memory[address] = value & 0xff;
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}
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}
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}
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if(CARD_SELECT) {
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if(CARD_DEVSEL) {
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if((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0) {
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apple_memory[address] = value;
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if((address & 0xCF8F) == 0xC08F)
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fs_handler((address & 0x70) >> 4);
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}
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}
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if(CARD_IOSTROBE) {
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apple_memory[address] = value;
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}
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// Config memory in card slot-rom address space
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if(CARD_IOSEL) {
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if((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0) {
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config_memory[address & 0x1F] = value;
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if((address & 0xFF) == 0xFF)
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config_handler();
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}
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}
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}
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// Shadow the soft-switches by observing all read & write bus cycles
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if((soft_switches & SOFTSW_IIE_REGS) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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if((address & 0xff80) == 0xc000) {
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switch(address & 0x7f) {
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case 0x00:
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soft_switches &= ~SOFTSW_80STORE;
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break;
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case 0x01:
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soft_switches |= SOFTSW_80STORE;
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break;
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case 0x04:
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soft_switches &= ~SOFTSW_AUX_WRITE;
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break;
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case 0x05:
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soft_switches |= SOFTSW_AUX_WRITE;
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break;
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case 0x08:
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soft_switches &= ~SOFTSW_AUXZP;
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break;
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case 0x09:
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soft_switches |= SOFTSW_AUXZP;
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break;
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}
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}
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}
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}
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void __time_critical_func(fs_businterface)() {
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while(v2mode == MODE_DIAG) {
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uint32_t value = pio_sm_get_blocking(CONFIG_ABUS_PIO, ABUS_MAIN_SM);
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uint32_t dout;
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uint32_t address = (value >> 10) & 0xffff;
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if((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) != 0) {
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if(CARD_SELECT) {
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dout = apple_memory[address];
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// device read access
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pio_sm_put_blocking(CONFIG_ABUS_PIO, ABUS_DEVICE_READ_SM, dout);
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}
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}
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shadow_memory(address, value);
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}
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}
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