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6502tests/test.c
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313
6502tests/test.c
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/*
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Bunch of unit tests I wrote during the development of the emulator.
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These are very nasty and not really release worthy but someone might
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find them useful!
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Copyright (c) 2015, Damian Peckett <damian.peckett@gmail.com>
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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//TEST Functions
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#include "test/testAdc.c"
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#include "test/testAnd.c"
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#include "test/testAsl.c"
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#include "test/testBcc.c"
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#include "test/testBcs.c"
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#include "test/testBeq.c"
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#include "test/testBit.c"
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#include "test/testBmi.c"
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#include "test/testBne.c"
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#include "test/testBpl.c"
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#include "test/testBrk.c"
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#include "test/testBvc.c"
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#include "test/testBvs.c"
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#include "test/testClear.c"
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#include "test/testCmp.c"
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#include "test/testCpx.c"
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#include "test/testCpy.c"
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#include "test/testDec.c"
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#include "test/testEor.c"
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#include "test/testInc.c"
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#include "test/testJmp.c"
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#include "test/testLd.c"
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#include "test/testLsr.c"
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#include "test/testOra.c"
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#include "test/testPha.c"
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#include "test/testPhp.c"
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#include "test/testPla.c"
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#include "test/testPlp.c"
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#include "test/testRol.c"
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#include "test/testRor.c"
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#include "test/testRti.c"
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#include "test/testRts.c"
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#include "test/testSbc.c"
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#include "test/testSet.c"
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#include "test/testSta.c"
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#include "test/testSt.c"
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#include "test/testTransfer.c"
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void testAdc() {
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printf("testAdcImmediate: %d\r\n", testAdcImmediate());
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printf("testAdcZeropage: %d\r\n", testAdcZeropage());
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printf("testAdcZeropageX: %d\r\n", testAdcZeropageX());
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printf("testAdcAbsolute: %d\r\n", testAdcAbsolute());
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printf("testAdcAbsoluteX: %d\r\n", testAdcAbsoluteX());
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printf("testAdcAbsoluteY: %d\r\n", testAdcAbsoluteY());
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printf("testAdcIndirectX: %d\r\n", testAdcIndirectX());
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printf("testAdcIndirectY: %d\r\n", testAdcIndirectY());
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}
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void testAnd() {
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printf("testAndImmediate: %d\r\n", testAndImmediate());
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printf("testAndZeropage: %d\r\n", testAndZeropage());
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printf("testAndZeropageX: %d\r\n", testAndZeropageX());
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printf("testAndAbsolute: %d\r\n", testAndAbsolute());
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printf("testAndAbsoluteX: %d\r\n", testAndAbsoluteX());
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printf("testAndAbsoluteY: %d\r\n", testAndAbsoluteY());
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printf("testAndIndirectX: %d\r\n", testAndIndirectX());
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printf("testAndIndirectY: %d\r\n", testAndIndirectY());
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}
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void testAsl() {
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printf("testAslImplied: %d\r\n", testAslImplied());
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printf("testAslZeropage: %d\r\n", testAslZeropage());
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printf("testAslZeropageX: %d\r\n", testAslZeropageX());
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printf("testAslAbsolute: %d\r\n", testAslAbsolute());
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printf("testAslAbsoluteX: %d\r\n", testAslAbsoluteX());
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}
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void testBranches() {
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printf("testBccImplied: %d\r\n", testBccImplied());
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printf("testBcsImplied: %d\r\n", testBcsImplied());
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printf("testBeqImplied: %d\r\n", testBeqImplied());
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printf("testBmiImplied: %d\r\n", testBmiImplied());
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printf("testBneImplied: %d\r\n", testBneImplied());
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printf("testBplImplied: %d\r\n", testBplImplied());
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printf("testBvcImplied: %d\r\n", testBvcImplied());
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printf("testBvsImplied: %d\r\n", testBvsImplied());
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}
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void testBit() {
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printf("testBitZeropage: %d\r\n", testBitZeropage());
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printf("testBitAbsolute: %d\r\n", testBitAbsolute());
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}
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void testBrk() {
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printf("testBrkImplied: %d\r\n", testBrkImplied());
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}
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void testClear() {
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printf("testClcImplied: %d\r\n", testClcImplied());
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printf("testCldImplied: %d\r\n", testCldImplied());
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printf("testCliImplied: %d\r\n", testCliImplied());
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printf("testClvImplied: %d\r\n", testClvImplied());
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}
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void testCompare() {
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printf("testCmpImmediate: %d\r\n", testCmpImmediate());
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printf("testCmpZeropage: %d\r\n", testCmpZeropage());
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printf("testCmpZeropageX: %d\r\n", testCmpZeropageX());
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printf("testCmpAbsolute: %d\r\n", testCmpAbsolute());
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printf("testCmpAbsoluteX: %d\r\n", testCmpAbsoluteX());
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printf("testCmpAbsoluteY: %d\r\n", testCmpAbsoluteY());
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printf("testCmpIndirectX: %d\r\n", testCmpIndirectX());
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printf("testCmpIndirectY: %d\r\n", testCmpIndirectY());
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printf("testCpxImmediate: %d\r\n", testCpxImmediate());
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printf("testCpxZeropage: %d\r\n", testCpxZeropage());
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printf("testCpxAbsolute: %d\r\n", testCpxAbsolute());
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printf("testCpyImmediate: %d\r\n", testCpyImmediate());
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printf("testCpyZeropage: %d\r\n", testCpyZeropage());
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printf("testCpyAbsolute: %d\r\n", testCpyAbsolute());
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}
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void testDec() {
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printf("testDecZeropage: %d\r\n", testDecZeropage());
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printf("testDecZeropageX: %d\r\n", testDecZeropageX());
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printf("testDecAbsolute: %d\r\n", testDecAbsolute());
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printf("testDexImplied: %d\r\n", testDexImplied());
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printf("testDeyImplied: %d\r\n", testDeyImplied());
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}
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void testEor() {
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printf("testEorImmediate: %d\r\n", testEorImmediate());
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printf("testEorZeropage: %d\r\n", testEorZeropage());
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printf("testEorZeropageX: %d\r\n", testEorZeropageX());
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printf("testEorAbsolute: %d\r\n", testEorAbsolute());
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printf("testEorAbsoluteX: %d\r\n", testEorAbsoluteX());
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printf("testEorAbsoluteY: %d\r\n", testEorAbsoluteY());
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printf("testEorIndirectX: %d\r\n", testEorIndirectX());
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printf("testEorIndirectY: %d\r\n", testEorIndirectY());
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}
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void testInc() {
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printf("testIncZeropage: %d\r\n", testIncZeropage());
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printf("testIncZeropageX: %d\r\n", testIncZeropageX());
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printf("testIncAbsolute: %d\r\n", testIncAbsolute());
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printf("testInxImplied: %d\r\n", testInxImplied());
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printf("testInyImplied: %d\r\n", testInyImplied());
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}
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void testJmp() {
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printf("testJmpAbsolute: %d\r\n", testJmpAbsolute());
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printf("testJmpIndirect: %d\r\n", testJmpIndirect());
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printf("testJsrAbsolute: %d\r\n", testJsrAbsolute());
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}
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void testLoads() {
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printf("testLdaImmediate: %d\r\n", testLdaImmediate());
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printf("testLdaZeropage: %d\r\n", testLdaZeropage());
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printf("testLdaZeropageX: %d\r\n", testLdaZeropageX());
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printf("testLdaAbsolute: %d\r\n", testLdaAbsolute());
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printf("testLdaAbsoluteX: %d\r\n", testLdaAbsoluteX());
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printf("testLdaAbsoluteY: %d\r\n", testLdaAbsoluteY());
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printf("testLdaIndirectX: %d\r\n", testJmpAbsolute());
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printf("testLdaIndirectY: %d\r\n", testLdaIndirectY());
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printf("testLdxImmediate: %d\r\n", testLdxImmediate());
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printf("testLdxZeropage: %d\r\n", testLdxZeropage());
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printf("testLdxZeropageY: %d\r\n", testLdxZeropageY());
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printf("testLdxAbsolute: %d\r\n", testLdxAbsolute());
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printf("testLdxAbsoluteY: %d\r\n", testLdxAbsoluteY());
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printf("testLdyImmediate: %d\r\n", testLdyImmediate());
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printf("testLdyZeropage: %d\r\n", testLdyZeropage());
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printf("testLdyZeropageX: %d\r\n", testLdyZeropageX());
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printf("testLdyAbsolute: %d\r\n", testLdyAbsolute());
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printf("testLdyAbsoluteX: %d\r\n", testLdyAbsoluteX());
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}
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void testLsr() {
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printf("testLsrImplied: %d\r\n", testLsrImplied());
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printf("testLsrZeropage: %d\r\n", testLsrZeropage());
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printf("testLdyZeropageX: %d\r\n", testLsrZeropageX());
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printf("testLsrAbsolute: %d\r\n", testLsrAbsolute());
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printf("testLsrAbsoluteX: %d\r\n", testLsrAbsoluteX());
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}
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void testOra() {
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printf("testOraImmediate: %d\r\n", testOraImmediate());
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printf("testOraZeropage: %d\r\n", testOraZeropage());
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printf("testOraZeropageX: %d\r\n", testOraZeropageX());
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printf("testOraAbsolute: %d\r\n", testOraAbsolute());
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printf("testOraAbsoluteX: %d\r\n", testOraAbsoluteX());
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printf("testOraAbsoluteY: %d\r\n", testOraAbsoluteY());
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printf("testOraIndirectX: %d\r\n", testOraIndirectX());
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printf("testOraIndirectY: %d\r\n", testOraIndirectY());
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}
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void testStack() {
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printf("testPhaImplied: %d\r\n", testPhaImplied());
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printf("testPhpImplied: %d\r\n", testPhpImplied());
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printf("testPlaImplied: %d\r\n", testPlaImplied());
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printf("testPlpImplied: %d\r\n", testPlpImplied());
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}
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void testRotate() {
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printf("testRolImplied: %d\r\n", testRolImplied());
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printf("testRolZeropage: %d\r\n", testRolZeropage());
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printf("testRolZeropageX: %d\r\n", testRolZeropageX());
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printf("testRolAbsolute: %d\r\n", testRolAbsolute());
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printf("testRolAbsoluteX: %d\r\n", testRolAbsoluteX());
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printf("testRorImplied: %d\r\n", testRorImplied());
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printf("testRorZeropage: %d\r\n", testRorZeropage());
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printf("testRorZeropageX: %d\r\n", testRorZeropageX());
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printf("testRorAbsolute: %d\r\n", testRorAbsolute());
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printf("testRorAbsoluteX: %d\r\n", testRorAbsoluteX());
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}
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void testReturn() {
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printf("testRtiImplied: %d\r\n", testRtiImplied());
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printf("testRtsImplied: %d\r\n", testRtsImplied());
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}
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void testSbc() {
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printf("testSbcImmediate: %d\r\n", testSbcImmediate());
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printf("testSbcZeropage: %d\r\n", testSbcZeropage());
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printf("testSbcZeropageX: %d\r\n", testSbcZeropageX());
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printf("testSbcAbsolute: %d\r\n", testSbcAbsolute());
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printf("testSbcAbsoluteX: %d\r\n", testSbcAbsoluteX());
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printf("testSbcAbsoluteY: %d\r\n", testSbcAbsoluteY());
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printf("testSbcIndirectX: %d\r\n", testSbcIndirectX());
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printf("testSbcIndirectY: %d\r\n", testSbcIndirectY());
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}
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void testSet() {
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printf("testSecImplied: %d\r\n", testSecImplied());
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printf("testSedImplied: %d\r\n", testSedImplied());
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printf("testSeiImplied: %d\r\n", testSeiImplied());
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}
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void testSta() {
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printf("testStaZeropage: %d\r\n", testStaZeropage());
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printf("testStaZeropageX: %d\r\n", testStaZeropageX());
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printf("testStaAbsolute: %d\r\n", testStaAbsolute());
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printf("testStaAbsoluteX: %d\r\n", testStaAbsoluteX());
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printf("testStaAbsoluteY: %d\r\n", testStaAbsoluteY());
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printf("testStaIndirectX: %d\r\n", testStaIndirectX());
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printf("testStaIndirectY: %d\r\n", testStaIndirectY());
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}
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void testStores() {
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printf("testStxZeropage: %d\r\n", testStxZeropage());
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printf("testStxZeropageY: %d\r\n", testStxZeropageY());
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printf("testStxAbsolute: %d\r\n", testStxAbsolute());
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printf("testStyZeropage: %d\r\n", testStyZeropage());
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printf("testStyZeropageX: %d\r\n", testStyZeropageX());
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printf("testStyAbsolute: %d\r\n", testStyAbsolute());
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}
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void testTransfer() {
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printf("testTaxImplied: %d\r\n", testTaxImplied());
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printf("testTayImplied: %d\r\n", testTayImplied());
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printf("testTsxImplied: %d\r\n", testTsxImplied());
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printf("testTxaImplied: %d\r\n", testTxaImplied());
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printf("testTxsImplied: %d\r\n", testTxsImplied());
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printf("testTyaImplied: %d\r\n", testTyaImplied());
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}
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int main() {
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testAnd();
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testAdc();
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testAsl();
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testBranches();
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testBit();
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testBrk();
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testClear();
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testCompare();
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testDec();
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testEor();
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testInc();
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testJmp();
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testLoads();
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testLsr();
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testOra();
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testStack();
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testRotate();
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testReturn();
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testSbc();
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testSet();
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testSta();
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testStores();
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testTransfer();
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return 0;
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}
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10
6502tests/test/test.iml
Normal file
10
6502tests/test/test.iml
Normal file
@ -0,0 +1,10 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<module type="WEB_MODULE" version="4">
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<component name="NewModuleRootManager" inherit-compiler-output="true">
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<exclude-output />
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<content url="file://$MODULE_DIR$" />
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<orderEntry type="inheritedJdk" />
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<orderEntry type="sourceFolder" forTests="false" />
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</component>
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</module>
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|
503
6502tests/test/testAdc.c
Normal file
503
6502tests/test/testAdc.c
Normal file
@ -0,0 +1,503 @@
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int testAdcImmediate() {
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//no carry
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A = 0x00;
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SR&=(~SR_CARRY);
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ram[0] = 0x69;
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ram[1] = 0x01;
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instructions = 1; run();
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if(!(A == 0x01 && !SR&SR_NEG && !SR&SR_ZERO && !SR&SR_CARRY && !SR&SR_OVER)) return -1;
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//with carry
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A = 0x00;
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SR|=SR_CARRY;
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ram[0] = 0x69;
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ram[1] = 0x01;
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instructions = 1; run();
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if(!(A == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
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//negative result
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A = 0xFE;
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SR&=(~SR_CARRY);
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ram[0] = 0x69;
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ram[1] = 0xFE;
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instructions = 1; run();
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if(!(A == 0xFC && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
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||||
//overflow result
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||||
A = 0x80;
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SR&=(~SR_CARRY);
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||||
ram[0] = 0x69;
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ram[1] = 0xFF;
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||||
instructions = 1; run();
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if(!(A == 0x7F && !(SR&SR_NEG) && !(SR&SR_ZERO) && SR&SR_CARRY && SR&SR_OVER)) return -4;
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||||
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||||
//zero result
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||||
A = 0xFF; //-1
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||||
SR&=(~SR_CARRY);
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||||
ram[0] = 0x69;
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||||
ram[1] = 0x01; //+1
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||||
instructions = 1; run();
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||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -5;
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||||
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||||
//carry result
|
||||
A = 0xF0; //+70
|
||||
SR&=(~SR_CARRY);
|
||||
ram[0] = 0x69;
|
||||
ram[1] = 0xF0; //+70
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xE0 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -6;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAdcZeropage() {
|
||||
//no carry
|
||||
A = 0x00;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x65;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x01 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//with carry
|
||||
A = 0x00;
|
||||
SR |= SR_CARRY;
|
||||
ram[0] = 0x65;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//negative result
|
||||
A = 0xFE;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x65;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0xFE;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFC && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
//overflow result
|
||||
A = 0x80;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x65;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x7F && !(SR&SR_NEG) && !(SR&SR_ZERO) && SR&SR_CARRY && SR&SR_OVER)) return -4;
|
||||
|
||||
//zero result
|
||||
A = 0xFF; //-1
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x65;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x01; //+1
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -5;
|
||||
|
||||
//carry result
|
||||
A = 0xF0; //+70
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x65;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0xF0; //+70
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xE0 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -6;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAdcZeropageX() {
|
||||
X = 0x01; Y=0x00;
|
||||
|
||||
//no carry
|
||||
A = 0x00;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x75;
|
||||
ram[1] = 0x02;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x01 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//with carry
|
||||
A = 0x00;
|
||||
SR |= SR_CARRY;
|
||||
ram[0] = 0x75;
|
||||
ram[1] = 0x02;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//negative result
|
||||
A = 0xFE;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x75;
|
||||
ram[1] = 0x02;
|
||||
ram[3] = 0xFE;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFC && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
//overflow result
|
||||
A = 0x80;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x75;
|
||||
ram[1] = 0x02;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x7F && !(SR&SR_NEG) && !(SR&SR_ZERO) && SR&SR_CARRY && SR&SR_OVER)) return -4;
|
||||
|
||||
//zero result
|
||||
A = 0xFF; //-1
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x75;
|
||||
ram[1] = 0x02;
|
||||
ram[3] = 0x01; //+1
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -5;
|
||||
|
||||
//carry result
|
||||
A = 0xF0; //+70
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x75;
|
||||
ram[1] = 0x02;
|
||||
ram[3] = 0xF0; //+70
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xE0 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -6;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAdcAbsolute() {
|
||||
//no carry
|
||||
A = 0x00;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x6D;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x01 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//with carry
|
||||
A = 0x00;
|
||||
SR |= SR_CARRY;
|
||||
ram[0] = 0x6D;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//negative result
|
||||
A = 0xFE;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x6D;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFE;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFC && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
//overflow result
|
||||
A = 0x80;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x6D;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x7F && !(SR&SR_NEG) && !(SR&SR_ZERO) && SR&SR_CARRY && SR&SR_OVER)) return -4;
|
||||
|
||||
//zero result
|
||||
A = 0xFF; //-1
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x6D;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01; //+1
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -5;
|
||||
|
||||
//carry result
|
||||
A = 0xF0; //+70
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x6D;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF0; //+70
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xE0 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -6;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAdcAbsoluteX() {
|
||||
X = 0x01; Y = 0x00;
|
||||
|
||||
//no carry
|
||||
A = 0x00;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x7D;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x01 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//with carry
|
||||
A = 0x00;
|
||||
SR |= SR_CARRY;
|
||||
ram[0] = 0x7D;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//negative result
|
||||
A = 0xFE;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x7D;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFE;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFC && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
//overflow result
|
||||
A = 0x80;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x7D;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x7F && !(SR&SR_NEG) && !(SR&SR_ZERO) && SR&SR_CARRY && SR&SR_OVER)) return -4;
|
||||
|
||||
//zero result
|
||||
A = 0xFF; //-1
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x7D;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01; //+1
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -5;
|
||||
|
||||
//carry result
|
||||
A = 0xF0; //+70
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x7D;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF0; //+70
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xE0 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -6;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAdcAbsoluteY() {
|
||||
Y = 0x01; X = 0x00;
|
||||
|
||||
//no carry
|
||||
A = 0x00;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x79;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x01 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//with carry
|
||||
A = 0x00;
|
||||
SR |= SR_CARRY;
|
||||
ram[0] = 0x79;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//negative result
|
||||
A = 0xFE;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x79;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFE;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFC && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
//overflow result
|
||||
A = 0x80;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x79;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x7F && !(SR&SR_NEG) && !(SR&SR_ZERO) && SR&SR_CARRY && SR&SR_OVER)) return -4;
|
||||
|
||||
//zero result
|
||||
A = 0xFF; //-1
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x79;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01; //+1
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -5;
|
||||
|
||||
//carry result
|
||||
A = 0xF0; //+70
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x79;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF0; //+70
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xE0 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -6;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAdcIndirectX() {
|
||||
X = 0x01; Y = 0x00;
|
||||
|
||||
//no carry
|
||||
A = 0x00;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x61;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x02;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x01 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//with carry
|
||||
A = 0x00;
|
||||
SR |= SR_CARRY;
|
||||
ram[0] = 0x61;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x02;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//negative result
|
||||
A = 0xFE;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x61;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x02;
|
||||
ram[3] = 0xFE;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFC && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
//overflow result
|
||||
A = 0x80;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x61;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x02;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x7F && !(SR&SR_NEG) && !(SR&SR_ZERO) && SR&SR_CARRY && SR&SR_OVER)) return -4;
|
||||
|
||||
//zero result
|
||||
A = 0xFF; //-1
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x61;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x02;
|
||||
ram[3] = 0x01; //+1
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -5;
|
||||
|
||||
//carry result
|
||||
A = 0xF0; //+70
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x61;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x02;
|
||||
ram[3] = 0xF0; //+70
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xE0 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -6;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAdcIndirectY() {
|
||||
Y = 0x01; X = 0x00;
|
||||
|
||||
//no carry
|
||||
A = 0x00;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x71;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x03;
|
||||
ram[3] = 0x00;
|
||||
ram[4] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x01 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//with carry
|
||||
A = 0x00;
|
||||
SR |= SR_CARRY;
|
||||
ram[0] = 0x71;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x03;
|
||||
ram[3] = 0x00;
|
||||
ram[4] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//negative result
|
||||
A = 0xFE;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x71;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x03;
|
||||
ram[3] = 0x00;
|
||||
ram[4] = 0xFE;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFC && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
//overflow result
|
||||
A = 0x80;
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x71;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x03;
|
||||
ram[3] = 0x00;
|
||||
ram[4] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x7F && !(SR&SR_NEG) && !(SR&SR_ZERO) && SR&SR_CARRY && SR&SR_OVER)) return -4;
|
||||
|
||||
//zero result
|
||||
A = 0xFF; //-1
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x71;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x03;
|
||||
ram[3] = 0x00;
|
||||
ram[4] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -5;
|
||||
|
||||
//carry result
|
||||
A = 0xF0; //+70
|
||||
SR &= (~SR_CARRY);
|
||||
ram[0] = 0x71;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x03;
|
||||
ram[3] = 0x00;
|
||||
ram[4] = 0xF0;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xE0 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -6;
|
||||
|
||||
return 0;
|
||||
}
|
174
6502tests/test/testAnd.c
Normal file
174
6502tests/test/testAnd.c
Normal file
@ -0,0 +1,174 @@
|
||||
int testAndImmediate() {
|
||||
A = 0xFF;
|
||||
|
||||
//all high
|
||||
ram[0] = 0x29;
|
||||
ram[1] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFF && SR&SR_NEG && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//all low
|
||||
ram[0] = 0x29;
|
||||
ram[1] = 0x00;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAndZeropage() {
|
||||
A = 0xFF;
|
||||
|
||||
//all high
|
||||
ram[0] = 0x25;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFF && SR&SR_NEG && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//all low
|
||||
ram[0] = 0x25;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAndZeropageX() {
|
||||
X = 0x01; Y = 0x00;
|
||||
A = 0xFF;
|
||||
|
||||
//all high
|
||||
ram[0] = 0x35;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFF && SR&SR_NEG && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//all low
|
||||
ram[0] = 0x35;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAndAbsolute() {
|
||||
A = 0xFF;
|
||||
|
||||
//all high
|
||||
ram[0] = 0x2D;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFF && SR&SR_NEG && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//all low
|
||||
ram[0] = 0x2D;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x00;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAndAbsoluteX() {
|
||||
A = 0xFF;
|
||||
X = 0x01; Y = 0x00;
|
||||
|
||||
//all high
|
||||
ram[0] = 0x3D;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFF && SR&SR_NEG && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//all low
|
||||
ram[0] = 0x3D;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x00;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAndAbsoluteY() {
|
||||
A = 0xFF;
|
||||
Y = 0x01; X = 0x00;
|
||||
|
||||
//all high
|
||||
ram[0] = 0x39;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFF && SR&SR_NEG && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//all low
|
||||
ram[0] = 0x39;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x00;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAndIndirectX() {
|
||||
A = 0xFF;
|
||||
X = 0x01; Y = 0x00;
|
||||
|
||||
//all high
|
||||
ram[0] = 0x21;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x02;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFF && SR&SR_NEG && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//all low
|
||||
ram[0] = 0x21;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x02;
|
||||
ram[3] = 0x00;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAndIndirectY() {
|
||||
A = 0xFF;
|
||||
Y = 0x01; X = 0x00;
|
||||
|
||||
//all high
|
||||
ram[0] = 0x31;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x03;
|
||||
ram[3] = 0x00;
|
||||
ram[4] = 0xFF;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0xFF && SR&SR_NEG && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//all low
|
||||
ram[0] = 0x31;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x03;
|
||||
ram[3] = 0x00;
|
||||
ram[4] = 0x00;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
131
6502tests/test/testAsl.c
Normal file
131
6502tests/test/testAsl.c
Normal file
@ -0,0 +1,131 @@
|
||||
int testAslImplied() {
|
||||
//normal
|
||||
A = 0x01;
|
||||
ram[0] = 0x0A;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//carry and zero
|
||||
A = 0x80;
|
||||
ram[0] = 0x0A;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//carry and negative
|
||||
A = 0xC0;
|
||||
ram[0] = 0x0A;
|
||||
instructions = 1; run();
|
||||
if(!(A == 0x80 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAslZeropage() {
|
||||
//normal
|
||||
ram[0] = 0x06;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(ram[2] == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//carry and zero
|
||||
ram[0] = 0x06;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x80;
|
||||
instructions = 1; run();
|
||||
if(!(ram[2] == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//carry and negative
|
||||
ram[0] = 0x06;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0xC0;
|
||||
instructions = 1; run();
|
||||
if(!(ram[2] == 0x80 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAslZeropageX() {
|
||||
X = 0x01; Y = 0x00;
|
||||
|
||||
//normal
|
||||
ram[0] = 0x16;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(ram[2] == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//carry and zero
|
||||
ram[0] = 0x16;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x80;
|
||||
instructions = 1; run();
|
||||
if(!(ram[2] == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//carry and negative
|
||||
ram[0] = 0x16;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0xC0;
|
||||
instructions = 1; run();
|
||||
if(!(ram[2] == 0x80 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAslAbsolute() {
|
||||
//normal
|
||||
ram[0] = 0x0E;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(ram[3] == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//carry and zero
|
||||
ram[0] = 0x0E;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x80;
|
||||
instructions = 1; run();
|
||||
if(!(ram[3] == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//carry and negative
|
||||
ram[0] = 0x0E;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xC0;
|
||||
instructions = 1; run();
|
||||
if(!(ram[3] == 0x80 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testAslAbsoluteX() {
|
||||
X = 0x01; Y = 0x00;
|
||||
|
||||
//normal
|
||||
ram[0] = 0x1E;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01;
|
||||
instructions = 1; run();
|
||||
if(!(ram[3] == 0x02 && !(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -1;
|
||||
|
||||
//carry and zero
|
||||
ram[0] = 0x1E;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x80;
|
||||
instructions = 1; run();
|
||||
if(!(ram[3] == 0x00 && !(SR&SR_NEG) && SR&SR_ZERO && SR&SR_CARRY && !(SR&SR_OVER))) return -2;
|
||||
|
||||
//carry and negative
|
||||
ram[0] = 0x1E;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xC0;
|
||||
instructions = 1; run();
|
||||
if(!(ram[3] == 0x80 && SR&SR_NEG && !(SR&SR_ZERO) && SR&SR_CARRY && !(SR&SR_OVER))) return -3;
|
||||
|
||||
return 0;
|
||||
}
|
23
6502tests/test/testBcc.c
Normal file
23
6502tests/test/testBcc.c
Normal file
@ -0,0 +1,23 @@
|
||||
int testBccImplied() {
|
||||
SR|=SR_CARRY;
|
||||
SR&=(~SR_DEC);
|
||||
ram[0] = 0x90;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8; //SED
|
||||
instructions = 4;
|
||||
run();
|
||||
if((SR&SR_DEC) > 0) return -1;
|
||||
|
||||
SR&=(~SR_CARRY);
|
||||
SR&=(~SR_DEC);
|
||||
ram[0] = 0x90;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8;
|
||||
instructions = 4;
|
||||
run();
|
||||
if((SR&SR_DEC) == 0) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
23
6502tests/test/testBcs.c
Normal file
23
6502tests/test/testBcs.c
Normal file
@ -0,0 +1,23 @@
|
||||
int testBcsImplied() {
|
||||
SR|=SR_CARRY;
|
||||
SR&=(~SR_DEC);
|
||||
ram[0] = 0xB0;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8; //SED
|
||||
instructions = 4;
|
||||
run();
|
||||
if((SR&SR_DEC) == 0) return -1;
|
||||
|
||||
SR&=(~SR_CARRY);
|
||||
SR&=(~SR_DEC);
|
||||
ram[0] = 0xB0;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8;
|
||||
instructions = 4;
|
||||
run();
|
||||
if((SR&SR_DEC) > 0) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
22
6502tests/test/testBeq.c
Normal file
22
6502tests/test/testBeq.c
Normal file
@ -0,0 +1,22 @@
|
||||
int testBeqImplied() {
|
||||
SR|=SR_ZERO;
|
||||
SR&=(~SR_DEC);
|
||||
ram[0] = 0xF0;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8; //SED
|
||||
instructions = 4;
|
||||
run();
|
||||
if((SR&SR_DEC) == 0) return -1;
|
||||
|
||||
SR&=(~SR_ZERO);
|
||||
SR&=(~SR_DEC);
|
||||
ram[0] = 0xF0;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8;
|
||||
instructions = 4; run();
|
||||
if(SR&SR_DEC) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
45
6502tests/test/testBit.c
Normal file
45
6502tests/test/testBit.c
Normal file
@ -0,0 +1,45 @@
|
||||
int testBitZeropage() {
|
||||
//bits set
|
||||
A = 0x00;
|
||||
ram[0] = 0x24;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0xFF;
|
||||
instructions = 2;
|
||||
run();
|
||||
if(!(SR&SR_NEG && SR&SR_ZERO && SR&SR_OVER)) return -1;
|
||||
|
||||
//bits unset
|
||||
A = 0x01;
|
||||
ram[0] = 0x24;
|
||||
ram[1] = 0x02;
|
||||
ram[2] = 0x01;
|
||||
instructions = 2;
|
||||
run();
|
||||
if(!(!(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int testBitAbsolute() {
|
||||
//bits set
|
||||
A = 0x00;
|
||||
ram[0] = 0x24;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xFF;
|
||||
instructions = 2;
|
||||
run();
|
||||
if(!(SR&SR_NEG && SR&SR_ZERO && !(SR&SR_CARRY) && SR&SR_OVER)) return -1;
|
||||
|
||||
//bits unset
|
||||
A = 0x01;
|
||||
ram[0] = 0x24;
|
||||
ram[1] = 0x03;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0x01;
|
||||
instructions = 2;
|
||||
run();
|
||||
if(!(!(SR&SR_NEG) && !(SR&SR_ZERO) && !(SR&SR_CARRY) && !(SR&SR_OVER))) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
21
6502tests/test/testBmi.c
Normal file
21
6502tests/test/testBmi.c
Normal file
@ -0,0 +1,21 @@
|
||||
int testBmiImplied() {
|
||||
SR |= SR_NEG;
|
||||
SR &= (~SR_DEC);
|
||||
ram[0] = 0x30;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8; //SED
|
||||
instructions = 4; run();
|
||||
if(!(SR&SR_DEC)) return -1;
|
||||
|
||||
SR &= (~SR_NEG);
|
||||
SR &= (~SR_DEC);
|
||||
ram[0] = 0x30;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8;
|
||||
instructions = 4; run();
|
||||
if(SR&SR_DEC) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
21
6502tests/test/testBne.c
Normal file
21
6502tests/test/testBne.c
Normal file
@ -0,0 +1,21 @@
|
||||
int testBneImplied() {
|
||||
SR &= (~SR_ZERO);
|
||||
SR &= (~SR_DEC);
|
||||
ram[0] = 0xD0;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8; //SED
|
||||
instructions = 4; run();
|
||||
if(!(SR&SR_DEC)) return -1;
|
||||
|
||||
SR |= SR_ZERO;
|
||||
SR &= (~SR_DEC);
|
||||
ram[0] = 0xD0;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8;
|
||||
instructions = 4; run();
|
||||
if(SR&SR_DEC) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
21
6502tests/test/testBpl.c
Normal file
21
6502tests/test/testBpl.c
Normal file
@ -0,0 +1,21 @@
|
||||
int testBplImplied() {
|
||||
SR |= SR_NEG;
|
||||
SR &= (~SR_DEC);
|
||||
ram[0] = 0x10;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8; //SED
|
||||
instructions = 4; run();
|
||||
if(SR&SR_DEC) return -1;
|
||||
|
||||
SR &= (~SR_NEG);
|
||||
SR &= (~SR_DEC);
|
||||
ram[0] = 0x10;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8;
|
||||
instructions = 4; run();
|
||||
if(!(SR&SR_DEC)) return -2;
|
||||
|
||||
return 0;
|
||||
}
|
8
6502tests/test/testBrk.c
Normal file
8
6502tests/test/testBrk.c
Normal file
@ -0,0 +1,8 @@
|
||||
int testBrkImplied() {
|
||||
SR &= (~SR_INT);
|
||||
SP = 0xFF;
|
||||
ram[0] = 0x00;
|
||||
instructions = 4; run();
|
||||
if(!(SR&SR_INT) || PC != (read8(0xFFFE)|((unsigned short)read8(0xFFFF)<<8)) || SP != 0xFC) return -1;
|
||||
return 0;
|
||||
}
|
21
6502tests/test/testBvc.c
Normal file
21
6502tests/test/testBvc.c
Normal file
@ -0,0 +1,21 @@
|
||||
int testBvcImplied() {
|
||||
SR |= SR_OVER;
|
||||
SR &= (~SR_DEC);
|
||||
ram[0] = 0x50;
|
||||
ram[1] = 0x01;
|
||||
ram[2] = 0x00;
|
||||
ram[3] = 0xF8; //SED
|
||||
instructions = 4; run();
|
||||
if(SR |