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226 lines
8.0 KiB
HTML
226 lines
8.0 KiB
HTML
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<HEAD><TITLE>Synthesis and Ngdbuild Report</TITLE>
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</HEAD>
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<PRE><A name="Syn"></A><B><U><big>Synthesis and Ngdbuild Report</big></U></B>
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synthesis: version Diamond (64-bit) 3.9.0.99.2
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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Thu Oct 05 12:19:47 2017
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Command Line: synthesis -f yellowstone_blink_yellowstone_blink_lattice.synproj -gui
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Synthesis options:
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The -a option is MachXO2.
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The -s option is 4.
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The -t option is TQFP100.
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The -d option is LCMXO2-1200HC.
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Using package TQFP100.
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Using performance grade 4.
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##########################################################
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### Lattice Family : MachXO2
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### Device : LCMXO2-1200HC
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### Package : TQFP100
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### Speed : 4
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##########################################################
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INFO - synthesis: User-Selected Strategy Settings
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Optimization goal = Balanced
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Top-level module name = blink.
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Target frequency = 1.000000 MHz.
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Maximum fanout = 1000.
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Timing path count = 3
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BRAM utilization = 100.000000 %
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DSP usage = true
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DSP utilization = 100.000000 %
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fsm_encoding_style = auto
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resolve_mixed_drivers = 0
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fix_gated_clocks = 1
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Mux style = Auto
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Use Carry Chain = true
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carry_chain_length = 0
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Loop Limit = 1950.
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Use IO Insertion = TRUE
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Use IO Reg = AUTO
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Resource Sharing = TRUE
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Propagate Constants = TRUE
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Remove Duplicate Registers = TRUE
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force_gsr = auto
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ROM style = auto
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RAM style = auto
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The -comp option is FALSE.
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The -syn option is FALSE.
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-p C:/Users/chamberlin/Documents/Liron (searchpath added)
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-p C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data (searchpath added)
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-p C:/Users/chamberlin/Documents/Liron/yellowstone_blink (searchpath added)
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-p C:/Users/chamberlin/Documents/Liron (searchpath added)
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Verilog design file = C:/Users/chamberlin/Documents/Liron/top.v
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NGD file = yellowstone_blink_yellowstone_blink.ngd
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-sdc option: SDC file input not used.
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-lpf option: Output file option is ON.
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Hardtimer checking is enabled (default). The -dt option is not used.
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The -r option is OFF. [ Remove LOC Properties is OFF. ]
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Technology check ok...
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Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
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Compile design.
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Compile Design Begin
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Analyzing Verilog file c:/users/chamberlin/documents/liron/top.v. VERI-1482
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Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
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Top module name (Verilog): blink
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INFO - synthesis: c:/users/chamberlin/documents/liron/top.v(1): compiling module blink. VERI-1018
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INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH. VERI-1018
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WARNING - synthesis: c:/users/chamberlin/documents/liron/top.v(18): expression size 32 truncated to fit in target size 24. VERI-1209
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
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Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
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Package Status: Final Version 1.42.
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Top-level module name = blink.
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GSR will not be inferred because no asynchronous signal was found in the netlist.
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Applying 1.000000 MHz constraint to all clocks
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WARNING - synthesis: No user .sdc file.
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Results of NGD DRC are available in blink_drc.log.
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
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All blocks are expanded and NGD expansion is successful.
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Writing NGD file yellowstone_blink_yellowstone_blink.ngd.
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################### Begin Area Report (blink)######################
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Number of register bits => 21 of 1520 (1 % )
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CCU2D => 11
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FD1S3AX => 21
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GSR => 1
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OB => 2
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OSCH => 1
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################### End Area Report ##################
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################### Begin BlackBox Report ######################
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TSALL => 1
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################### End BlackBox Report ##################
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################### Begin Clock Report ######################
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Clock Nets
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Number of Clocks: 1
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Net : clk, loads : 21
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Clock Enable Nets
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Number of Clock Enables: 0
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Top 0 highest fanout Clock Enables:
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Highest fanout non-clock nets
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Top 10 highest fanout non-clock nets:
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Net : pin_led_c_20, loads : 2
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Net : n21, loads : 1
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Net : n20, loads : 1
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Net : n19, loads : 1
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Net : n18, loads : 1
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Net : n17, loads : 1
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Net : n16, loads : 1
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Net : n15, loads : 1
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Net : n14, loads : 1
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Net : n13, loads : 1
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################### End Clock Report ##################
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<A name="lse_trs"></A><B><U><big>Timing Report Summary</big></U></B>
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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create_clock -period 1000.000000 -name | | |
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clk0 [get_nets clk] | 1.000 MHz| 181.028 MHz| 12
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--------------------------------------------------------------------------------
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All constraints were met.
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Peak Memory Usage: 49.246 MB
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--------------------------------------------------------------
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Elapsed CPU time for LSE flow : 0.406 secs
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--------------------------------------------------------------
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