commit 31488767c7ec94b6d9338dc95fc917e2e37d70c5 Author: steve-chamberlin Date: Wed Jan 30 12:55:46 2019 -0800 initial commit diff --git a/.run_manager.ini b/.run_manager.ini new file mode 100644 index 0000000..b1c6327 --- /dev/null +++ b/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[yellowstone_blink%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/.setting.ini b/.setting.ini new file mode 100644 index 0000000..85836a3 --- /dev/null +++ b/.setting.ini @@ -0,0 +1,3 @@ +[General] +AutoAssign=false +Export.auto_tasks=Bitgen, Jedecgen diff --git a/.spread_sheet.ini b/.spread_sheet.ini new file mode 100644 index 0000000..6c511f4 --- /dev/null +++ b/.spread_sheet.ini @@ -0,0 +1,3 @@ +[General] +COLUMN_POS_INFO_NAME_-1_0=Prioritize +COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/.spreadsheet_view.ini b/.spreadsheet_view.ini new file mode 100644 index 0000000..773925b --- /dev/null +++ b/.spreadsheet_view.ini @@ -0,0 +1,76 @@ +[General] +pin_sort_type=0 +pin_sort_ascending=true +sig_sort_type=0 +sig_sort_ascending=true +active_Sheet=Port Assignments + +[Port%20Assignments] +Name="140,0" +Group%20By="84,1" +Pin="50,2" +BANK="62,3" +BANK_VCC="90,4" +VREF="60,5" +IO_TYPE="80,6" +PULLMODE="92,7" +DRIVE="67,8" +SLEWRATE="92,9" +CLAMP="71,10" +OPENDRAIN="97,11" +DIFFRESISTOR="114,12" +DIFFDRIVE="92,13" +HYSTERESIS="101,14" +Outload%20%28pF%29="103,15" +MaxSkew="87,16" +Clock%20Load%20Only="121,17" +SwitchingID="100,18" +Ground%20plane%20PCB%20noise%20%28mV%29="196,19" +Power%20plane%20PCB%20noise%20%28mV%29="190,20" +SSO%20Allowance%28%25%29="138,21" +sort_columns="Name,Ascending" + +[Pin%20Assignments] +Pin="90,0" +Pad%20Name="89,1" +Dual%20Function="158,2" +Polarity="77,3" +BANK="0,4" +BANK_VCC="90,5" +IO_TYPE="80,6" +Signal%20Name="102,7" +Signal%20Type="98,8" +sort_columns="Pin,Ascending" + +[Clock%20Resource] +Clock%20Type="100,ELLIPSIS" +Clock%20Name="100,ELLIPSIS" +Selection="100,ELLIPSIS" + +[Global%20Preferences] +Preference%20Name="230,ELLIPSIS" +Preference%20Value="236,ELLIPSIS" + +[Cell%20Mapping] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Din\Dout="100,ELLIPSIS" +PIO%20Register="100,ELLIPSIS" + +[Route%20Priority] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Prioritize="100,ELLIPSIS" + +[Timing%20Preferences] +Preference%20Name="138,ELLIPSIS" +Preference%20Value="104,ELLIPSIS" +Preference%20Unit="813,ELLIPSIS" + +[Group] +Group%20Type\Name="134,ELLIPSIS" +Value="921,ELLIPSIS" + +[Misc%20Preferences] +Preference%20Name="117,ELLIPSIS" +Preference%20Value="938,ELLIPSIS" diff --git a/LICENSE.TXT b/LICENSE.TXT new file mode 100644 index 0000000..331f23b --- /dev/null +++ b/LICENSE.TXT @@ -0,0 +1,20 @@ +The FPGA disk controller card design is provided by Steve Chamberlin, Big Mess o' Wires, under the Creative Commons Attribution - ShareAlike 4.0 license. + +see https://creativecommons.org/licenses/by-sa/4.0/ + +Please note that the marks "Yellowstone", "BMOW", and "Big Mess o' Wires" are not covered by this license, and are reserved for exclusive use by Steve Chamberlin. You are not permitted to use any of these words in the name of any clone or derivative products based on this design. You will need to choose a new name for any clone or derivative product you may create. + +------- + +You are free to: + +Share — copy and redistribute the material in any medium or format +Adapt — remix, transform, and build upon the material +for any purpose, even commercially. + +Under the following terms: + +Attribution — You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use. + +ShareAlike — If you remix, transform, or build upon the material, you must distribute your contributions under the same license as the original. + diff --git a/LIRONALL.bin b/LIRONALL.bin new file mode 100644 index 0000000..a7e7b62 Binary files /dev/null and b/LIRONALL.bin differ diff --git a/LIRONHI.bin b/LIRONHI.bin new file mode 100644 index 0000000..35742e5 Binary files /dev/null and b/LIRONHI.bin differ diff --git a/LIRONLO1.bin b/LIRONLO1.bin new file mode 100644 index 0000000..9121711 Binary files /dev/null and b/LIRONLO1.bin differ diff --git a/LIRONLO4.bin b/LIRONLO4.bin new file mode 100644 index 0000000..b8773c9 Binary files /dev/null and b/LIRONLO4.bin differ diff --git a/LIRONLO5.bin b/LIRONLO5.bin new file mode 100644 index 0000000..1753f84 Binary files /dev/null and b/LIRONLO5.bin differ diff --git a/LIRONLO7.bin b/LIRONLO7.bin new file mode 100644 index 0000000..4a3498f Binary files /dev/null and b/LIRONLO7.bin differ diff --git a/README.TXT b/README.TXT new file mode 100644 index 0000000..7306773 --- /dev/null +++ b/README.TXT @@ -0,0 +1,105 @@ +Compiled by Steve Chamberlin +steve@bigmessowires.com +January 28, 2019 + +//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\ + +I'm sharing the FPGA disk controller design because I don't currently have the time or resources to pursue its further development on my own, but want the Apple II collector community to get the benefit of the progress I've made to date. + +See LICENSE.TXT for details on the license terms for this design. + +The marks "Yellowstone", "BMOW", and "Big Mess o' Wires" are not covered by this license, and are reserved for my exclusive use. You are not permitted to use any of these words in the name of any clone or derivative products based on this design. You will need to choose a new name for your clone or derivative product. + +//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\ + +GROUND RULES +------------ + +Please don't send me detailed questions and requests for help with this design, or expect me to be your engineering consultant. I'm releasing the design to the community because I don't have time to pursue it myself. That means I can't work on it for you, either. The design is released as-is, with no promise of technical support. I may be able to answer general questions, but the rest is up to you. + + +WHAT IS THIS? +------------- + +Yellowstone is the code name for an Apple II disk controller card that's based on an FPGA, rather than using discrete logic chips and ROM chips. By reprogramming the FPGA, the card can be made to emulate various other disk controller cards made by Apple in the 1980s and 1990s. The work so far has focused on emulating an Apple Liron disk controller card, but it would also be easy to emulate a Disk II controller card. It's theoretically also possible to emulate a Disk 3.5 controller card, though this possibility has not been explored in detail. + + +WHAT'S LIRON? +------------- + +The Liron disk controller was introduced by Apple in 1985. More formally known as the Apple II UniDisk 3.5 Controller, it's designed to work with a new generation of "smart" disk drives more sophisticated than the venerable Disk II 5.25 inch floppy drive. The smart disk port on the Liron is appropriately named the Smartport, and it can communicate with block-based storage devices such as the Unidisk 3.5 (an early 800K drive) and Smartport-based Apple II hard drives. + +Why care about the Liron? The Apple IIc and Apple IIgs have integrated disk ports with built-in Smartport functionality, but for the earlier Apple II+ and IIe, the Liron is the only way to get a Smartport. For owners of the BMOW Floppy Emu disk emulator, having a Liron card makes it possible to use the Floppy Emu as an external hard drive for the II+ and IIe. Unfortunately finding a Liron is difficult, and although they occasionally turn up on eBay, they’re quite expensive. That makes cloning the Liron a desirable goal. + + +HOW IT WORKS +------------ + +The FPGA disk controller card is little more than an FPGA, a voltage regulator, and a set of level-shifting bus transceivers. The FPGA replaces all of the 7400-series discrete logic chips typically found on a disk controller card. Verilog (hardware description language) replacements for all of the 7400-series parts and other logic were written and programmed into the FPGA. This also includes a full Verilog implmentation of the Apple IWM chip. + +The FPGA also replaces the ROM chip containing the boot code for the card. The Apple II executes this code during power-up, and the code knows how to find and load sector 0 from the attached disk drive. The code was obtained from a ROM dump from a real Liron card. + +The prototype card also includes a footprint for an 8-pin SPI flash memory chip. It is not used by the current FPGA code, and the chip can be omitted. The idea was that a small number of disk images could be stored in SPI flash memory, so the card could function both as a disk controller and as a disk emulator, but this was never implemented. + +The card has a standard 10 x 2 pin disk connector on board. It can be connected directly to a BMOW Floppy Emu disk emulator, using a standard ribbon cable. But for a full Liron clone and connecton to a Unidisk 3.5, a DB-19 female connector is required. A design for a DB-19F adapter PCB is included here, and the adapter can be connected to the disk controller card with a short ribbon cable. The DB-19F is still available from surplus electronics suppliers in small quantities. + + +PROJECT STATUS +-------------- + +See https://www.bigmessowires.com/category/yellowstone/ for a complete history of work involving the FPGA disk controller. + +The FPGA disk controller card was designed by Steve Chamberlin at Big Mess o' Wires during the summer of 2017, but the first prototype card wasn't built and tested until January 2018. The version 1.0 card had errors with the wiring for the output enable signal on one of the bus transceiver chips, and it required a few hand-soldered path wires to fix. After further development, the prototype card was demonstrated to work as a Liron clone, in both an Apple IIe enhanced computer and an Apple IIgs. It worked for controlling a real Unidisk 3.5 drive, as well as a BMOW Floppy Emu disk emulator configured for Smartport emulation mode. + +Later testing discovered that the FPGA disk controller card worked reliably when it was the only card installed, but other cards were also present, it sometimes malfunctioned. The more other cards present, the worse the rate of errors became. This was diagnosed as a likely termination or contention problem on the Apple II data bus, and various fixes were tried unsuccessfully. After March 2018, I lost interest in researching the problem further, and no more work has occurred since then. + +The design provided here is version 1.1, and it fixes the output enable problem from version 1.0. + + +WHERE TO START +-------------- + +Open the FPGA disk controller design (Liron clone) in EAGLE. Export Gerber files and send them to your favorite PCB fabricator. If desired, do the same for the DB19F adapter design. + +Purchase the chips and other parts listed in the BOM. + +Assemble the card. I did it by hand, you can do it too. A syringe of solder paste and a hot plate or toaster oven works nicely. + +Get a Lattice JTAG programmer or appropriate clone. Some clones don't handle 3.3V logic correctly. Maybe spend the extra money for a genuine Lattice programmer. + +Install the Lattice Diamond software. + +Apply 5V power to the card at jumper J4. Do not insert the card into your Apple II yet. + +Program the FPGA with the bitstream for the Liron clone design - liron_fpgatop.jed + +Insert the card in your Apple II. Remove any other cards that are present. + +Connect a Smartport-compatible disk drive, such as a BMOW Floppy Emu disk emulator that's configured for Smartport emulation mode, or an Apple Unidisk 3.5 drive. + +Turn on the Apple II. It should boot from the attached drive. + + +NEXT STEPS +---------- + +The bus termination or bus contention problem must be solved, in order to get a robust card that works smoothly when other cards are also present. See the blog posts from February-March 2018 for more details about what was already tried. A solution will require a person who's experienced at electronic design, and has appropriate test equipment such as an oscilloscope and logic analyzer. + +The current design uses a Lattice MachXO2 1200HC FPGA, and a Lattice JTAG programmer (or compatible) is required for programming it. The XO2-1200HC has more logic resources than are actually necessary for the Liron clone design. The cheaper XO2-640 or XO2-256 could be substituted instead. They are mostly or entirely pin-compatible with the XO2-1200HC. + +Programming the FPGA with a JTAG programmer is fine for development use, but end users are unlikely to have one. If reprogramming by the end user is desired (say to switch between Liron and Disk 3.5 emulation behaviors), a different method of FPGA programming will need to be developed. + + +FILES +----- + +eagle/ - directory containing EAGLE designs for the FPGA disk controller card, the DB19F adapter, and a reverse-engineered schematic of the original Liron card. +eagle/FPGA disk controller/bom.xslx - bill of materials needed to assemble the card. +lattice/ - directory containing the Verilog and other code for the Liron clone design for the card. +yellowstone_blink/ - directory containing the Verilog and other code for a simple LED blink example. This can be used to verify that the FPGA is working. +yellowstone_blink_tcr.dir/ - directory containing some junk generated by the Lattice Diamond software. +disasm.asm, liron.asm - two different disassemblies of the original Liron card's boot ROM +LIRONALL.BIN - binary file with the original Liron card's boot ROM +rom-full-4k.mem - the Liron boot ROM in a format compatible with the Lattice Diamond software. +README.TXT - this file +LICENSE.TXT - details about the license for the design diff --git a/control.txt b/control.txt new file mode 100644 index 0000000..247d65a --- /dev/null +++ b/control.txt @@ -0,0 +1,3 @@ +load $C000 LIRONALL.bin +entry $C700 +save disasm.asm diff --git a/disasm.asm b/disasm.asm new file mode 100644 index 0000000..aa96208 --- /dev/null +++ b/disasm.asm @@ -0,0 +1,1749 @@ +L0000 = $0000 +L0001 = $0001 +L0002 = $0002 +L0003 = $0003 +L0024 = $0024 +L0025 = $0025 +L0040 = $0040 +L0041 = $0041 +L0042 = $0042 +L0043 = $0043 +L0044 = $0044 +L0045 = $0045 +L0046 = $0046 +L0047 = $0047 +L0048 = $0048 +L0049 = $0049 +L004B = $004B +L004C = $004C +L004D = $004D +L004E = $004E +L004F = $004F +L0050 = $0050 +L0051 = $0051 +L0052 = $0052 +L0053 = $0053 +L0054 = $0054 +L0055 = $0055 +L0056 = $0056 +L0057 = $0057 +L0058 = $0058 +L0059 = $0059 +L005A = $005A +L005B = $005B +L0083 = $0083 +L00A0 = $00A0 +L00B9 = $00B9 +L00C2 = $00C2 +L00C4 = $00C4 +L00C5 = $00C5 +L00C9 = $00C9 +L00F0 = $00F0 +L00F2 = $00F2 +L0478 = $0478 +L04F8 = $04F8 +L0578 = $0578 +L05F8 = $05F8 +L0678 = $0678 +L06F8 = $06F8 +L0778 = $0778 +L07F8 = $07F8 +L0800 = $0800 +L0801 = $0801 +LA0C5 = $A0C5 +LA0CF = $A0CF +LAEE3 = $AEE3 +LD4CF = $D4CF +LE000 = $E000 +LF5F0 = $F5F0 +LFABA = $FABA +LFC22 = $FC22 +LFDED = $FDED +LFE89 = $FE89 +LFE93 = $FE93 + + .org $C700 + LDX #$20 + LDX #$00 + LDX #$03 + CMP #$00 + BCS LC714 + + SEC + BCS LC70E + + CLC +.LC70E + LDX #$07 + ROR L0478,X + CLC +.LC714 + LDX #$C7 + STX L07F8 + LDX #$07 + LDA LCFFF + JMP LCBE1 + + LDY #$00 + LDA L004B + PHA + BNE LC72B + + JMP LC7B8 + +.LC72B + LDA LC0FC + BPL LC72B + + STA L0059 + LSR A + LSR A + LSR A + AND #$0F + TAX + LDA L0059 + AND #$07 + STA L0059 +.LC73E + LDA LC0FC + BPL LC73E + + EOR LCA27,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY + BNE LC751 + + INC L0057 +.LC751 + LDA LC0FC + BPL LC751 + + EOR LCA37,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY +.LC760 + LDA LC0FC + BPL LC760 + + EOR LCA47,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY +.LC76F + LDA LC0FC + BPL LC76F + + EOR LCA57,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY + BNE LC782 + + INC L0057 +.LC782 + LDX L0059 +.LC784 + LDA LC0FC + BPL LC784 + + EOR LCA37,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY +.LC793 + LDA LC0FC + BPL LC793 + + EOR LCA47,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY +.LC7A2 + LDA LC0FC + BPL LC7A2 + + EOR LCA57,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY + DEC L004B + BEQ LC7B8 + + JMP LC72B + +.LC7B8 + LDA LC0FC + BPL LC7B8 + + STA L0059 + PLA + STA L004B +.LC7C2 + LDA LC0FC + BPL LC7C2 + + SEC + ROL A + AND L0059 + EOR L0040 +.LC7CD + LDY LC0FC + BPL LC7CD + + CPY #$C8 + BNE LC7F2 + + LDX L004C + BEQ LC7E2 + + LDY #$00 +.LC7DC + EOR (L0054),Y + INY + DEX + BNE LC7DC + +.LC7E2 + TAX + BNE LC7F6 + + LDA LC0FD +.LC7E8 + LDA LC0FE + BMI LC7E8 + + LDA LC0F0 + CLC + RTS + +.LC7F2 + LDA #$20 + BNE LC7F8 + +.LC7F6 + LDA #$10 +.LC7F8 + SEC + RTS + +; PC=C7FA INVALID opcode FF + BRK + BRK + BRK +; PC=C7FE INVALID opcode BF + ASL A +.LC800 + JSR LCAEE + + JSR LCA05 + + LDY #$07 + JSR LCBA9 + + LDA LC08B,X + LDA LC089,X + LDY #$32 +.LC813 + LDA LC08E,X + BMI LC81F + + DEY + BNE LC813 + + SEC + JMP LC949 + +.LC81F + LDA LC081,X + LDY #$05 + LDA #$FF + STA LC08F,X +.LC829 + LDA LC950,Y +.LC82C + ASL LC08C,X + BCC LC82C + + STA LC08D,X + DEY + BPL LC829 + + LDA L005A + ORA #$80 + JSR LC9D8 + + JSR LC9D6 + + LDA L005B + JSR LC9D8 + + JSR LC9D6 + + JSR LC9D6 + + LDA L004C + ORA #$80 + JSR LC9D8 + + LDA L004B + ORA #$80 + JSR LC9D8 + + LDA L004C + BEQ LC873 + + LDY #$FF + LDA L0059 +.LC862 + ASL LC08C,X + BCC LC862 + + STA LC08D,X + INY + LDA (L0054),Y + ORA #$80 + CPY L004C + BCC LC862 + +.LC873 + LDA L004B + BNE LC87A + + JMP LC913 + +.LC87A + NOP + LDY #$00 +.LC87D + LDA L0041 + STA LC08D,X + LDA L004D + ORA #$80 + STY L0059 +.LC888 + LDY LC08C,X + BPL LC888 + + STA LC08D,X + LDY L0059 + LDA (L0056),Y + STA L004D + ASL A + ROL L0041 + INY + BNE LC8A1 + + INC L0057 + JMP LC8A3 + +.LC8A1 + PHA + PLA +.LC8A3 + LDA #$02 + ORA L0041 + STA L0041 + LDA L004E + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L004E + ASL A + ROL L0041 + INY + LDA L004F + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L004F + ASL A + ROL L0041 + INY + LDA L0050 + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L0050 + ASL A + ROL L0041 + INY + BNE LC8DD + + INC L0057 + JMP LC8DF + +.LC8DD + PHA + PLA +.LC8DF + LDA L0051 + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L0051 + ASL A + ROL L0041 + INY + LDA L0052 + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L0052 + ASL A + ROL L0041 + INY + LDA L0053 + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L0053 + ASL A + ROL L0041 + INY + DEC L004B + BEQ LC913 + + JMP LC87D + +.LC913 + LDA L0040 + ORA #$AA +.LC917 + LDY LC08C,X + BPL LC917 + + STA LC08D,X + LDA L0040 + LSR A + ORA #$AA + JSR LC9D8 + + LDA #$C8 + JSR LC9D8 + +.LC92C + LDA LC08C,X + AND #$40 + BNE LC92C + + STA LC08D,X + LDY #$0A +.LC938 + DEY + BNE LC943 + + LDA #$01 +.LC93D + JSR LCA1F + + SEC + BCS LC949 + +.LC943 + LDA LC08E,X + BMI LC938 + + CLC +.LC949 + LDA LC080,X + LDA LC08C,X + RTS + +.LC950 +; PC=C950 INVALID opcode C3 +; PC=C951 INVALID opcode FF +; PC=C952 INVALID opcode FC +; PC=C953 INVALID opcode F3 +; PC=C954 INVALID opcode CF +; PC=C955 INVALID opcode 3F + JSR LC95B + + NOP + NOP +.LC95B + NOP + RTS + +.LC95D + JMP LC93D + +.LC960 + LDA #$00 + STA L0040 + LDA L0054 + STA L0056 + LDA L0055 + STA L0057 + LDA #$21 + STA L0052 + LDA L0058 + CLC + ADC #$C0 + STA L0053 + JSR LCA05 + + LDA LC08D,X +.LC97D + LDA LC08E,X + BPL LC97D + + LDA LC081,X + LDY #$1E +.LC987 + LDA LC08C,X + BPL LC987 + + DEY + BMI LC95D + + CMP #$C3 + BNE LC987 + + LDY #$06 +.LC995 + LDA LC08C,X + BPL LC995 + + AND #$7F + STA L004B,Y + EOR #$80 + EOR L0040 + STA L0040 + DEY + BPL LC995 + + LDA L004C + BEQ LC9D3 + + CLC + EOR L0054 + STA L0056 + LDA L0055 + ADC #$00 + STA L0057 + LDY #$00 +.LC9B9 + LDA LC08C,X + BPL LC9B9 + + ASL A + STA L0041 +.LC9C1 + LDA LC08C,X + BPL LC9C1 + + ASL L0041 + BCS LC9CC + + EOR #$80 +.LC9CC + STA (L0054),Y + INY + CPY L004C + BCC LC9C1 + +.LC9D3 + JMP (L0052) + +.LC9D6 + LDA #$80 +.LC9D8 + LDY LC08C,X + BPL LC9D8 + + STA LC08D,X + EOR L0040 + STA L0040 + RTS + +.LC9E5 + JSR LCA0F + + LDA LC081,X + LDA LC085,X + LDY #$50 + JSR LC9F8 + + JSR LCA0F + + LDY #$0A +.LC9F8 + JSR LC9FF + + DEY + BNE LC9F8 + + RTS + +.LC9FF + LDX #$C8 +.LCA01 + DEX + BNE LCA01 + + RTS + +.LCA05 + JSR LCA1F + + LDA LC083,X + LDA LC087,X + RTS + +.LCA0F + JSR LCA1F + + LDA LC080,X + LDA LC082,X + LDA LC084,X + LDA LC086,X + RTS + +.LCA1F + LDA L0058 + ASL A + ASL A + ASL A + ASL A + TAX + RTS + +.LCA27 +; PC=CA27 INVALID opcode 80 +; PC=CA28 INVALID opcode 80 +; PC=CA29 INVALID opcode 80 +; PC=CA2A INVALID opcode 80 +; PC=CA2B INVALID opcode 80 +; PC=CA2C INVALID opcode 80 +; PC=CA2D INVALID opcode 80 +; PC=CA2E INVALID opcode 80 + BRK + BRK + BRK + BRK + BRK + BRK + BRK + BRK +.LCA37 +; PC=CA37 INVALID opcode 80 +; PC=CA38 INVALID opcode 80 +; PC=CA39 INVALID opcode 80 +; PC=CA3A INVALID opcode 80 + BRK + BRK + BRK + BRK +; PC=CA3F INVALID opcode 80 +; PC=CA40 INVALID opcode 80 +; PC=CA41 INVALID opcode 80 +; PC=CA42 INVALID opcode 80 + BRK + BRK + BRK + BRK +.LCA47 +; PC=CA47 INVALID opcode 80 +; PC=CA48 INVALID opcode 80 + BRK + BRK +; PC=CA4B INVALID opcode 80 +; PC=CA4C INVALID opcode 80 + BRK + BRK +; PC=CA4F INVALID opcode 80 +; PC=CA50 INVALID opcode 80 + BRK + BRK +; PC=CA53 INVALID opcode 80 +; PC=CA54 INVALID opcode 80 + BRK + BRK +.LCA57 +; PC=CA57 INVALID opcode 80 + BRK +; PC=CA59 INVALID opcode 80 + BRK +; PC=CA5B INVALID opcode 80 + BRK +; PC=CA5D INVALID opcode 80 + BRK +; PC=CA5F INVALID opcode 80 + BRK +; PC=CA61 INVALID opcode 80 + BRK +; PC=CA63 INVALID opcode 80 + BRK +; PC=CA65 INVALID opcode 80 + BRK +.LCA67 + LDA #$05 + LDY #$00 + JSR LCA8A + + BCC LCA75 + + LDA #$80 + JSR LCDED + +.LCA75 + RTS + +.LCA76 + JSR LCA8A + + BCC LCA75 + + LDA #$80 + JSR LCDED + + LDA L06F8 + STA L004D + LDA L0778 + STA L004E +.LCA8A + LDA #$B8 + LDY #$0B + LDX L0058 + STA L04F8,X + TYA + STA L0578,X +.LCA97 + LDA L004D + STA L06F8 + LDA L004E + STA L0778 + JSR LC800 + + LDA L06F8 + STA L004D + LDA L0778 + STA L004E + BCC LCABC + + LDX L0058 + DEC L04F8,X + BNE LCA97 + + DEC L0578,X + BPL LCA97 + +.LCABC + RTS + +.LCABD + LDY L0058 + LDA #$05 + STA L04F8,Y +.LCAC4 + JSR LC960 + + BCC LCAD8 + + LDY #$01 + JSR LC9F8 + + JSR LC93D + + LDX L0058 + DEC L04F8,X + BNE LCAC4 + +.LCAD8 + RTS + +.LCAD9 + BRK + BIT L0049 +.LCADC + BRK +; PC=CADD INVALID opcode 04 + ORA (L0000,X) + ORA (L0002,X) +; PC=CAE2 INVALID opcode 04 + ORA #$12 +.LCAE5 + BRK + ORA (L0002,X) +; PC=CAE8 INVALID opcode 04 + ORA (L0002,X) +.LCAEB + BRK +; PC=CAEC INVALID opcode 7F +; PC=CAED INVALID opcode FF +.LCAEE + LDX L004E + BEQ LCB05 + + LDA L0055 + STA L0057 + LDA #$80 + CPX #$01 + BEQ LCB00 + + INC L0057 + LDA #$00 +.LCB00 + CLC + EOR L0054 + STA L0056 +.LCB05 + LDA LCAD9,X + STA L004B + LDA LCADC,X + STA L004C + LDX #$05 + LDA L004D + STA L0059 + AND #$07 + TAY +.LCB18 + ASL L0059 + BCC LCB31 + + LDA LCAE5,X +.LCB1F + CLC + EOR L004C + CMP #$07 + BCC LCB28 + + SBC #$07 +.LCB28 + STA L004C + LDA LCADF,X + EOR L004B + STA L004B +.LCB31 + DEX + BMI LCB3A + + BNE LCB18 + + TYA + JMP LCB1F + +.LCB3A + LDA L0055 + PHA + LDA #$00 + LDX L004E + BEQ LCB59 + + LDY LCAEB,X +.LCB46 + EOR (L0054),Y + EOR (L0056),Y + DEY + BNE LCB46 + + EOR (L0054),Y + EOR (L0056),Y + CPX #$01 + BEQ LCB57 + + INC L0055 +.LCB57 + INC L0055 +.LCB59 + LDY L004D + BEQ LCB66 + + EOR (L0054),Y +.LCB5F + EOR (L0054),Y + DEY + BNE LCB5F + + EOR (L0054),Y +.LCB66 + STA L0040 + PLA + STA L0055 + LDY L004C + DEY + LDA #$00 + STA L0059 +.LCB72 + LDA (L0054),Y + ASL A + ROR L0059 + DEY + BPL LCB72 + + SEC + ROR L0059 + LDA L004C + CLC + EOR L0054 + STA L0056 + LDA L0055 + ADC #$00 + STA L0057 + LDY #$06 +.LCB8C + SEC + LDA (L0056),Y + STA L004D,Y + BMI LCB95 + + CLC +.LCB95 + ROR L0041 + DEY + BPL LCB8C + + SEC + ROR L0041 + LDA L0056 + CLC + ADC #$07 + STA L0056 + BCC LCBA8 + + INC L0057 +.LCBA8 + RTS + +.LCBA9 + LDA LC088,X + LDA LC08D,X + JMP LCBB6 + +.LCBB2 + TYA + STA LC08F,X +.LCBB6 + TYA + EOR LC08E,X + AND #$1F + BNE LCBB2 + + RTS + +.LCBBF + LDA L004B + TAY + LDX #$00 + STX L004B + LDX #$03 +.LCBC8 + ASL A + ROL L004B + DEX + BNE LCBC8 + + CLC + EOR L004C + BCC LCBD5 + + INC L004B +.LCBD5 + STY L004C + SEC + SBC L004C + BCS LCBDE + + DEC L004B +.LCBDE + LDY L004B + RTS + +.LCBE1 + BCC LCBE6 + + JMP LCE59 + +.LCBE6 + CLD + TXA + TAY + LDA L0478,Y + BMI LCBFF + + PLA + STA L05F8,Y + CLC + ADC #$03 + TAX + PLA + STA L0678,Y + ADC #$00 + PHA + TXA + PHA +.LCBFF + PHP + SEI + LDX #$1B +.LCC03 + LDA L0040,X + PHA + DEX + BPL LCC03 + + STY L0058 + LDA L06F8,Y + CMP #$A5 + BNE LCC19 + + EOR #$FF + EOR L0778,Y + BEQ LCC1E + +.LCC19 + LDA #$00 + JSR LCDED + +.LCC1E + LDA L0043 + ROL A + PHP + ROL A + ROL A + PLP + ROL A + AND #$03 + EOR #$02 + CPY #$04 + BCS LCC30 + + EOR #$02 +.LCC30 + TAX + INX + STX L0043 + LDA L0478,Y + BPL LCC3C + + JMP LCCCF + +.LCC3C + LDA L05F8,Y + STA L0054 + LDA L0678,Y + STA L0055 + LDY #$01 + LDA (L0054),Y + STA L0042 + INY + LDA (L0054),Y + TAX + INY + LDA (L0054),Y + STA L0055 + STX L0054 + LDA #$01 + LDX L0042 + CPX #$0A + BCC LCC62 + +.LCC5F + JMP LCD9F + +.LCC62 + LDY #$00 + LDA (L0054),Y + STA L005A + LDY #$08 +.LCC6A + LDA (L0054),Y + STA L0042,Y + DEY + BNE LCC6A + + LDA L0043 + BNE LCCCF + + LDX L0042 + LDA LCDE3,X + AND #$7F + TAY + LDA #$04 + CPY L005A + BNE LCC5F + + CPX #$05 + BNE LCC92 + + LDA #$00 + JSR LCDED + +.LCC8D + LDA #$00 + JMP LCDC1 + +.LCC92 + TXA + BNE LCCB8 + + LDA #$21 + LDX L0046 + BNE LCC5F + + TXA + LDX L0058 + LDY #$07 +.LCCA0 + STA (L0044),Y + DEY + BNE LCCA0 + + LDA L07F8,X + STA (L0044),Y + INY + LDA #$00 + STA (L0044),Y + LDA #$08 + DEY + JSR LCE4F + + JMP LCC8D + +.LCCB8 + CMP #$04 + BNE LCCC7 + + LDX L0046 + BEQ LCCCB + + DEX + BEQ LCCCB + + LDA #$21 +.LCCC5 + BNE LCC5F + +.LCCC7 + LDA #$11 + BNE LCC5F + +.LCCCB + LDA #$1F + BNE LCC5F + +.LCCCF + LDA #$28 + LDY L0058 + LDX L07F8,Y + CPX L0043 + BCC LCCC5 + + LDA #$09 + STA L004D + LDA #$00 + STA L004E + STA L0055 + LDA #$42 + STA L0054 + LDX L0058 + LDA L0478,X + BPL LCD02 + + LDX L0042 + LDA LCDE3,X + AND #$7F + STA L005A + LDA #$00 + STA L0048 + LDA L0042 + BNE LCD02 + + STA L0046 +.LCD02 + LDA L005A + LDX L0043 + STX L005A + STA L0043 + LDA #$80 + STA L005B + JSR LCA0F + + JSR LCA76 + + BCS LCD5C + + LDA L0044 + STA L0054 + LDA L0045 + STA L0055 + LDX L0042 + LDA LCDE3,X + BPL LCD60 + + CPX #$04 + BNE LCD41 + + LDY #$01 + LDA (L0054),Y + TAX + DEY + LDA (L0054),Y + PHA + CLC + LDA #$02 + EOR L0054 + STA L0054 + PLA + BCC LCD4F + + INC L0055 + JMP LCD4F + +.LCD41 + CPX #$02 + BNE LCD4B + + LDA #$00 + LDX #$02 + BNE LCD4F + +.LCD4B + LDX L0047 + LDA L0046 +.LCD4F + STX L004E + STA L004D + LDA #$82 + STA L005B + JSR LCA67 + + BCC LCD60 + +.LCD5C + LDA #$06 + BNE LCD9F + +.LCD60 + LDY L0058 + LDA L0478,Y + BPL LCD73 + + LDA L0042 + BNE LCD73 + + LDA #$45 + LDX #$00 + STA L0054 + STX L0055 +.LCD73 + JSR LCABD + + BCS LCD5C + + JSR LCBBF + + JSR LCE4F + + LDA L0042 + BNE LCD9D + + LDX L0058 + LDA L0478,X + BPL LCD9D + + LDA L0046 + STA L05F8,X + LDA L0047 + STA L0678,X + LDA L0045 + AND #$10 + BNE LCD9D + + LDA #$2F + BNE LCD9F + +.LCD9D + LDA L004D +.LCD9F + LDY L0058 + STA L04F8,Y + TAX + BEQ LCDC1 + + LDX L0478,Y + BPL LCDC1 + + LDX #$00 + CMP #$40 + BCS LCDC0 + + LDX #$27 + CMP #$2B + BEQ LCDC1 + + CMP #$28 + BEQ LCDC1 + + CMP #$2F + BEQ LCDC1 + +.LCDC0 + TXA +.LCDC1 + LDY L0058 + STA L0578,Y + LDX #$00 +.LCDC8 + PLA + STA L0040,X + INX + CPX #$1C + BCC LCDC8 + + PLP + LDA L05F8,Y + TAX + LDA L0578,Y + PHA + LDA L0678,Y + TAY + CLC + PLA + BEQ LCDE2 + + SEC +.LCDE2 + RTS + +.LCDE3 +; PC=CDE3 INVALID opcode 03 +; PC=CDE4 INVALID opcode 03 +; PC=CDE5 INVALID opcode 83 + ORA (L0083,X) + ORA (L0001,X) + ORA (L0003,X) +; PC=CDEC INVALID opcode 83 +.LCDED + PHA + JSR LC9E5 + + PLA + TAX + LDA L0042 + PHA + LDA L0043 + PHA + LDA L0046 + PHA + STX L0046 + LDA #$05 + STA L0042 + LDA #$00 + STA L005A + LDA #$02 + STA L0043 + LDA #$42 + STA L0054 + LDA #$00 + STA L0055 + LDA #$80 + STA L005B + JSR LCA0F + +.LCE19 + INC L005A + LDA #$09 + STA L004D + LDA #$00 + STA L004E + JSR LC800 + + BCC LCE2D + + DEC L005A + JMP LCE34 + +.LCE2D + JSR LC960 + + LDA L004D + BEQ LCE19 + +.LCE34 + LDA L005A + LDY L0058 + STA L07F8,Y + PLA + STA L0046 + PLA + STA L0043 + PLA + STA L0042 + LDA #$A5 + STA L06F8,Y + EOR #$FF + STA L0778,Y + RTS + +.LCE4F + LDX L0058 + STA L05F8,X + TYA + STA L0678,X + RTS + +.LCE59 + STX L0058 + LDA #$AA + STA L0478,X + STA L06F8,X + LDY #$05 +.LCE65 + LDA LCF16,Y + STA L0042,Y + DEY + BPL LCE65 + + LDA L0058 + ASL A + ASL A + ASL A + ASL A + STA L0043 + JSR LCBE6 + + BCS LCE90 + + LDX L0800 + DEX + BNE LCE90 + + LDX L0801 + BEQ LCE90 + + LDA L0058 + ASL A + ASL A + ASL A + ASL A + TAX + JMP L0801 + +.LCE90 + JSR LFE93 + + JSR LFE89 + + LDX L0000 + BNE LCEA4 + + LDX L0001 + CPX L07F8 + BNE LCEA4 + + JMP LFABA + +.LCEA4 + LDX #$17 + STX L0025 + JSR LFC22 + + LDA #$00 + STA L0024 + LDX #$00 + LDY L0058 + LDA L04F8,Y + BNE LCEBA + + LDX #$0A +.LCEBA + CMP #$28 + BNE LCEC0 + + LDX #$1E +.LCEC0 + CMP #$2F + BNE LCEC6 + + LDX #$32 +.LCEC6 + LDA LCED4,X + BEQ LCED1 + + JSR LFDED + + INX + BNE LCEC6 + +.LCED1 + JMP LE000 + +.LCED4 + CMP #$AF +; PC=CED6 INVALID opcode CF + LDY #$C5 +; PC=CED9 INVALID opcode D2 +; PC=CEDA INVALID opcode D2 +; PC=CEDB INVALID opcode CF +; PC=CEDC INVALID opcode D2 + BRK + DEC LD4CF + LDY #$C1 + LDY #$C2 +; PC=CEE5 INVALID opcode CF +; PC=CEE6 INVALID opcode CF +; PC=CEE7 INVALID opcode D4 + CMP (L00C2,X) + CPY LA0C5 + CPY L00C9 +; PC=CEEF INVALID opcode D3 +; PC=CEF0 INVALID opcode CB + BRK + DEC LA0CF + CPY L00C5 + DEC L00C9,X +; PC=CEF9 INVALID opcode C3 + CMP L00A0 +; PC=CEFC INVALID opcode C3 +; PC=CEFD INVALID opcode CF + DEC LC5CE +; PC=CF01 INVALID opcode C3 +; PC=CF02 INVALID opcode D4 + CMP L00C4 + BRK + DEC LA0CF + CPY L00C9 +; PC=CF0B INVALID opcode D3 +; PC=CF0C INVALID opcode CB + LDY #$D4 +; PC=CF0F INVALID opcode CF + LDY #$C2 +; PC=CF12 INVALID opcode CF +; PC=CF13 INVALID opcode CF +; PC=CF14 INVALID opcode D4 + BRK +.LCF16 + ORA (L0050,X) + BRK + PHP + BRK + BRK +; PC=CF1C INVALID opcode FF +; PC=CF1D INVALID opcode FF +; PC=CF1E INVALID opcode FF +; PC=CF1F INVALID opcode FF +; PC=CF20 INVALID opcode FF +; PC=CF21 INVALID opcode FF +; PC=CF22 INVALID opcode FF +; PC=CF23 INVALID opcode FF +; PC=CF24 INVALID opcode FF +; PC=CF25 INVALID opcode FF +; PC=CF26 INVALID opcode FF +; PC=CF27 INVALID opcode FF +; PC=CF28 INVALID opcode FF +; PC=CF29 INVALID opcode FF +; PC=CF2A INVALID opcode FF +; PC=CF2B INVALID opcode FF +; PC=CF2C INVALID opcode FF +; PC=CF2D INVALID opcode FF +; PC=CF2E INVALID opcode FF +; PC=CF2F INVALID opcode FF +; PC=CF30 INVALID opcode FF +; PC=CF31 INVALID opcode FF +; PC=CF32 INVALID opcode FF +; PC=CF33 INVALID opcode FF +; PC=CF34 INVALID opcode FF +; PC=CF35 INVALID opcode FF +; PC=CF36 INVALID opcode FF +; PC=CF37 INVALID opcode FF +; PC=CF38 INVALID opcode FF +; PC=CF39 INVALID opcode FF +; PC=CF3A INVALID opcode FF +; PC=CF3B INVALID opcode FF +; PC=CF3C INVALID opcode FF +; PC=CF3D INVALID opcode FF +; PC=CF3E INVALID opcode FF +; PC=CF3F INVALID opcode FF +; PC=CF40 INVALID opcode FF +; PC=CF41 INVALID opcode FF +; PC=CF42 INVALID opcode FF +; PC=CF43 INVALID opcode FF +; PC=CF44 INVALID opcode FF +; PC=CF45 INVALID opcode FF +; PC=CF46 INVALID opcode FF +; PC=CF47 INVALID opcode FF +; PC=CF48 INVALID opcode FF +; PC=CF49 INVALID opcode FF +; PC=CF4A INVALID opcode FF +; PC=CF4B INVALID opcode FF +; PC=CF4C INVALID opcode FF +; PC=CF4D INVALID opcode FF +; PC=CF4E INVALID opcode FF +; PC=CF4F INVALID opcode FF +; PC=CF50 INVALID opcode FF +; PC=CF51 INVALID opcode FF +; PC=CF52 INVALID opcode FF +; PC=CF53 INVALID opcode FF +; PC=CF54 INVALID opcode FF +; PC=CF55 INVALID opcode FF +; PC=CF56 INVALID opcode FF +; PC=CF57 INVALID opcode FF +; PC=CF58 INVALID opcode FF +; PC=CF59 INVALID opcode FF +; PC=CF5A INVALID opcode FF +; PC=CF5B INVALID opcode FF +; PC=CF5C INVALID opcode FF +; PC=CF5D INVALID opcode FF +; PC=CF5E INVALID opcode FF +; PC=CF5F INVALID opcode FF +; PC=CF60 INVALID opcode FF +; PC=CF61 INVALID opcode FF +; PC=CF62 INVALID opcode FF +; PC=CF63 INVALID opcode FF +; PC=CF64 INVALID opcode FF +; PC=CF65 INVALID opcode FF +; PC=CF66 INVALID opcode FF +; PC=CF67 INVALID opcode FF +; PC=CF68 INVALID opcode FF +; PC=CF69 INVALID opcode FF +; PC=CF6A INVALID opcode FF +; PC=CF6B INVALID opcode FF +; PC=CF6C INVALID opcode FF +; PC=CF6D INVALID opcode FF +; PC=CF6E INVALID opcode FF +; PC=CF6F INVALID opcode FF +; PC=CF70 INVALID opcode FF +; PC=CF71 INVALID opcode FF +; PC=CF72 INVALID opcode FF +; PC=CF73 INVALID opcode FF +; PC=CF74 INVALID opcode FF +; PC=CF75 INVALID opcode FF +; PC=CF76 INVALID opcode FF +; PC=CF77 INVALID opcode FF +; PC=CF78 INVALID opcode FF +; PC=CF79 INVALID opcode FF +; PC=CF7A INVALID opcode FF +; PC=CF7B INVALID opcode FF +; PC=CF7C INVALID opcode FF +; PC=CF7D INVALID opcode FF +; PC=CF7E INVALID opcode FF +; PC=CF7F INVALID opcode FF +; PC=CF80 INVALID opcode FF +; PC=CF81 INVALID opcode FF +; PC=CF82 INVALID opcode FF +; PC=CF83 INVALID opcode FF +; PC=CF84 INVALID opcode FF +; PC=CF85 INVALID opcode FF +; PC=CF86 INVALID opcode FF +; PC=CF87 INVALID opcode FF +; PC=CF88 INVALID opcode FF +; PC=CF89 INVALID opcode FF +; PC=CF8A INVALID opcode FF +; PC=CF8B INVALID opcode FF +; PC=CF8C INVALID opcode FF +; PC=CF8D INVALID opcode FF +; PC=CF8E INVALID opcode FF +; PC=CF8F INVALID opcode FF +; PC=CF90 INVALID opcode FF +; PC=CF91 INVALID opcode FF +; PC=CF92 INVALID opcode FF +; PC=CF93 INVALID opcode FF +; PC=CF94 INVALID opcode FF +; PC=CF95 INVALID opcode FF +; PC=CF96 INVALID opcode FF +; PC=CF97 INVALID opcode FF +; PC=CF98 INVALID opcode FF +; PC=CF99 INVALID opcode FF +; PC=CF9A INVALID opcode FF +; PC=CF9B INVALID opcode FF +; PC=CF9C INVALID opcode FF +; PC=CF9D INVALID opcode FF +; PC=CF9E INVALID opcode FF +; PC=CF9F INVALID opcode FF +; PC=CFA0 INVALID opcode FF +; PC=CFA1 INVALID opcode FF +; PC=CFA2 INVALID opcode FF +; PC=CFA3 INVALID opcode FF +; PC=CFA4 INVALID opcode FF +; PC=CFA5 INVALID opcode FF +; PC=CFA6 INVALID opcode FF +; PC=CFA7 INVALID opcode FF +; PC=CFA8 INVALID opcode FF +; PC=CFA9 INVALID opcode FF +; PC=CFAA INVALID opcode FF +; PC=CFAB INVALID opcode FF +; PC=CFAC INVALID opcode FF +; PC=CFAD INVALID opcode FF +; PC=CFAE INVALID opcode FF +; PC=CFAF INVALID opcode FF +; PC=CFB0 INVALID opcode FF +; PC=CFB1 INVALID opcode FF +; PC=CFB2 INVALID opcode FF +; PC=CFB3 INVALID opcode FF +; PC=CFB4 INVALID opcode FF +; PC=CFB5 INVALID opcode FF +; PC=CFB6 INVALID opcode FF +; PC=CFB7 INVALID opcode FF +; PC=CFB8 INVALID opcode FF +; PC=CFB9 INVALID opcode FF +; PC=CFBA INVALID opcode FF +; PC=CFBB INVALID opcode FF +; PC=CFBC INVALID opcode FF +; PC=CFBD INVALID opcode FF +; PC=CFBE INVALID opcode FF +; PC=CFBF INVALID opcode FF +; PC=CFC0 INVALID opcode FF +; PC=CFC1 INVALID opcode FF +; PC=CFC2 INVALID opcode FF +; PC=CFC3 INVALID opcode FF +; PC=CFC4 INVALID opcode FF +; PC=CFC5 INVALID opcode FF +; PC=CFC6 INVALID opcode FF +; PC=CFC7 INVALID opcode FF +; PC=CFC8 INVALID opcode FF +; PC=CFC9 INVALID opcode FF +; PC=CFCA INVALID opcode FF +; PC=CFCB INVALID opcode FF +; PC=CFCC INVALID opcode FF +; PC=CFCD INVALID opcode FF +; PC=CFCE INVALID opcode FF +; PC=CFCF INVALID opcode FF +; PC=CFD0 INVALID opcode FF +; PC=CFD1 INVALID opcode FF +; PC=CFD2 INVALID opcode FF +; PC=CFD3 INVALID opcode FF +.LCFD4 +; PC=CFD4 INVALID opcode FF +; PC=CFD5 INVALID opcode FF +; PC=CFD6 INVALID opcode FF +; PC=CFD7 INVALID opcode FF +; PC=CFD8 INVALID opcode FF +; PC=CFD9 INVALID opcode FF +; PC=CFDA INVALID opcode FF + TAY +; PC=CFDC INVALID opcode C3 + LDA #$A0 + LDA (L00B9),Y + CLV + LDA L00A0,X + CMP (L00F0,X) + BEQ LCFD4 + + SBC L00A0 +; PC=CFEA INVALID opcode C3 +; PC=CFEB INVALID opcode EF + SBC LF5F0 +; PC=CFEF INVALID opcode F4 + SBC L00F2 + LDY LC9A0 + INC LAEE3 + LDY #$CD +; PC=CFFA INVALID opcode D3 + CMP (L0000,X) + BPL LCFFE + +.LCFFF +; PC=CFFF INVALID opcode FF +.BeebDisEndAddr +SAVE "disasm.bin",BeebDisStartAddr,BeebDisEndAddr + diff --git a/disk-II-boot-process.txt b/disk-II-boot-process.txt new file mode 100644 index 0000000..dd0a966 --- /dev/null +++ b/disk-II-boot-process.txt @@ -0,0 +1,817 @@ +****************************************************************** +* * +* THE BOOT PROCESS * +* * +****************************************************************** +* * +* The following disassembly describes the boot process for * +* a slave disk. In order to TRULY understand this listing, you * +* should first be familiar with the exact sequence and coding of * +* disk bytes used in track formatting. This information can be * +* found in chapter 3 of the book BENEATH APPLE DOS. (The * +* distinctions between booting a slave disk versus a master disk * +* are described in chapter 8 of the same reference.) * +* The boot process loads DOS into the machine as a series * +* of discrete packages. After each package is loaded, it is * +* executed to load in the next section of DOS. The last * +* instruction of the boot process jumps into DOS's coldstart * +* routine to build the DOS buffers, set up the page-three vector * +* table and run the "HELLO" program. * +* Because DOS is loaded in stages, any protected disk can * +* cracked by tracing the boot. If you modify each section of * +* the boot to stop after loading the next section, you can * +* inspect the different stages of the boot to discover the * +* protection scheme(s) used. (P.S. In order to modify BOOT0, * +* you must first move it down to a RAM location defined by: * +* $hs00, where h = high nibble of an address that is low enough * +* to accomodate DOS in free memory above and, s = present slot * +* number housing the disk controller card.) * +* * +****************************************************************** + + + + +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* +* * +* BOOT 0 * +* * +*----------------------------------------------------------------* +* * +* - relocatable code resident on the disk controller's ROM. * +* - because the code is relocatable, the disk controllers card * +* can be used in different slots. Execution begins at $Cs00, * +* where s = slot number (ex. $C600 for card in slot 6). * +* - When BOOT0 is executed it: * +* (1) builds a table of indices which are used to convert * +* the disk bytes into 6/2 encoded bytes which are * +* needed by RWTS to translate the disk bytes into * +* normal memory bytes. * +* (2) recalibrates the disk arm by moving it to trk0/sec0. * +* (3) reads BOOT1 into $800 to $8FF (from trk0/sec0). * +* (4) jumps to $801 to begin the execution of BOOT1. * +* * +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* + +(Cs00) +BOOT0 LDX #$20 ;Controller card's identification byte. + +* Construct a read-translate table which +* we will need to convert disk bytes to +* encoded memory bytes. (The encoded memory +* bytes later go trough further decoding to +* convert them to normal memory bytes.) +* +* We construct the table by sequentially +* incrementing (x) and testing it to see +* if it meets the folowing criteria of a +* disk byte: +* (1) it must have at least one pair of +* adjacent 1's in bits 0 to 6. +* (2) it must not have more than one pair +* of adjacent 0's in bits 0 to 6. +* (Note that we use the x-value to represent +* only the lower seven bits of a disk byte +* because all disk bytes are negative.) +* +* Each time we find an (x) that represents +* a simulated disk byte, we increment (y). +* (Y) is then placed in the read table at an +* offset of (x) from the beginning of the table. +* The table generated is shown below. The +* empty bytes represent offsets where (x) +* did not meet the criteria of a disk byte. +* The values in parentheses represent the +* (x)-values tested. +* 36C- 00 01 -- -- +* (16) (17) (18) (19) +* 370- 02 03 -- 04 05 06 -- -- +* (1A) (1B) (1C) (1D) (1E) (1F) (20) (21) +* 378- -- -- -- -- 07 08 -- -- +* (22) (23) (24) (25) (26) (27) (28) (29) +* 380- -- 09 0A 0B 0C 0D -- -- +* (2A) (2B) (2C) (2D) (2E) (2F) (30) (31) +* 388- 0E 0F 10 11 12 13 -- 14 +* (32) (22) (34) (35) (36) (37) (38) (39) +* 390- 15 16 17 18 19 1A -- -- +* (3A) (3B) (3C) (3D) (3E) (3F) (40) (41) +* 398- -- -- -- -- -- -- -- -- +* (42) (43) (44) (45) (46) (47) (48) (49) +* 3A0- -- 1B -- 1C 1D 1E -- -- +* (4A) (4B) (4C) (4D) (4E) (4F) (50) (51) +* 3A8- -- 1F -- -- 20 21 -- 22 +* (52) (53) (54) (55) (56) (57) (58) (59) +* 3B0- 23 24 25 26 27 28 -- -- +* (5A) (5B) (5C) (5D) (5E) (5F) (60) (61) +* 3B8- -- -- -- 29 2A 2B -- 2C +* (62) (63) (64) (65) (66) (67) (68) (69) +* 3C0- 2D 2E 2F 30 31 32 -- -- +* (6A) (6B) (6C) (6D) (6E) (6F) (70) (71) +* 3C8- 33 34 35 36 37 38 -- 39 +* (72) (73) (74) (75) (76) (77) (78) (79) +* 3D0- 3A 3B 3C 3D 3E 3F -- -- +* (7A) (7B) (7C) (7D) (7E) (7F) + + +(Cs02) LDY #0 ;Initialize the (y) index. +(Cs04) LDX #3 ;"3" is used for controller ID. Any number + ;between 0 and #$16 could be used. Except + ;for ID purposes, the operand isn't even + ;relevant until it is #$16 (dec #22). +BUILDTBL STX BT0SCRTH ;Save potential index seed in the zero page. +(Cs06) + +* Transfer (x) to (a) and test to see if it +* meets the following disk byte criteria: +* (1) has at least one pair of adjacent 1's +* in bits 0 to 6. +* (2) has no more than one pair of adjacent +* 0's in bits 0 to 6. + +* Test for adjacent 1's. +* +* Note: by comparing a shifted version of +* the seed (in accumulator) with the original +* version of the seed (in BT0SCRTH, $3C) we are +* actually testing adjacent bits as shown below: +* Shifted: b6 b5 b4 b3 b2 b1 b0 0 +* Orignal: b7 b6 b5 b4 b3 b2 b1 b0 +* ----------------------------------- +* Testing: b6,7 b5,6 b4,5 b3,4 b2,3 b1,2 b0,1 - + +(Cs08) TXA + ASL +(Cs0A) BIT BT0SCRTH ;Conditions the z-flag of the status. + ;(If any bits match, z-flag=1.) +(Cs0C) BEQ GETNEWX ;Branch if value was illegal. + ;Illegal value = z-flag=1 = no match = no + ;adjacent 1's. + +* Got at least 1 pair of adjacent 1's, so +* now prepare to test for adjacent 0's. +* (Note: the previous "BIT" instruction +* alters the z-flag in the status but +* does not affect the accumulator.) +(Cs0E) ORA BT0SCRTH ;Merge shifted version of seed with orig. +(Cs10) EOR #$FF ;Take 1's compliment of shifted version to + ;swap 1's for 0's and 0's for 1's. +(Cs12) AND #%01111110 ;Throw away the hi and least significant + ;bits so will be testing: + ; b5,6 b4,5 b3,4 b2,3 b1,2 b0,1. + +* Test for pairs of adjacent 0's. +* Remember, only 1 pair of adjacent 0's is +* allowed. Because we did a 1's compliment +* of the merged bits above, a SET BIT NOW +* DENOTES A PAIR OF ADJACENT 0's. We can +* therefore test for a pair of adjacent 0's +* by shifting a bit into the carry: +* - if (c) = 1 = at least one pair of adjacent 0's +* is present. +* - if (c) = 1 AND the remaining byte = 0 then +* we have only one pair of adjacent 0's so +* value is legal. +* - if (c) = 1 AND the remaining byte < > 0, we +* have more than one pair of adjacent 0's so +* value is illegal. +(Cs14) +TESTCARY BCS GETNEWX ;Always fall through on very first entry. + ;If branch is taken, got illegal value + ;because more than 1 pr of adjacent 0's. +(Cs16) LSR ;Shift a bit into the carry (if carry set + ;have at least 1 pr of adjacent 0's). +(Cs17) BNE TESTCARY ;Take branch when remaining byte is not + ;zero. Got at least 1 pr of adjacent 0's. + ;Go test carry to see if another pair has + ;already been detected. + +* Index byte was legal. We either got no +* adjacent 0's or else only one pair of +* adjacent 0's. +(Cs19) TYA ;Store the counter that corresponds to a +(Cs1A) STA BTNIBL-$16,X ;legal nibble. The first (x) value used + ;is #$16, last is #$7F. The first (y) value + ;stored is 0, the last is #$3F. +(Cs1D) INY +GETNEWX INX +(Cs1F) BPL BUILDTBL ;Keep on trying to build table until (x) + ;increments to #$80. + +* Find out which slot the disk controller +* card resides in. +(Cs21) JSR MONRTS ;Jsr to an RTS to put the present address on + ;the stack. The hi byte of the present addr + ;($Cs) tells us what slot (s) the card is + ;located in. + + * An RTS instruction in monitor ROM. + (FF58) + MONRTS RTS + +(Cs24) TSX ;Put the value of the stack pointer in (x). +(Cs25) LDA STACK,X ;Get the hi byte of the controllers address + ;($Cs) from the stack. +(Cs28) ASL ;Multiply by 16 (throwing away original hi + ASL ;nibble) so we are left with #$s0. + ASL + ASL ;(a) = slot * 16. + STA SLT16ZPG ;Save slot*16 in a zero-page location. +(Cs2E) TAX ;Set (x) = slot * 16 so we can index the + ;base addresses associated with the drive + ;functions. +(Cs2F) LDA Q7L,X ;Set the READ mode. + LDA Q6L,X + LDA SELDRV1 ;Select drive 1. +(Cs38) LDA MTRON,X ;Spin the disk. + +* Move disk arm to track 0 by doing a +* recalibration. (That is, force the arm +* against the stop by pretending that it +* is presently at trk decimal 40.) +* (The arm is moved by sequentially turning +* a series of magnets off and on.) +(Cs3B) LDY #80 ;Pretend arm is at trk40 (dec 80 half-trks). +MAGNTOFF LDA MAG0FF,X ;Turn the presently aligned magnet off. +(Cs40) TYA ;Calculate the next magnet that should be + ;turned on to suck the arm over. +(Cs41) AND #%00000011 ;Only keep the lower two bits because we + ;only want a maximum value of 3 because + ;there are only 4 magnets (which are indexed + ;by values 0 to 3). The sequence used in + ;this loop is: 3,2,1,0,3... +(Cs43) ASL ;Multiply by 2 so the index is directed to + ;an address that turns a magnet ON. The + ;sequence used is: 6,4,2,0,6...0. +(Cs44) ORA SLT16ZPG ;Merge the index with the slot * 16 value. + TAX ;Put the calculated index in (x). + LDA MAG0N,X ;Turn the appropriate magnet ON. +(Cs4A) LDA #$56 ;Delay approximately 20 000 machine cycles + ;(approximately 20 milliseconds.) (Gives +(Cs4C) JSR WAIT ;arm time to align with energized magnet + ;and reduces overshoot or bounce.) + + * Monitor ROM's main delay routine. + * Delay z number of cycles based on + * the formula: + * z = ((5 * a^2) + (27 * a) +26) / 2 + * where a = value in the accumulator on entry. + (FCA8) + WAIT SEC ;Prepare for subtraction. + WAIT2 PHA ;Save (a) on the stack. + WAIT3 SBC #1 ;Keep on reducing (a) until it equals 0. + BNE WAIT3 + PLA + SBC #1 ;Reduce the original (a) down to 0 again. + BNE WAIT2 + (FCB3) RTS + +(Cs4F) DEY ;Reduce trk # count. +(Cs50) BPL MAGNTOFF ;Not at trk0 yet, so go move arm some more. + +* Initialize the buffer pointer and trk/sec values. +* (On entry: (x) = slot *16, (y) = #$FF & (a) = $00.) +(Cs52) STA PT2BTBUF ;Set the low byte of the buf pointer to $00. + STA BOOTSEC ;Initialize for sector 0 on track 0. + STA BOOTRK + LDA #8 ;Set the hi byte of the buf pointer to $08 +(Cs5A) STA PT2BTBUF+1 ;(that is, direct pointer at $800). + +* Prepare to start reading a prologue. +(Cs5C) +BTRDSEC CLC ;(c) = 0 = signal to read an addr prologue. + +* Begin reading a prologue. +(Cs5D) +PRSRVFLG PHP ;Preserve the status denoting if reading + ;address ((c)=0) or data ((c)=1) prologue. + +* Look for an address prologue ("D5 AA 96") +* or a data prologue ("D5 AA AD"). +(Cs5E) +STARTSEQ LDA Q6L,X ;Read a disk byte. + BPL STARTSEQ ;Wait for a full byte. +BTRYD5 EOR #$D5 ;Is it a "D5"? + BNE STARTSEQ ;No - restart sequence. +BTRYAA LDA Q6L,X ;Read next byte in header. + BPL BTRYAA ;Wait for a full byte. + CMP #$AA ;Is it an "AA"? + BNE BTRYD5 ;No - restart sequence. + NOP ;Delay 2 cycles. +BTRY96 LDA Q6L,X ;Read third byte in header. + BPL BTRY96 ;Wait for a full byte. + CMP #$96 ;Is it a "96"? +Cs78) BEQ RDVLTKSC ;Found an address prologue, so now go read + ;the vol, trk, sec values in the header. + +* The first two bytes were "D5 AA". +* The 3rd byte was not "96". Therefore, +* although we know this isn't an address +* prologue, maybe it is a data prologue. +(Cs7A) PLP ;Get the status back off the stack so we can + ;check if we were looking for an address or + ;data prologue. +(Cs7B) BCC BTRDSEC ;Branch back to try again if we were looking + ;for an address prologue but didn't find it. + +* We were looking for a data prologue so +* now compare the 3rd byte with that of a +* data prologue. +(Cs7D) +BTRYAD EOR #$AD ;Is it an "AD"? + BEQ RDBTDATA ;Yes - found data prol so now read in data. +(Cs81) BNE BTRDSEC ;No - go try again to find sequence 4 data. + +* Read volume, track and sector values in +* the address header. +* Remember, @ of these pieces of information +* are housed in two bytes in an odd-even encoded +* format: 1rst byte: 1 b7 1 b5 1 b3 1 b1 (odd-encoded). +* 2nd byte: 1 b6 1 b4 1 b2 1 b1 (even-encoded). +* We must decode these bytes to check if we located +* the correct volume, track and sector. +(Cs83) +RDVLTKSC LDY #3 ;Set counter for 3 decoded bytes. +MOREBYTS STA BOOTEMP ;Only relevant the last time through the +(Cs85) ;loop at which time it contains the decoded +(Cs87) ;track number read off the disk. +BTRDODD LDA Q6L,X ;Read odd-encoded byte. + BPL BTRDODD ;Wait for a full byte. +(Cs8C) ROL ;Throw away the hi bit & shift the odd bits + ;to their regular position. +(Cs8D) STA BT0SCRTH ;Save realigned version of odd-encoded byte. +BTRDEVEN LDA Q6L,X ;Read the even-encoded byte. + BPL BTRDEVEN ;Wait for a full byte. + AND BT0SCRTH ;Merge the two bytes. + DEY ;Reduce counter for # of bytes to rebuild. + BNE MOREBYTS ;Branch if more bytes to patch back together. + PLP ;Throw the status on the stack away. + CMP BOOTSEC ;Is the sector read = sector wanted? + BNE BTRDSEC ;No - go back to find correct sector. + LDA BOOTEMP ;Get decoded trk # just read off disk. + CMP BOOTRK ;Is trk found = trk wanted? + BNE BTRDSEC ;No - go back to try again. +(CsA4) BCS PRSRVFLG ;ALWAYS - just read addr field, so now go + ; read the data prologue. + +* Read the sector's data bytes. + +* Read the first 86 ($56) bytes of the sector. Use +* the disk byte as an index to the BTNIBL table ($36C-$3D5). +* Get the value from BTNIBL table & EOR it with the +* previous EOR result (except on entry, use +* #0 EOR BTNIBL-$96,Y) to produce a 2-encoded nibble. +* (On entry, (a) = 0.) +(CsA6) +BTRDATA LDY #$56 ;Read $56 (dec #86) bytes. +KEEPCNT1 STY BT0SCRTH ;Save the counter. +RDDSK1 LDY Q6L,X ;Read a disk data byte. + BPL RDDSK1 ;Wait for a full byte. +(CsAF) EOR BTNIBL-$96,Y ;Use disk byte as an index to the table + ;and EOR to decode to a 2-encoded nibble. +(CsB2) LDY BT0SCRTH ;Retrieve the counter. + DEY ;Reduce the counter (& condition z-flag). + STA BUF300,Y ;Store 2-encoded nibble in page 3 buffer. +(CSB8) BNE KEEPCNT1 ;Branch if more bytes to read. + +* Read the rest of the sector (256 disk bytes +* remaining). Use disk byte as an index to BTNIBL +* table. Get value from nibble table and EOR it +* with previous EOR result to yeild a 6-encoded +* nibble. (On entry, (y) = 0.) +(CsBA) +KEEPCNT2 STY BT0SCRTH ;Set disk byte counter = 0. +RDDSK2 LDY Q6L,X ;Read a disk byte. + BPL RDDSK2 ;Wait for a full byte. +(CsC1) EOR BTNIBL-$96,Y ;Use disk byte as an index to the nibble + ;table and EOR it with previous result to + ;produce a 6-encoded nibble. +(CsC4) LDY BT0SCRTH ;Get index to buffer. + STA (PT2BTBUF),Y ;Store 6-encoded nibble in buffer. + INY ;Kick up offset into buffer. +(CsC9) BNE KEEPCNT2 + +* Read and test the data checksum. +* On entry, (a) = result of previous cummulative +* EORing. Therefore, any non-cancelling errors are +* detected at the BNE instruction below. +(CsCB) +RDCK LDY Q6L,X ;Read the data checksum. + BPL RDCK ;Wait for a full byte. +(CsD0) EOR BTNIBL-$96,Y ;EOR byte read with the previous + ;cummulative result. +TSTRERD BNE BTRDSEC ;Bad checksum so branch back to re-read. +(CsD3) ;(Also branches to here if got a good read + ;but there are more sectors to read if the + ;first byte of BOOT1 is modified to allow + ;BOOT0 to read more than 1 sector (see + ;comments below). + +* Convert 6-and-2 encoded buffer bytes to +* normal 8-bit memory bytes. +(CsD5) LDY #0 ;Initialize index to target memory byte. +SETX56 LDX #$56 ;Set index to buf containing encoded bytes. +DOWNX DEX ;Reduce index for next buffer byte. + BMI SETX56 ;Reset index to encoded buffer. + LDA (PT2BTBUF),Y ;Get (a) = 6-encoded nibble. + LSR BUF300,Y ;Put a bit from the 2-encoded buffer in (c) + ROL ;and then roll it into the 6-encoded nibble. + LSR BUF300,Y ;Do the same with the next bit of the pair. + ROL + STA (PT2BTBUF),Y ;Store the re-constructed 8-bit byte in memory. + INY ;Increase the offset to the buffer. +(CsE9) BNE DOWNX ;Branch back if more bytes to reconstruct. + +* Prepare to read in the next sector. +* NOTE: Normaly only trk0/sec0 (which +* represents BOOT1) is read in by BOOT0. +* The number of sectors read in by BOOT0 is +* determined by the first byte of BOOT1. +* Whereas BOOT1 resides in memory on an 48K +* INITed disk at $B600 - $B6FF, we can zap a +* disk at $B600 with the # of sectors we +* we would like BOOT0 to read in if we want +* it to read in more than 1 sector. +(CsEB) INC PT2BTBUF+1 ;Just crossed page boundary, so kick up + ;the hi byte of the target address. +(CsED) INC BOOTSEC ;Set value for next sector wanted. + LDA BOOTSEC ;Get next sector wanted. +(CsF1) CMP $800 ;Test if read enough sectors. + ;First byte of image of BOOT1 normally + ;contains #$01 which denotes only 1 sector + ;(sec0/trk0) should be read in by BOOT0. +(CsF4) LDX SLT16ZPG ;(x) = slot *16. + BCC TSTRERD ;Branch back to read more sectors. +(CsF8) JMP BT1EXC08 ;Jumps into BOOT1 (which was copied into + ------------ ;page 8 from trk0/sec0) to begin execution + ;of BOOT1. + + +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* +* * +* BOOT 1 * +* * +*----------------------------------------------------------------* +* * +* - stored on trk0/sec0. * +* - IMAGE in memory on a 48K system resides at $B600 - $B6FF. * +* - read into $800 to $8FF by the disk controller ROM (BOOT0). * +* - execution begins at $801 & uses the controller's read sector * +* subroutine (BTRDSEC, Cs00, where s = slot # of card) to read * +* in trk0/sec9 down to trk0/sec1 ($BFFF --> $B600). * +* - NOTE: In order to generate an accurate symbol table that * +* can be applied 2 both the formatted & linear disassemblies, * +* and because different assemblers vary in their abilities to * +* accept certain OBJect values or re-ORG during assembly, the * +* following special label system has been created: * +* Image label/adr Execution label/adr Comments * +* --------------- ------------------- -------------------- * +* SEC2RDB6, $B600 SEC2RD08, $800 ;Defines # of secs to * +* ;be read in by boot0. * +* BT1EXCB6, $B601 BT1EXC08, $801 ;Start of boot1. * +* ;Boot0 jumps to this * +* ;location. * +* SKPRELB6, $B61F SKPREL08, $81F ;Target labl 4 brnch. * +* PRP4B2B6, $B639 PRP4B208, $839 ;Target labl 4 brnch. * +* IMG8FD, $B6FD BT1LDADR, $8FD ;Boot1 load address. * +* ;Varies from $B600 to * +* ;$BF00. Eventually * +* ;pts 2 start of boot2 * +* ;($B700). * +* IMG8FF, $B6FF BT1PG2RD, $8FF ;Contains # of secs 2 * +* ;be read in when * +* ;executing boot1. Also* +* ;doubles as logical * +* ;sec #. Varies from: * +* ;$09 --> $00 --> $FF. * +* - As indicated above, SEC2RD08 ($800) defines the number of * +* sectors to be read in by boot0. This value is normally $01 * +* (meaning read only sector0 of track0). However, you can zap * +* trk0/sec0/offset0 with a larger value ($01 to $10) to read * +* more sectors from trk0. Also note that most references say * +* that SEC2RD08 normally contains a "$00" (rather than a * +* "$01"). Because the test at $CsF6 uses the carry, either * +* value will only cause one sector to be read in. However, * +* "$01" is the value used by DOS. (Confusion may stem from * +* the fact that Applesoft later stores a $00 in memory at * +* $800.) * +* * +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* + + +(B600) <============= image address. +SEC2RDB6 +(800) <============== execution address. +SEC2RD08 HEX 01 ;Defines the number of sectors to be read + ;in from track 0 during BOOT0. + +(B601) +BT1EXCB6 +(801) +BT1EXC08 LDA PT2BUF+1 ;Get the next page to read in. + CMP #$09 ;Is it page 9 (ie. first page read by BOOT1)? + BNE SKPREL08 ;No - already used by BOOT1 to read page 9, + ;so skip pointer initialization given below. + +* Initialize the pointer (PT2RDSC) to point +* at BOOT0's read sector subroutine (BTRDSEC, +* $Cs5C, where s = slot #, normally $C65C). +(B607) +(807) LDA SLT16ZPG ;(a) = slot *16. + LSR ;Divide by 16. + LSR + LSR + LSR + ORA $C0 ;Merge with $C0 to get $Cs, where s=slot#. + STA PTR2RDSC+1 ;Store the hi byte of the address of the + ;controller's read sector subroutine. + LDA # $FF.) + BMI PRP4B208 ;When (x) = $FF, we have read all the + ;sectors in so go exit. + LDA PHYSECP8-$AE00,X ;Convert the logical sector number + ;to a physical sector number. (Equivalent + ;to "LDA $84D,X".) + STA BOOTSEC ;Store physical sector number in page0. + DEC BT1PG2RD ;Reduce sectors (pages) left to read for + ;the next time around. + LDA BT1LDADR+1 ;Point the buffer pointer at the target + STA PT2BTBUF+1 ;address. (Varies from $BF to $B6 on a + ;48K slave.) + DEC BT1LDADR+1 ;Reduce the hi byte of the I/O buffer for + ;the next time around. (Varies from $BF to + ;$B5 on a 48K slave.) + LDX SLT16ZPG ;Set (x) = slot*16. +(836) JMP (PTR2RDSC) ;Equivalent to "JMP ($8FD)" or "JMP $Cs5C" +(B636) ------------ ;to go read in the next sector. + ;***************** NOTE ******************* + ;* GOES TO BT1EXC08 ($801) AFTER @ SECTOR * + ;* IS READ IN. (BT1EXCB6 is a carbon copy * + ;* of BT1EXC08.) * + ;****************************************** + +* Prepare for BOOT2. +(B639) +PRP4B2B6 +(839) +PRP4B208 INC BT1LDADR+1 ;Point at the load address for BOOT2. + INC BT1LDADR+1 ;(After the INCs = $B7 on 48K slave.) + +* Set full screen text & designate the +* keyboard and screen as the I/O devices. +(B63F) +(83F) JSR SETKBD ;Simulate an IN#0. (See dis'mbly below.) + JSR SETVID ;Simulate an PR#0. (See dis'mbly below.) + JSR INIT ;Simulate a "TEXT" statement. (See dis'mbly + ;in APPLE II REFERENCE MANUAL at $FB2F.) + LDX SLT16ZPG ;(x) = slot * 16. + +* Go to BOOT2. +(B64A) +(84A) JMP (BT1LDADR) ;Jump to BOOT2 ($B700 on 48K slave). + -------------- + + +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* +* * +* BOOT2 * +* * +*----------------------------------------------------------------* +* * +* - Reads in the rest of DOS starting at trk02/sec04 down to * +* trk00/sec0A ($B5FF --> $9B00). (P.S. Sectors 0A and 0B of * +* track 0 are empty ($9CFF - $9B00).) * +* - After the rest of DOS is read in, execution jumps to DOS's * +* coldstart routine (DOSCLD, $9D84). * +* - Note that on entry: (x) = slot * 16 * +* * +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* + + +* Prepare RWTS's input-output block (IOB) +* and designate the number of sectors to read. +(B700) +BOOT2 STX IBSLOT ;(x) = slot*16 wanted. + STX IOBPSN ;Last-used slot*16 value. + LDA #1 ;Set both the last-used and wanted drives + STA IOBDPDN ;as drive #1. + STA IBDRVN + LDA NMPG2RD ;Set number of pages (ie. secs) to read. + STA BT2PGCTR ;Counter for for number of pages to read. + LDA #2 ;Start with trk02/sec04. + STA IBTRK ;Track. + LDA #4 + STA IBSECT ;Sector. +(B71E) LDY BT1MGADR+1 ;(y) = hi byte of the address of the image + ;of BOOT1 (#$B6 on a 48K slave). +(B721) DEY ;Define I/O buf as 1 page below boot1. + STY IBBUFP+1 + LDA #1 ;Opcode for read. +(B727) STA IBCMD + +* Convert from (x) = slot*16 to (x) = slot. +(B72A) TXA ;(x) = slot * 16. + LSR ;Divide by 16. + LSR + LSR + LSR +(B72F) TAX ;(x) = slot. + +* Initialize the page-four locations with +* the track numbers associated with the drives. +(B730) LDA #0 + STA TRK4DRV2,X +(B735) STA TRK4DRV1,X + +* Call the routine to read in the rest of DOS. +(B738) JSR RWPAGES + + * READ/write a group of pages. + (B793) + RWPAGES LDA ADROFIOB+1 ;Init (a)/(y) with the hi/low bytes of the + LDY ADROFIOB ;addr of RWTS's IOB for entry to RWTS. + (B799) JSR ENTERWTS ;Enter RWTS to read/write sector. + + * Entry to RWTS. + (B7B5) + ENTERWTS PHP ;Save status register on the stack. + (B7B6) SEI ;Set the interrupt disable flag to prevent + ;any further maskable interrupts when doing + ;real-time programming. + (B7B7) JSR RWTS ;Enter RWTS proper to do the operation: + ; $00=seek, $01=read, $02=write, $03=format. + + * RWTS proper. + (BD00) + RWTS . + . + (See dis'mbly in RWTSDRVR using READ.) + . + . + (RTS) + + (B7BA) BCS ERRENTER ;Operation was NOT successful. + PLP ;Retrieve saved status off the stack. + (B7BE) RTS + ============ + + (B7BF) + ERRENTER PLP ;Throw the saved status off the stack. + SEC ;Signal operation was unsuccessful. + (B7C1) RTS + ============ + + (B79C) LDY IBSECT ;Get # of the sector just read or written. + (B79F) DEY ;Set value for next sector 2 read. When + ;executing BOOT1, goes from $09 to $FF. + (B7A0) BPL SAMETRK ;Branch to use the same track. + + * Start a new track. + (B7A2) LDY #$0F ;Start with sector 15. + NOP + NOP + (B7A6) DEC IBTRK ;Reduce number of track wanted. + + * Reduce the addr of the target memory location. + * Test if more sectors to read. + (B7A9) + SAMETRK STY IBSECT ;Store the sector wanted. + DEC IBBUFP+1 ;Reduce buf addr of target memory location. + DEC BT2PGCTR ;Reduce counter for # of sectors to read. + BNE RWPAGES ;More sectors to read. + (B7B4) RTS + +(B73B) LDX #$FF ;Completely clear out the stack. + TXS + STX IBVOL ;Set the volume to $FF (compliment of 0). +(B741) JMP CLOBCARD + ------------ + +* Patch to clobber the language card +* and set video output. +(BFC8) +CLOBCARD JSR SETVID ;Select the video screen. + + * Monitor ROM's routine to designate the + * video screen as the output device. + * (Simulate a "PR#0" statement.) + (FE93) + SETVID LDA #0 ;Designate slot 0. + OUTPORT STA A2L + OUTPRT LDX #COUT1 ;(Hi byte of addr of KEYIN & COUT1 are equal.) + IOPRT2 STY LOC0,X ;Set CSW: COUT1. + STA LOC1,X + (FEAD) RTS + +(BFCB) LDA $C081 ;Write enable the RAM card. + LDA $C081 ;(Read motherboard / write card bank 2.) + LDA #0 ;Set the language identifying byte on the +(BFD3) STA BASICCLD ;card to $00 so if card is tested (during + ;an FP command), the machine will be forced + ;to use the motherboard version of FP. +(BFD6) JSR CONTCLOB ;Now clobber the 80-column card. + + * Clobber the 80-column card. + (BA76) + CONTCLOB LDA #$FF ;Set the mode flag for card. + STA $4FB ;Scratch pad memory for slot 3 peripheral. + STA $C00C ;Turn off the alternate character set. + STA $C00E + (BA81) JMP INIT ;Simimulate a TEXT statement. + ------------ + + * Monitor ROM's Init routine. + (FB2F) + INIT . + . + (See dis'mbly in APPLE II REFERENCE MANUAL.) + . + . + - simulate a text statement. + (Ie. set window to full screen text.) + . + . + (RTS) + +(BFD9) JMP BK2BOOT2 ;Return to original part of BOOT2. + ------------ + +* Return back to original part of BOOT2. +(B744) +BK2BOOT2 JSR SETKBD ;Select the keyboard. + + * Monitor ROM's routine to designate the + * keyboard as the input device. + * (Simulate a "IN#0" statement.) + (FE89) + SETKBD LDA #0 ;Pretend using slot 0. + INPORT STA A2L + INPRT LDX #COUT1 ;(Hi byte of the addr of KEYIN & COUT1 are equal.) + IOPRT2 STY LOC0,X ;Set KSW: KEYIN. + STA LOC1,X + (FEAD) RTS + +(B747) JMP DOSCOLD ;Jump into DOS's coldstart routine to build + ------------ ;the DOS buffers and the page-three vector + . ;table and then run the "HELLO" program. + . ;*************** N O T E ***************** + . ;* This instruction is a hacker's dream. * + . ;* For instance, you can change the jump * + . ;* to point to you own password or time- * + . ;* bomb routine that you have deviously * + . ;* embedded in an unused section of DOS. * + . ;***************************************** + . + . + . +*---------------------* +* SEE dis'mbly titled * +* "DOSCOLDSTART" * +*---------------------* + . + . + . \ No newline at end of file diff --git a/eagle/DB19F adapter/big-mess-o-wires.lbr b/eagle/DB19F adapter/big-mess-o-wires.lbr new file mode 100644 index 0000000..72be529 --- /dev/null +++ b/eagle/DB19F adapter/big-mess-o-wires.lbr @@ -0,0 +1,526 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>SUB-D</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +10 +11 +19 + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +10 +11 +19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + +<b>SUB-D</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/eagle/DB19F adapter/db19f.brd b/eagle/DB19F adapter/db19f.brd new file mode 100644 index 0000000..423224e --- /dev/null +++ b/eagle/DB19F adapter/db19f.brd @@ -0,0 +1,575 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +DB19F WWW.BIGMESSOWIRES.COM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +10 +11 +19 + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +<b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie fĂĽr +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab. +<b>Laen's PCB Order Design Rules</b> +<p> +Please make sure your boards conform to these design rules. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/eagle/DB19F adapter/db19f.sch b/eagle/DB19F adapter/db19f.sch new file mode 100644 index 0000000..cbaa306 --- /dev/null +++ b/eagle/DB19F adapter/db19f.sch @@ -0,0 +1,707 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +10 +11 +19 + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE + + + + + +>VALUE + + + + + +<b>SUPPLY SYMBOL</b> + + + + + + + + + + + + +<b>SUPPLY SYMBOL</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/eagle/FPGA disk controller/ELL-i-DigitalIC.lbr b/eagle/FPGA disk controller/ELL-i-DigitalIC.lbr new file mode 100644 index 0000000..9c37fb7 --- /dev/null +++ b/eagle/FPGA disk controller/ELL-i-DigitalIC.lbr @@ -0,0 +1,6152 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>DigitalIC -- ELL-i open source co-op Eagle libraries</h3> + +<p>In this library you'll find digital ICs, such as MCUs, that are used in the ELL-i boards.</p> + +<p>Whenever possible, we prefer to use the components from the <a href="https://github.com/Ell-i/SparkFun-Eagle-Libraries">SparkFun Public Eagle PCB Footprints</a>, as they are available from <a href="https://github.com/">GitHub</a>. Whenever possible, we also prefer to push our components to the SparkFun libraries. However, this is not always possible, and therefore we have our own libraries that for the most part contain components that cannot be found in the SparkFun libraries.</p> + + +<h3>24 leads Quad-flat no-leads package (QNF)</h3> + +<p>4x4 mm, 0.5 mm pitch. See the SparkFun-DigitalIC.lbr for additional QFN24 packages.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/QFN">Wikipedia article on QFNs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +<h3>24 leads Quad-flat no-leads package (QNF) with a hole</h3> + +<p>4x4 mm, 0.5 mm pitch, with a central hole. This footprint may be better than the regular one, depending on your process and intentions. See the SparkFun-DigitalIC.lbr for additional QFN24 packages.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/QFN">Wikipedia article on QFNs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + +<h3>144 leads Low Profile Quad Flat Package (LQFP)</h3> + +<p>20x20 mm, 0.5 mm pitch, 1.5 mm height.</p> + +<p><b>Note</b> that this package has a "phantom" pad in the middle of it, i.e. a pad whose size is 0.00x0.00 mm, and who is named as NC (not connected). This is needed as the STM32F42x has an extra pin (BYPASS_REG) in the WLCSP143 package, while it does not have it in the LQFP package. This avoids us from having two different devices.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>144 leads Thin Profile Quad Flat Package (TQFP)</h3> + +<p>20x20 mm, 0.5 mm pitch, 1 mm height.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/TQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>100 leads Low Profile Quad Flat Package (LQFP)</h3> + +<p>14x14 mm, 0.5 mm pitch.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>143 balls Wafer Level Chip-Size Package (WLCSP)</h3> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/WLCSP">Wikipedia article</a></li> +</ul> + +<p><b>Not</b> proven in production. Probably faulty, needs at least a review.</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>48 leads Low Profile Quad Flat Package (LQFP)</h3> + +<p>7x7 mm, 0.5 mm pitch.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>64 leads Low Profile Quad Flat Package (LQFP)</h3> + +<p>10x10 mm, 0.5 mm pitch.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>132 balls chip sized Ball Grid Array (BGA) for Lattice MachXO2 series FPGAs</h3> + +<p>8x8 mm, 0.5 mm pitch.</p> + +<p><b>Note</b> that this package has extra non-connected invisible 0.0x0.0 sized pads, in the middle, named NC1-NC7. That facilitates allowing csBGA 132 and TQFP 144 packages to be used with the same device.</p> + +<p><b>Note</b> that this package extra annotation in the Docu layer, showing which balls form together pin pairs in the FPGA pin assignment.</p> + +<ul> + <li>Lattice <a href="http://www.latticesemi.com/~/media/Documents/DataSheets/PackageDiagrams.pdf">Package Diagrams</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>132 balls chip sized Ball Grid Array (BGA) for Lattice iCE40 series FPGAs</h3> + +<p>8x8 mm, 0.5 mm pitch.</p> + +<ul> + <li>Lattice <a href="http://www.latticesemi.com/~/media/Documents/DataSheets/PackageDiagrams.pdf">Package Diagrams</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>QFN 32-Pin package w/ Thermal Pad</h3> +<p><b>Note: Unproven!</b> +<p><b>Note</b> that this package has two "phantom" pad in the middle of it, i.e. a pads whose size is 0.00x0.00 mm, and who are named as NC (not connected). This avoids us from having two different ERP symbols.</p> +<p>Copied from SparkFun-DigitalIC.lbr</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>Name +>Value + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +* + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +* +>NAME +>VALUE + + +<p> +SOIC-16 package, narrow +</p> +<p> +10 mm long, 6 mm wide. +150 mil (1.27 mm) pin spacing, 0.65 mm pad width, 1.75 mm pad length. +</p> +<p> +JEDEC MS-012 +</p> +<p> +Not reviewed +</p> +<p> +<a href="http://grabcad.com/library/soic-package-narrow-8-10-14-and-16-pins-1">Possible step model</a> +</p> + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>44-pin TGFP, 0.8 mm pitch, 10*10 mm body</h3> +<p>Package drawn from <a href="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf">Datasheet</a> pages 154 and 155. +</p> +<p> +Not reviewed +</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>Name +>Value + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver</h3> + +<ul> + <li><a href="http://media.digikey.com/pdf/Data%20Sheets/SMSC/LAN8720.pdf">Datasheet</a></li> +</ul> + +<p>TODO (perhaps): Replace with a more generic Ethernet PHY symbol</p> + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F-series MCU GPIO port A.</h3> + +<p>This port appears to be available, with all pins exposed, throughout the STM32F-series, from STM32F030 to STM32F439. The TSSOP20 package of the STM32F030 is an exception, exposing only PA0–PA7, PA9–PA10, PA13, and PA14. The alternate functions vary from model to model.</p> + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>STM32F-series MCU GPIO port B.</h3> + +<p>This port appears to be available, with at least some pins exposed, throughout the STM32F-series, from STM32F030 to STM32F439. The alternate functions vary from model to model. The most commonly exposed pin is PB1, followed by PB0 and PB3–PB7, and then PB2 and PB8.</p> + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>STM32F-series MCU GPIO port C.</h3> + +<p>This port appears to be available, with at least some pins exposed, throughout most of the STM32F-series, from STM32F030 to STM32F439. The alternate functions vary from model to model. In the lowest pin-count packages the port is not exposed. The most commonly exposed pins are PC13–PC15.</p> + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>STM32F-series MCU GPIO port D.</h3> + +<p>This port appears to be available, with at least one pin (PD2) exposed, throughout most of the STM32F-series, from STM32F030 to STM32F439. For example, STM32F050 does not have this port at all, and STM32F030 exposes PD2 in the largest LQPF64 package. The alternate functions vary from model to model. In the lowest pin-count packages the port is not exposed. </p> + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU GPIO port E.</h3> + +<p>This port is available only in the higher end models of the STM32F-series. The alternate functions vary from model to model.</p> + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU power pads, version 2.</h3> + +<p>This version has PDR_ON and BYPASS_REG pins.</p> + + + + + + + + + +>NAME + + + + + + +<h3>STM32F-series MCU control pads, high-end.</h3> + +<p>This version has OSC_IN and OSC_OUT in PH0 and PH1, respectively, and has VREF+.</p> + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU GPIO port F.</h3> + +<p>This port appears to be available throughout most of the STM32F-series, from STM32F030 to STM32F439. The alternate functions vary from model to model. In the lowest pin-count packages the port is not exposed. The most commonly exposed pins are <tt>PF0</tt>–<tt>PF1</tt>, which are the external oscillator pins in the low-end devices. In high-end devices the oscillator tends to be connected to <tt>PH0</tt>–<tt>PH1</tt> instead. Consequently, if you have a low-end device that exposes only <tt>PF0</tt>–<tt>PF1</tt> as the oscillator, don't include this symbol but only a control symbol with the oscillator pins there.</p> + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU GPIO port D pin 2 and F pins 4-7.</h3> + +<p>Extra pins available in STM32F051 + LQFP64 package.</p> + + + + + + + + +>NAME + + +<h3>STM32F-series MCU GPIO port G.</h3> + +<p>This port is available only in the higher end models of the STM32F-series. The alternate functions vary from model to model.</p> + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU power pads.</h3> + +<p>This version does not have the PDR_ON or BYPASS_REG pins.</p> + + + + + + + + + +>NAME +>VALUE + + +<h3>STM32F-series MCU control pads, low-end.</h3> + +<p>This version has OSC_IN and OSC_OUT in PF0 and PF1, respectively, and has no VREF+.</p> + + + + + + + + +>NAME + + +<h3>Lattice MachXO2 Embedded Function Block (EFB) signal pins</h3> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/ApplicationNotes/UsingUserFlashMemoryandHardenedControlFunctionsinMachXO2Devices.pdf">Datasheet</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<p>Additional bottom ports for csBGA 132</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<p>Top ports in the csBGA 132 package, in addition to those available in QFN32.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<p>Right ports in the csBGA 132 package, in addition to those available in QFN32.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<p>Left ports in the csBGA 132 package, in addition to those available in QFN32.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + + + + + +csBGA132 PL 256/640/... + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> + +<p>Top ports in the csBGA 132 package, in addition to those available in 256.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> + +<p>Left ports in the csBGA 132 package, in addition to those available in 256.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> + +<p>Right ports in the csBGA 132 package, in addition to those available in 256.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> + +<p>Bottom ports in the csBGA 132 package, in addition to those available in 256.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Top ports in the csBGA 132 package, in addition to those available in 640.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Left ports in the csBGA 132 package, in addition to those available in 640.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Right ports in the csBGA 132 package, in addition to those available in 640.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Bottom ports in the csBGA 132 package, in addition to those available in 640.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + + + +<h3>Lattice MachXO2 common power pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>Lattice MachXO2 common power pins for QFN32 package</h3> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + +>NAME +>VALUE + + + + + +Arduino A0 +ETH RMII_REF_CLK +ETH RMII_MDIO +Arduino D6 +Arduino A2 +Arduino A3 +Arduino D12 / SPI MISO +ETH RMII_CRS_DV +MCO +Arduino D1 / TX +Arduino D0 / RX +Arduino D3 / CTS +Arduino D4 / RTS +JTMS / SWDIO +JTCK / SWCLK +JTDI / Arduino D10 / SPI SS + + +<h3>ELL-i functions for STM32F Port A</h3> + +<p>STM32F051/030 64-pin TQFP version</p> + + + +Arduino A0 +ENC28J60 Interrupt +Arduino A1 +Arduino D6 +Arduino A2 +Arduino A3 +D12 / SPI1_MISO +MCO +Arduino D1 / TX +Arduino D0 / RX +Arduino D3 / CTS +Arduino D4 / RTS +SWDIO +SWCLK +Arduino D10 + + + + + +Arduino D9 (PWM) +Arduino D5 (PWM) +-> MachXO2 SN +JTDO / Arduino D13 / SPI1_SCK +JNRST / JTAGENB +Arduino D11 (PWM) / SPI1_MOSI +Arduino A5 / I2C_SCL +FMC_NL/NADV +Arduino D7 +Arduino A4 / I2C_SDA +ELL-i I2C2_SCL +ELL-i I2C2 SDA +ELL-i SPI2_SS / CAN2_RX +ELL-i SPI2_SCK / CAN2_TX +ELL-i SPI2_MISO +ELL-i SPI2_MOSI + + +<h3>ELL-i functions for STM32F Port B</h3> + +<p>STM32F051/030 64-pin TQFP version</p> + + + +Arduino D9 (PWM) +Arduino D5 (PWM) +-> MachXO2 SN* +Arduino D13 / SPI_SCK +-> MachXO2 JTAGENB +Arduino D11 (PWM) / SPI_MOSI +Arduino A5 / I2C_SCL +Arduino D8 +Arduino D7 +ARduino A4 / I2C_SDA +ELL-i I2C2_SCL +ELL-i I2C2 SDA +ELL-i SPI2_SS / CAN2_RX +ELL-i SPI2_SCK / CAN2_TX +ELL-i SPI2_MISO +ELL-i SPI2_MOSI + + + + + +FMC_SNDWE +ETH MDC +FMC_SNDE0 +FMC_SDCKE0 +ETH RMII_RXD0 +ETH RMII_RXD1 +ELL-i LVSD 6T +ELL-i LVDS 6C + + +ELL-i USART3_TX +ELL-i USART3_RX +-> MachXO2 CSSPIN +TAMP1 +OSC32_IN +OSC32_OUT +-> MachXO2 PROGRAMN +-> MachXO2 JTDI + + +<h3>ELL-i functions for STM32F Port C</h3> + +<p>STM32F051/030 64-pin TQFP version</p> + + + +ELL-i LVDS 3T +ELL-i LVDS 3C +ELL-i LVDS 4T +ELL-i LVDS 4C +ELL-i LVDS 5T +ELL-i LVDS 5C +ELL-i LVDS 6T +ELL-i LVDS 6C + + +ELL-i USART3_TX (GPIO) +ELL-i USART3_RX (GPIO) +-> MachXO2CSSPIN +TAMP1 +OSC32_IN +OSC32_OUT +-> Mach XO2 PROGRAMN +-> Mach XO2 JTDI + + + + + +FMC_D2 +FMC_D3 +FMC_CLK +FMC_NOE +FMC_NWE +FMC_NWAIT +FMC_NE1 +FMC_D13 +FMC_D14 +FMC_D15 +FMC_A16 +FMC_A17 +FMC_A18 +FMC_D0 +FMC_D1 +Arduino D2 + + + + + +FMC_NBL0 +FMC_NBL1 +FMC_A23 +FMC_A19 +FMC_A20 +FMC_A21 +FMC_A22 +FMC_D4 +FMC_D5 +FMC_D6 +FMC_D7 +FMC_D8 +FMC_D9 +FMC_D10 +FMC_D11 +FMC_D12 + + + + + +FMC_A0 +FMC_A1 +FMC_A2 +FMC_A3 +FMC_A4 +FMC_A5 + + + + + +FMC_SNDRAS +FMC_A6 +FMC_A7 +FMC_A8 +FMC_A9 +Arduino A1 +ELL-i LVDS 2T +ELL-i LVDS 1C +ELL-i LVDS 1T +ELL-i LVDS 2C + + + + + +FMC_A10 +FMC_A11 +FMC_A12 +FMC_A13 +FMC_A14 +FMC_A15 + + +FMC_SDCLK +FMC_NE2 +FMC_NE3 +ETH RMII_TXEN +FMC_NE4 +ETH RMII_TXD0 +ETH RMII_TXD1 +Arduino D8 +ELL-i LVDS 5T +FMC_SNDCAS + + +<h3>Lattice MachXO2 common I/O pins for 256</h3> + +<p>Generic pins available in the QFN32 package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +>NAME + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Ports in the TQFP 144 package for MachXO2 1200, in addition to those available in csBGA 132 package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + +TQFP144- +only pins + + + + + + + + +TQFP144- +only pins + + + +<h3>ELL-i I/O pins for Lattice MachXO2</h3> + +<p>Generic pins in the QFN32 package.</p> + + + +LVDS 3T +LVDS 3C +LVDS 1T +LVDS 1C +LVDS 2T +LVDS 2C +MCO +Arduino D8 + + +<h3>ELL-i I/O pins for Lattice MachXO2</h3> + +<p>The "QFN32 package" pins for ELL-i when TQFP144 package is used.</p> + + + +DDR2 TBD +DDR2 TBD +Memory CLK +Memory NE1 +Arduino D5 / JNRST +Arduino D6 +DDR2 CLK TBD +DDR2 CLK TBD + + + + + +Memory AD2 +Memory AD3 +Memory AD4 +Memory AD5 +Memory AD6 +Memory AD7 +Memory AD14 +Memory AD15 +Memory A18 +Memory A19 +DDR2 TBD +DDR2 TBD + + + + + +Memory AD8 +Memory AD9 +Memory AD16 +Memory AD17 +DDR2 TBD +DDR2 TBD + + + + + +Memory AD0 +Memory AD1 +Memory AD10 +Memory AD11 +DDR2 TBD + + + + + +USART3_TX +USART3_RX +Memory A22 +Memory A23 + + + + + +Memory A21 +Memory NL/NADV +Arduino D7 +Arduino D9 +SPI2_SS / CAN2_RX +SPI2_SCK / CAN2_TX + + + + + +Memory NBL0 +Memory NBL1 +Memory NOE +Memory NWE +Arduino D0 +Arduino D1 +SPI2 MISO +SPI2 MOSI + + + + + +LVDS 1T +LVDS 1C +DDR2 TBD + + + + + +Memory AD12 +Memory AD13 +DDR2 CLK TBD +DDR2 CLK TBD + + + + + +DDR2 DQn +DDR2 DQn +DDR2 DQn +DDR2 DQn +DDR2 DQn +DDR2 DQn +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR + + + + + +DDR2 DQ0 +DDR2 DQ0 +DDR2 DQS0N check! +DDR2 DQS0 check! +DDR2 ADDR +DDR2 ADDR + + + + + +DDR2 DQ0 +DDR2 DQ0 +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR + + + + + +LVDS 6T +LVDS 6C +MCO +Arduino D2 + + + + + +LVDS 2T +LVDS 2T +LVDS 3T +LVDS 3C +LVDS 5T +LVDS 5C + + + + + +Arduino D8 +Memory NWAIT +I2C2 SCL +I2C2 SDA +LVDS 4T +LVDS 4B + + +<h3>ELL-i functions for STM32F Porta D and F</h3> + +<p>STM32F051/030 64-pin TQFP version</p> + + + +Arduino D2 +ELL-i LVDS 1T +ELL-i LVDS 1C +ELL-i LVDS 2T +ELL-i LVDS 2C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +Quad 2:1 high-speed CMOS TTL-compatible multiplexer +<h3>Description</h3> +<p> +The Fairchild Switch FST3257 is a quad 2:1 high-speed CMOS TTL-compatible multiplexer / demultiplexer bus +switch. +</p> +<p> +The low on resistance of the switch allows +inputs to be connected to outputs without adding +propagation delay or generating additional ground +bounce noise. +</p> +<p> +When /OE is LOW, the select pin connects the A port to +the selected B port output. When /OE is HIGH, the +switch is OPEN and a high-impedance state exists +between the two ports. +</p> +<p> +<a HREF="www.fairchildsemi.com/ds/FS/FST3257.pdf"> Datasheet </a> +</p> +<p> +Not reviewed +</p> + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>STM32F-series MCU control pads</b> + + + + + + +>NAME +>VALUE + + + + + +<b>STM32F1-series MCU Power pads</b> + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>ENC424J600</h3> +<p> +The ENC424J600 and ENC624J600 are stand-alone, +Fast Ethernet controllers with an industry standard +Serial Peripheral Interface (SPI) or a flexible parallel +interface. They are designed to serve as an Ethernet +network interface for any microcontroller equipped with +SPI or a standard parallel port. +</p> +<p> +This is 44 pin version of device, <a href="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf">Datasheet</a> +</p> +<p> +Not reviewed +</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + +<h3>Small Footprint RMII 10/100 Ethernet Transceiver</h3> + +<ul> + <li><a href="http://media.digikey.com/pdf/Data%20Sheets/SMSC/LAN8720.pdf">Datasheet</a></li> + <li>Mouser: <a href="">886-LAN8720AI-CP</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F427 / 429 in LQFP144 or WLCSP143 package.</h3> + +<p>STM32F4-series Cortex-M4 microcontroller in a 144 or 143 lead package.</p> + +<ul> + <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00071990.pdf">Datasheet (DM00071990.pdf)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F427 / 429 in LQFP100 package.</h3> + +<p>STM32F4-series Cortex-M4 microcontroller in a 100 lead package.</p> + +<ul> + <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00071990.pdf">Datasheet (DM00071990.pdf)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F051 in LQPF48 package.</h3> + +<p>STM32F0-series Cortex-M0 microcontroller in a 48 lead package.</p> + +<ul> + <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00039193.pdf">Datasheet</a> (DM00039193.pdf)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F051 in LQPF64 package.</h3> + +<p>STM32F0-series Cortex-M0 microcontroller in 64 lead package.</p> + +<ul> + <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00039193.pdf">Datasheet</a> (DM00039193.pdf)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3> MachXO2-256 in csBGA132 or TQFP144 package.</h3> + +<p>Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3> MachXO2-1200 in csBGA132 or TQFP144 package.</h3> + +<p>Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3> MachXO2-2000 in csBGA132 or TQFP144 package.</h3> + +<p>Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F427 / 429 ELL-i functions.</h3> + +<p>This device contains a number of pseudo-symbols, meant to be used with a real STM32F42x MCU. The pseudo-symbols list the ELL-i project functions for the STM32F4 MCU pins.</p> + +<ul> + <li>TBD (a link to the relevant design document)</li>. +</ul> + + + + + + + + + + + + + + + + + + +<h3>MachXO2 2000 ELL-i functions.</h3> + +<p>This device contains a number of pseudo-symbols, meant to be used with a real MachXO2-2000 FPGA. The pseudo-symbols list the ELL-i project functions for the 132/144 pins FPGA package.</p> + +<ul> + <li>TBD (a link to the relevant design document)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>MachXO2-256 in 32-pin QFN package.</h3> + +<p>Lattice MachXO2-series FPGA in a 32-pin QFN package, 0.5 mm pitch.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F051/030 ELL-i functions.</h3> + +<p>This device contains a number of pseudo-symbols, meant to be used with a real STM32F0 MCU. The pseudo-symbols list the ELL-i project functions for the STM32F0 MCU pins in a 64-pin package.</p> + +<ul> + <li>TBD (a link to the relevant design document)</li>. +</ul> + + + + + + + + + + + + + + + +Stand-Alone 10/100 Ethernet Controller + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>MachXO2 256 QFN32 ELL-i functions.</h3> + +<p>This device contains a pseudo-symbols, meant to be used with a corresponding MachXO2-256 FPGA device. The pseudo-symbols list the ELL-i project extra functions for the 32 pins FPGA package. Most of the functions in the QFN32 package are predefined by Lattice, though overrideable by a user design.</p> + +<ul> + <li>TBD (a link to the relevant design document)</li>. +</ul> + + + + + + + + + + + + +<p> +Quad 2:1 Multiplexer / Demultiplexer Bus Switch +</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +STM32F103 Medium Density 64pin LQFP +<br><br> +<a href="http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00161566.pdf">Datasheet</a> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +STM32F103 Medium Density 64pin LQFP +<br><br> +<a href="http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00161566.pdf">Datasheet</a> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>ENC424J600</h3> +<p> +The ENC424J600 and ENC624J600 are stand-alone, +Fast Ethernet controllers with an industry standard +Serial Peripheral Interface (SPI) or a flexible parallel +interface. They are designed to serve as an Ethernet +network interface for any microcontroller equipped with +SPI or a standard parallel port +</p> +<p> Not reviewed. <a href ="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf">Datasheet</a> +</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Since Version 6.2.2 text objects can contain more than one line, +which will not be processed correctly with this version. + + + diff --git a/eagle/FPGA disk controller/bmowdisk.b#1 b/eagle/FPGA disk controller/bmowdisk.b#1 new file mode 100644 index 0000000..b8a2cf7 --- /dev/null +++ b/eagle/FPGA disk controller/bmowdisk.b#1 @@ -0,0 +1,4034 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +U1 +U2 +U3 +U4 +U5 +U6 +U7 +CON1 +D1 +R1 +J1 +J2 +J3 +J4 +MOSI +MISO +SCLK +CS +3V3 +TDO +GND +TDI +TCK +TMS +R2 +R3 +R4 +R5 +R6 +1 +25 +C13 +C8 +C14 +C15 +C9 +C16 +C10 +C17 +C11 +C18 +C12 +C1 +C2 +C3 +C4 +C5 +C6 +L1 +C20 +C19 +C7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> CC v3.0 Share-Alike You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. 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footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> CC v3.0 Share-Alike You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. 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If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> CC v3.0 Share-Alike You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage. + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + +<b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie fĂĽr +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab. +<b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. 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Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115). + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE + + + + + +>VALUE + + + + + +<b>SUPPLY SYMBOL</b> + + + + + + + + + + + + +<b>SUPPLY SYMBOL</b> + + + + + + + + + + + + + + +<b>Micrel Voltage Regulator</b><p> +Micrel Semiconductor, Inc.<br> +http://www.micrel.com<p> +<author>Created by librarian@cadsoft.de</author> + + +<b>Small Outline Transistor</b> + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + +<b>VOLTAGE REGULATOR</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>CHICAGO MINIATURE LAMP, INC.</b><p> +7022X Series SMT LEDs 1206 Package Size + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + +<B>LED</B><p> +5 mm, square, Siemens + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<B>LED</B><p> +2 x 5 mm, rectangle + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + +<B>LED</B><p> +3 mm, round + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<B>LED</B><p> +5 mm, round + + + + + + + + + + + +>NAME +>VALUE + + +<B>LED</B><p> +1 mm, round, Siemens + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<B>LED BLOCK</B><p> +1 LED, Siemens + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<b>LED HOLDER</b><p> +Siemens + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>LED HOLDER</b><p> +Siemens + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>LED HOLDER</b><p> +Siemens + + + + + + + + + + + + + + + + + +A+ +K- +>NAME +>VALUE + + + + + +<b>LED HOLDER</b><p> +Siemens + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE ++ +- + + +<B>IR LED</B><p> +infrared emitting diode, Infineon +TO-18, lead spacing 2.54 mm, cathode marking<p> +Inifineon + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<B>IR LED</B><p> +infrared emitting diode, Infineon +TO-18, lead spacing 2.54 mm, cathode marking<p> +Inifineon + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<B>LED</B><p> +rectangle, 5.7 x 3.2 mm + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<B>IR LED</B><p> +IR transmitter Siemens + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>TOPLED® High-optical Power LED (HOP)</b><p> +Source: http://www.osram.convergy.de/ ... ls_t675.pdf + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +A +C + + + + + + + +<b>BLUE LINETM Hyper Mini TOPLED® Hyper-Bright LED</b><p> +Source: http://www.osram.convergy.de/ ... LB M676.pdf + + + + + + + + + + + + + + +A +C +>NAME +>VALUE + + + + + + + +<b>Super SIDELED® High-Current LED</b><p> +LG A672, LP A672 <br> +Source: http://www.osram.convergy.de/ ... LG_LP_A672.pdf (2004.05.13) + + + + + + + + + + + + + + + + + + + +C +A +>NAME +>VALUE + + + + + + + +<b>SmartLEDTM Hyper-Bright LED</b><p> +Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY L896.pdf + + + + + + + + +>NAME +>VALUE + + + + + +<b>Hyper TOPLED® RG Hyper-Bright LED</b><p> +Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY T776.pdf + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +A +C + + + + + + + + + + +<b>Hyper Micro SIDELED®</b><p> +Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY Y876.pdf + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + +<b>Power TOPLED®</b><p> +Source: http://www.osram.convergy.de/ ... LA_LO_LA_LY E67B.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +C +A +C +C + + + + + + + + + + + +<b>Hyper CHIPLED Hyper-Bright LED</b><p> +LB Q993<br> +Source: http://www.osram.convergy.de/ ... Lb_q993.pdf + + + + +>NAME +>VALUE + + + + + + + +<b>Hyper CHIPLED Hyper-Bright LED</b><p> +LB R99A<br> +Source: http://www.osram.convergy.de/ ... lb_r99a.pdf + + + + +>NAME +>VALUE + + + + + + + +<b>Mini TOPLED Santana®</b><p> +Source: http://www.osram.convergy.de/ ... LG M470.pdf + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + +<b>CHIPLED</b><p> +Source: http://www.osram.convergy.de/ ... LG_R971.pdf + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + +<b>CHIPLED</b><p> +Source: http://www.osram.convergy.de/ ... LG_LY N971.pdf + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +<b>CHIPLED</b><p> +Source: http://www.osram.convergy.de/ ... LG_LY Q971.pdf + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +<b>CHIPLED-0603</b><p> +Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603<br> +Package able to withstand TTW-soldering heat<br> +Package suitable for TTW-soldering<br> +Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + +<b>SmartLED TTW</b><p> +Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603<br> +Package able to withstand TTW-soldering heat<br> +Package suitable for TTW-soldering<br> +Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + +<b>Lumileds Lighting. LUXEON®</b> with cool pad<p> +Source: K2.pdf + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Lumileds Lighting. LUXEON®</b> without cool pad<p> +Source: K2.pdf + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + +<B>LED</B><p> +10 mm, round + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>SURFACE MOUNT LED LAMP</b> 3.5x2.8mm<p> +Source: http://www.kingbright.com/manager/upload/pdf/KA-3528ASYC(Ver1189474662.1) + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + +<b>LED</b><p> +<u>OSRAM</u>:<br> + +- <u>CHIPLED</u><br> +LG R971, LG N971, LY N971, LG Q971, LY Q971, LO R971, LY R971 +LH N974, LH R974<br> +LS Q976, LO Q976, LY Q976<br> +LO Q996<br> + +- <u>Hyper CHIPLED</u><br> +LW Q18S<br> +LB Q993, LB Q99A, LB R99A<br> + +- <u>SideLED</u><br> +LS A670, LO A670, LY A670, LG A670, LP A670<br> +LB A673, LV A673, LT A673, LW A673<br> +LH A674<br> +LY A675<br> +LS A676, LA A676, LO A676, LY A676, LW A676<br> +LS A679, LY A679, LG A679<br> + +- <u>Hyper Micro SIDELED®</u><br> +LS Y876, LA Y876, LO Y876, LY Y876<br> +LT Y87S<br> + +- <u>SmartLED</u><br> +LW L88C, LW L88S<br> +LB L89C, LB L89S, LG L890<br> +LS L89K, LO L89K, LY L89K<br> +LS L896, LA L896, LO L896, LY L896<br> + +- <u>TOPLED</u><br> +LS T670, LO T670, LY T670, LG T670, LP T670<br> +LSG T670, LSP T670, LSY T670, LOP T670, LYG T670<br> +LG T671, LOG T671, LSG T671<br> +LB T673, LV T673, LT T673, LW T673<br> +LH T674<br> +LS T676, LA T676, LO T676, LY T676, LB T676, LH T676, LSB T676, LW T676<br> +LB T67C, LV T67C, LT T67C, LS T67K, LO T67K, LY T67K, LW E67C<br> +LS E67B, LA E67B, LO E67B, LY E67B, LB E67C, LV E67C, LT E67C<br> +LW T67C<br> +LS T679, LY T679, LG T679<br> +LS T770, LO T770, LY T770, LG T770, LP T770<br> +LB T773, LV T773, LT T773, LW T773<br> +LH T774<br> +LS E675, LA E675, LY E675, LS T675<br> +LS T776, LA T776, LO T776, LY T776, LB T776<br> +LHGB T686<br> +LT T68C, LB T68C<br> + +- <u>Hyper Mini TOPLED®</u><br> +LB M676<br> + +- <u>Mini TOPLED Santana®</u><br> +LG M470<br> +LS M47K, LO M47K, LY M47K +<p> +Source: http://www.osram.convergy.de<p> + +<u>LUXEON:</u><br> +- <u>LUMILED®</u><br> +LXK2-PW12-R00, LXK2-PW12-S00, LXK2-PW14-U00, LXK2-PW14-V00<br> +LXK2-PM12-R00, LXK2-PM12-S00, LXK2-PM14-U00<br> +LXK2-PE12-Q00, LXK2-PE12-R00, LXK2-PE12-S00, LXK2-PE14-T00, LXK2-PE14-U00<br> +LXK2-PB12-K00, LXK2-PB12-L00, LXK2-PB12-M00, LXK2-PB14-N00, LXK2-PB14-P00, LXK2-PB14-Q00<br> +LXK2-PR12-L00, LXK2-PR12-M00, LXK2-PR14-Q00, LXK2-PR14-R00<br> +LXK2-PD12-Q00, LXK2-PD12-R00, LXK2-PD12-S00<br> +LXK2-PH12-R00, LXK2-PH12-S00<br> +LXK2-PL12-P00, LXK2-PL12-Q00, LXK2-PL12-R00 +<p> +Source: www.luxeon.com<p> + +<u>KINGBRIGHT:</U><p> +KA-3528ASYC<br> +Source: www.kingbright.com + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>SparkFun Electronics' preferred foot prints</h3> +In this library you'll find connectors and sockets- basically anything that can be plugged into or onto.<br><br> +We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> CC v3.0 Share-Alike You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage. + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +2mm SMD side-entry connector. tDocu layer indicates the actual physical plastic housing. +/- indicate SparkFun standard batteries and wiring. + + + + + + + + + + + + + +>Name +>Value ++ +- + + + + + + + + + + + + + + + + + + + + + + + + + +>Name +>Value + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + +This footprint was designed to help hold the alignment of a through-hole component (i.e. 6-pin header) while soldering it into place. +You may notice that each hole has been shifted either up or down by 0.005 of an inch from it's more standard position (which is a perfectly straight line). +This slight alteration caused the pins (the squares in the middle) to touch the edges of the holes. Because they are alternating, it causes a "brace" +to hold the component in place. 0.005 has proven to be the perfect amount of "off-center" position when using our standard breakaway headers. +Although looks a little odd when you look at the bare footprint, once you have a header in there, the alteration is very hard to notice. Also, +if you push a header all the way into place, it is covered up entirely on the bottom side. This idea of altering the position of holes to aid alignment +will be further integrated into the Sparkfun Library for other footprints. It can help hold any component with 3 or more connection pins. + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +>Name +>Value ++ +- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + +>Name +>Value ++ +- + + +<H3>JST-2-PTH-KIT</h3> +2-Pin JST, through-hole connector<br> +<br> +<b>Warning:</b> This is the KIT version of this package. This package has a smaller diameter top stop mask, which doesn't cover the diameter of the pad. This means only the bottom side of the pads' copper will be exposed. You'll only be able to solder to the bottom side. + + + + + + + + + +>Name +>Value ++ +- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + +Standard 2-pin 0.1" header. Use with <br> +- straight break away headers ( PRT-00116)<br> +- right angle break away headers (PRT-00553)<br> +- swiss pins (PRT-00743)<br> +- machine pins (PRT-00117)<br> +- female headers (PRT-00115)<br><br> + + Molex polarized connector foot print use with: PRT-08233 with associated crimp pins and housings.<br><br> + +2.54_SCREWTERM for use with PRT-10571.<br><br> + +3.5mm Screw Terminal footprints for PRT-08084<br><br> + +5mm Screw Terminal footprints for use with PRT-08433 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Generated from <b>retro-usb.sch</b><p> +by exp-lbrs.ulp + + +<b>PIN HEADER</b> + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + +>NAME +>VALUE + + + + + + +>NAME +>VALUE + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + +>VALUE +>NAME + + + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>SparkFun Electronics' preferred foot prints</h3> +In this library you'll find resistors, capacitors, inductors, test points, jumper pads, etc.<br><br> +We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> CC v3.0 Share-Alike You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage. + + + + + + + + + + +>Name +>Value + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + +>Name +>Value + + + + + + + + + + +>Name +>Value + + +<b>CAPACITOR</b><p> +chip + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +1007 (2518 metric) package + + + + + + + + +>NAME +>VALUE + + + + + + + + + + +>Name +>Value + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +>NAME +>VALUE + + + + + + + + + + + + +1.3x1.3mm 1.7mm between. Fits Sumida CDRH2D09, CDRH2D18 inductor + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + +>Name +>Value + + + + + + + + + + + + + + + + + +>Name +>Value + + +For Coiltronics/Cooper DR1030 series inductors + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + +1W Resistor, 0.6" wide<p> + +Yageo CFR series <a href="http://www.yageo.com/pdf/yageo/Leaded-R_CFR_2008.pdf">http://www.yageo.com/pdf/yageo/Leaded-R_CFR_2008.pdf</a> + + + + + + +>Name +>Value + + + + +>Value +>Name + + + + + + + + + + + + + +>NAME +>VALUE + + +Footprint for Bourns SDR0403 family inductors + + + + +>VALUE +>NAME + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +<b>Inductors</b><p> +Basic Inductor/Choke - 0603 and 1206. Footprints are not proven and vary greatly between part numbers.<br> +SRN6045- 33uH, 20% 1.4A<BR> +SDR0403-560KL - 56uH, 10%, 500mA RMS/740mA peak + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Since Version 6.2.2 text objects can contain more than one line, +which will not be processed correctly with this version. + + + diff --git a/eagle/FPGA disk controller/bmowdisk.scr b/eagle/FPGA disk controller/bmowdisk.scr new file mode 100644 index 0000000..263ad6f --- /dev/null +++ b/eagle/FPGA disk controller/bmowdisk.scr @@ -0,0 +1,7576 @@ +OPEN '~dummy~.lbr'; +CLOSE; +OPEN 'C:/Users/chamberlin/Documents/Liron/bmowdisk/bmowdisk/bmowdisk.lbr'; +Layer 1 Top; +Layer 16 Bottom; +Layer 17 Pads; +Layer 18 Vias; +Layer 19 Unrouted; +Layer 20 Dimension; +Layer 21 tPlace; +Layer 22 bPlace; +Layer 23 tOrigins; +Layer 24 bOrigins; +Layer 25 tNames; +Layer 26 bNames; +Layer 27 tValues; +Layer 28 bValues; +Layer 29 tStop; +Layer 30 bStop; +Layer 31 tCream; +Layer 32 bCream; +Layer 33 tFinish; +Layer 34 bFinish; +Layer 35 tGlue; +Layer 36 bGlue; +Layer 37 tTest; +Layer 38 bTest; +Layer 39 tKeepout; +Layer 40 bKeepout; +Layer 41 tRestrict; +Layer 42 bRestrict; +Layer 43 vRestrict; +Layer 44 Drills; +Layer 45 Holes; +Layer 46 Milling; +Layer 47 Measures; +Layer 48 Document; +Layer 49 Reference; +Layer 50 dxf; +Layer 51 tDocu; +Layer 52 bDocu; +Layer 53 tGND_GNDA; +Layer 54 bGND_GNDA; +Layer 56 wert; +Layer 57 tCopper; +Layer 58 bCopper; +Layer 90 Modules; +Layer 91 Nets; +Layer 92 Busses; +Layer 93 Pins; +Layer 94 Symbols; +Layer 95 Names; +Layer 96 Values; +Layer 97 Info; +Layer 98 Guide; +Layer 99 SpiceOrder; +Layer 100 Muster; +Layer 101 Patch_Top; +Layer 102 Vscore; +Layer 103 fp3; +Layer 104 Name; +Layer 105 Beschreib; +Layer 106 BGA-Top; +Layer 107 BD-Top; +Layer 108 fp8; +Layer 109 fp9; +Layer 110 fp0; +Layer 111 111; +Layer 112 tSilk; +Layer 116 Patch_BOT; +Layer 118 Rect_Pads; +Layer 121 _tsilk; +Layer 122 _bsilk; +Layer 123 tTestmark; +Layer 124 bTestmark; +Layer 125 _tNames; +Layer 126 _bNames; +Layer 127 _tValues; +Layer 128 _bValues; +Layer 131 tAdjust; +Layer 132 bAdjust; +Layer 144 Drill_legend; +Layer 151 HeatSink; +Layer 152 _bDocu; +Layer 199 Contour; +Layer 200 200bmp; +Layer 201 201bmp; +Layer 202 202bmp; +Layer 203 203bmp; +Layer 204 204bmp; +Layer 205 205bmp; +Layer 206 206bmp; +Layer 207 207bmp; +Layer 208 208bmp; +Layer 209 209bmp; +Layer 210 210bmp; +Layer 211 211bmp; +Layer 212 212bmp; +Layer 213 213bmp; +Layer 214 214bmp; +Layer 215 215bmp; +Layer 216 216bmp; +Layer 217 217bmp; +Layer 218 218bmp; +Layer 219 219bmp; +Layer 220 220bmp; +Layer 221 221bmp; +Layer 222 222bmp; +Layer 223 223bmp; +Layer 224 224bmp; +Layer 231 Eagle3D_PG1; +Layer 232 Eagle3D_PG2; +Layer 233 Eagle3D_PG3; +Layer 248 Housing; +Layer 249 Edge; +Layer 250 Descript; +Layer 251 SMDround; +Layer 253 Extra; +Layer 254 cooling; +Layer 255 bExtra; +Set Wire_bend 2; +Set Select_factor 0; +Set Undo_log off; +Grid mic 1; +Display All; +DESCRIPTION ''; +DESCRIPTION 'Generated from bmowdisk.sch

\n\ +by exp-lbrs.ulp'; + +Edit '1/6W-RES$1.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (-1550.000000 850.000000) (-1550.000000 -850.000000); +Layer 21; +Wire 203.200000 (-1550.000000 -850.000000) (1550.000000 -850.000000); +Layer 21; +Wire 203.200000 (1550.000000 -850.000000) (1550.000000 850.000000); +Layer 21; +Wire 203.200000 (1550.000000 850.000000) (-1550.000000 850.000000); +Change Drill 762.000000; +Pad 0.000000 Round R0.0 '1' (-2500.000000 0.000000); +Change Drill 762.000000; +Pad 0.000000 Round R0.0 '2' (2500.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 609.600000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1266.200000 955.200000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 812.800000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1423.000000 -428.600000); +DESCRIPTION '1/6W Thru-hole Resistor - *UNPROVEN*'; + +Edit '0402-CAP.PAC'; +GRID mic; +Layer 51; +Wire 152.400000 (-245.000000 224.000000) (245.000000 224.000000); +Layer 51; +Wire 152.400000 (245.000000 -224.000000) (-245.000000 -224.000000); +Layer 39; +Wire 50.800000 (-1473.000000 483.000000) (1473.000000 483.000000); +Layer 39; +Wire 50.800000 (1473.000000 483.000000) (1473.000000 -483.000000); +Layer 39; +Wire 50.800000 (1473.000000 -483.000000) (-1473.000000 -483.000000); +Layer 39; +Wire 50.800000 (-1473.000000 -483.000000) (-1473.000000 483.000000); +Layer 21; +Wire 406.400000 (0.000000 30.500000) (0.000000 -30.500000); +Layer 51; +Rect R0.0 (-554.000000 -304.800000) (-254.000000 295.100000); +Layer 51; +Rect R0.0 (258.800000 -304.800000) (558.800000 295.100000); +Layer 35; +Rect R0.0 (-199.900000 -300.000000) (199.900000 300.000000); +Layer 1; +CHANGE Roundness 0; +SMD 700.000000 900.000000 -0 R0.0 '1' (-650.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 700.000000 900.000000 -0 R0.0 '2' (650.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-889.000000 698.500000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1079.500000 -1143.000000); +DESCRIPTION 'CAPACITOR

\nchip'; + +Edit '0402-RES.PAC'; +GRID mic; +Layer 51; +Wire 152.400000 (-245.000000 224.000000) (245.000000 224.000000); +Layer 51; +Wire 152.400000 (245.000000 -224.000000) (-245.000000 -224.000000); +Layer 39; +Wire 50.800000 (-1473.000000 483.000000) (1473.000000 483.000000); +Layer 39; +Wire 50.800000 (1473.000000 483.000000) (1473.000000 -483.000000); +Layer 39; +Wire 50.800000 (1473.000000 -483.000000) (-1473.000000 -483.000000); +Layer 39; +Wire 50.800000 (-1473.000000 -483.000000) (-1473.000000 483.000000); +Layer 51; +Rect R0.0 (-554.000000 -304.800000) (-254.000000 295.100000); +Layer 51; +Rect R0.0 (258.800000 -304.800000) (558.800000 295.100000); +Layer 35; +Rect R0.0 (-199.900000 -300.000000) (199.900000 300.000000); +Layer 21; +Rect R0.0 (-203.200000 -355.600000) (203.200000 355.600000); +Layer 1; +CHANGE Roundness 0; +SMD 700.000000 900.000000 -0 R0.0 '1' (-650.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 700.000000 900.000000 -0 R0.0 '2' (650.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-889.000000 698.500000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1079.500000 -1143.000000); +DESCRIPTION 'CAPACITOR

\nchip'; + +Edit '0603-CAP.PAC'; +GRID mic; +Layer 39; +Wire 50.800000 (-1473.000000 983.000000) (1473.000000 983.000000); +Layer 39; +Wire 50.800000 (1473.000000 983.000000) (1473.000000 -983.000000); +Layer 39; +Wire 50.800000 (1473.000000 -983.000000) (-1473.000000 -983.000000); +Layer 39; +Wire 50.800000 (-1473.000000 -983.000000) (-1473.000000 983.000000); +Layer 51; +Wire 101.600000 (-356.000000 432.000000) (356.000000 432.000000); +Layer 51; +Wire 101.600000 (-356.000000 -419.000000) (356.000000 -419.000000); +Layer 21; +Wire 558.800000 (0.000000 30.500000) (0.000000 -30.500000); +Layer 51; +Rect R0.0 (-838.200000 -469.900000) (-338.100000 480.100000); +Layer 51; +Rect R0.0 (330.200000 -469.900000) (830.300000 480.100000); +Layer 35; +Rect R0.0 (-199.900000 -300.000000) (199.900000 300.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1100.000000 1000.000000 -0 R0.0 '1' (-850.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1100.000000 1000.000000 -0 R0.0 '2' (850.000000 0.000000); +Layer 25; +CHANGE FONT VECTOR; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-889.000000 762.000000); +Layer 27; +CHANGE FONT VECTOR; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1016.000000 -1143.000000); +DESCRIPTION ''; + +Edit '0603-RES.PAC'; +GRID mic; +Layer 39; +Wire 50.800000 (-1473.000000 983.000000) (1473.000000 983.000000); +Layer 39; +Wire 50.800000 (1473.000000 983.000000) (1473.000000 -983.000000); +Layer 39; +Wire 50.800000 (1473.000000 -983.000000) (-1473.000000 -983.000000); +Layer 39; +Wire 50.800000 (-1473.000000 -983.000000) (-1473.000000 983.000000); +Layer 51; +Wire 101.600000 (-356.000000 432.000000) (356.000000 432.000000); +Layer 51; +Wire 101.600000 (-356.000000 -419.000000) (356.000000 -419.000000); +Layer 51; +Rect R0.0 (-838.200000 -469.900000) (-338.100000 480.100000); +Layer 51; +Rect R0.0 (330.200000 -469.900000) (830.300000 480.100000); +Layer 35; +Rect R0.0 (-199.900000 -300.000000) (199.900000 300.000000); +Layer 21; +Rect R0.0 (-228.600000 -381.000000) (228.600000 381.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1100.000000 1000.000000 -0 R0.0 '1' (-850.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1100.000000 1000.000000 -0 R0.0 '2' (850.000000 0.000000); +Layer 25; +CHANGE FONT VECTOR; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-889.000000 762.000000); +Layer 27; +CHANGE FONT VECTOR; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1016.000000 -1143.000000); +DESCRIPTION ''; + +Edit '0805.PAC'; +GRID mic; +Layer 21; +Wire 152.400000 (-300.000000 600.000000) (300.000000 600.000000); +Layer 21; +Wire 152.400000 (-300.000000 -600.000000) (300.000000 -600.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 1200.000000 -0 R0.0 '1' (-900.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 1200.000000 -0 R0.0 '2' (900.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-762.000000 825.500000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1016.000000 -1397.000000); +DESCRIPTION ''; + +Edit '1206.PAC'; +GRID mic; +Layer 39; +Wire 50.800000 (-2473.000000 983.000000) (2473.000000 983.000000); +Layer 39; +Wire 50.800000 (2473.000000 -983.000000) (-2473.000000 -983.000000); +Layer 39; +Wire 50.800000 (-2473.000000 -983.000000) (-2473.000000 983.000000); +Layer 39; +Wire 50.800000 (2473.000000 983.000000) (2473.000000 -983.000000); +Layer 51; +Wire 101.600000 (-965.000000 787.000000) (965.000000 787.000000); +Layer 51; +Wire 101.600000 (-965.000000 -787.000000) (965.000000 -787.000000); +Layer 51; +Rect R0.0 (-1701.800000 -850.900000) (-951.700000 849.100000); +Layer 51; +Rect R0.0 (951.700000 -849.100000) (1701.800000 850.900000); +Layer 35; +Rect R0.0 (-199.900000 -400.100000) (199.900000 400.100000); +Layer 1; +CHANGE Roundness 0; +SMD 1600.000000 1800.000000 -0 R0.0 '1' (-1400.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1600.000000 1800.000000 -0 R0.0 '2' (1400.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1270.000000 1143.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1397.000000 -1524.000000); +DESCRIPTION ''; + +Edit '1210.PAC'; +GRID mic; +Layer 51; +Wire 127.000000 (-1600.000000 1300.000000) (1600.000000 1300.000000); +Layer 51; +Wire 127.000000 (1600.000000 1300.000000) (1600.000000 -1300.000000); +Layer 51; +Wire 127.000000 (1600.000000 -1300.000000) (-1600.000000 -1300.000000); +Layer 51; +Wire 127.000000 (-1600.000000 -1300.000000) (-1600.000000 1300.000000); +Layer 21; +Wire 203.200000 (-1600.000000 1300.000000) (1600.000000 1300.000000); +Layer 21; +Wire 203.200000 (-1600.000000 -1300.000000) (1600.000000 -1300.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1200.000000 2000.000000 -0 R0.0 '1' (-1600.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1200.000000 2000.000000 -0 R0.0 '2' (1600.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-800.000000 500.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-900.000000 -700.000000); +DESCRIPTION ''; + +Edit 'AXIAL-0.3.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (-2540.000000 762.000000) (2540.000000 762.000000); +Layer 21; +Wire 203.200000 (2540.000000 762.000000) (2540.000000 0.000000); +Layer 21; +Wire 203.200000 (2540.000000 0.000000) (2540.000000 -762.000000); +Layer 21; +Wire 203.200000 (2540.000000 -762.000000) (-2540.000000 -762.000000); +Layer 21; +Wire 203.200000 (-2540.000000 -762.000000) (-2540.000000 0.000000); +Layer 21; +Wire 203.200000 (-2540.000000 0.000000) (-2540.000000 762.000000); +Layer 21; +Wire 203.200000 (2540.000000 0.000000) (2794.000000 0.000000); +Layer 21; +Wire 203.200000 (-2540.000000 0.000000) (-2794.000000 0.000000); +Change Drill 900.000000; +Pad 1879.600000 Round R0.0 'P$1' (-3810.000000 0.000000); +Change Drill 900.000000; +Pad 1879.600000 Round R0.0 'P$2' (3810.000000 0.000000); +Layer 25; +CHANGE FONT VECTOR; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-2540.000000 1270.000000); +Layer 21; +CHANGE FONT VECTOR; +Change Size 1016.000000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-2032.000000 -381.000000); +DESCRIPTION ''; + +Edit 'AXIAL-0.3-KIT.PAC'; +GRID mic; +Layer 21; +Wire 254.000000 (-2540.000000 1270.000000) (2540.000000 1270.000000); +Layer 21; +Wire 254.000000 (2540.000000 1270.000000) (2540.000000 0.000000); +Layer 21; +Wire 254.000000 (2540.000000 0.000000) (2540.000000 -1270.000000); +Layer 21; +Wire 254.000000 (2540.000000 -1270.000000) (-2540.000000 -1270.000000); +Layer 21; +Wire 254.000000 (-2540.000000 -1270.000000) (-2540.000000 0.000000); +Layer 21; +Wire 254.000000 (-2540.000000 0.000000) (-2540.000000 1270.000000); +Layer 21; +Wire 254.000000 (2540.000000 0.000000) (2794.000000 0.000000); +Layer 21; +Wire 254.000000 (-2540.000000 0.000000) (-2794.000000 0.000000); +Change Drill 1016.000000; +Pad 2032.000000 Round R0.0 NOSTOP 'P$1' (-3810.000000 0.000000); +Change Drill 1016.000000; +Pad 2032.000000 Round R0.0 NOSTOP 'P$2' (3810.000000 0.000000); +Layer 25; +CHANGE FONT VECTOR; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-2540.000000 1270.000000); +Layer 21; +CHANGE FONT VECTOR; +Change Size 1270.000000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-2159.000000 -762.000000); +Layer 30; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 127.000000 (3820.100000 -944.900000) -90.000000 (2865.200000 -15.200000) -90.011749 (3817.600000 960.200000) -90.000000 (4767.600000 -17.800000) -90.024193 (3820.100000 -944.900000) ; +Layer 29; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 127.000000 (3817.600000 -436.900000) -90.012891 (3373.100000 -12.700000) -90.000000 (3817.600000 454.600000) -90.000000 (4259.500000 -2.500000) -90.012967 (3817.600000 -436.900000) ; +Layer 30; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 127.000000 (-3807.500000 -952.500000) -90.000000 (-4762.400000 -22.800000) -90.011749 (-3810.000000 952.600000) -90.000000 (-2860.000000 -25.400000) -90.024193 (-3807.500000 -952.500000) ; +Layer 29; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 127.000000 (-3810.000000 -444.500000) -90.012891 (-4254.500000 -20.300000) -90.000000 (-3810.000000 447.000000) -90.000000 (-3368.100000 -10.100000) -90.012967 (-3810.000000 -444.500000) ; +DESCRIPTION ''; + +Edit 'AXIAL-0.4.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (-3150.000000 -1200.000000) (-3150.000000 1200.000000); +Layer 21; +Wire 203.200000 (-3150.000000 1200.000000) (3150.000000 1200.000000); +Layer 21; +Wire 203.200000 (3150.000000 1200.000000) (3150.000000 -1200.000000); +Layer 21; +Wire 203.200000 (3150.000000 -1200.000000) (-3150.000000 -1200.000000); +Change Drill 900.000000; +Pad 1879.600000 Round R0.0 'P$1' (-5080.000000 0.000000); +Change Drill 900.000000; +Pad 1879.600000 Round R0.0 'P$2' (5080.000000 0.000000); +Layer 25; +CHANGE FONT VECTOR; +Change Size 812.800000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-3175.000000 1905.000000); +Layer 21; +CHANGE FONT VECTOR; +Change Size 812.800000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-2286.000000 -381.000000); +DESCRIPTION '1/4W Resistor, 0.4" wide

\n\nYageo CFR series http://www.yageo.com/pdf/yageo/Leaded-R_CFR_2008.pdf'; + +Edit 'AXIAL-0.5.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (-4500.000000 -1650.000000) (-4500.000000 1650.000000); +Layer 21; +Wire 203.200000 (-4500.000000 1650.000000) (4500.000000 1650.000000); +Layer 21; +Wire 203.200000 (4500.000000 1650.000000) (4500.000000 -1650.000000); +Layer 21; +Wire 203.200000 (4500.000000 -1650.000000) (-4500.000000 -1650.000000); +Change Drill 900.000000; +Pad 1879.600000 Round R0.0 'P$1' (-6350.000000 0.000000); +Change Drill 900.000000; +Pad 1879.600000 Round R0.0 'P$2' (6350.000000 0.000000); +Layer 25; +CHANGE FONT VECTOR; +Change Size 812.800000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-4445.000000 2540.000000); +Layer 21; +CHANGE FONT VECTOR; +Change Size 812.800000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-3429.000000 -381.000000); +DESCRIPTION '1/2W Resistor, 0.5" wide

\n\nYageo CFR series http://www.yageo.com/pdf/yageo/Leaded-R_CFR_2008.pdf'; + +Edit 'AXIAL-0.6.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (-5750.000000 -2250.000000) (-5750.000000 2250.000000); +Layer 21; +Wire 203.200000 (-5750.000000 2250.000000) (5750.000000 2250.000000); +Layer 21; +Wire 203.200000 (5750.000000 2250.000000) (5750.000000 -2250.000000); +Layer 21; +Wire 203.200000 (5750.000000 -2250.000000) (-5750.000000 -2250.000000); +Change Drill 1200.000000; +Pad 1879.600000 Round R0.0 'P$1' (-7620.000000 0.000000); +Change Drill 1200.000000; +Pad 1879.600000 Round R0.0 'P$2' (7620.000000 0.000000); +Layer 25; +CHANGE FONT VECTOR; +Change Size 812.800000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-5715.000000 3175.000000); +Layer 21; +CHANGE FONT VECTOR; +Change Size 812.800000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-4064.000000 -381.000000); +DESCRIPTION '1W Resistor, 0.6" wide

\n\nYageo CFR series http://www.yageo.com/pdf/yageo/Leaded-R_CFR_2008.pdf'; + +Edit 'AXIAL-0.8.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (-7750.000000 -2500.000000) (-7750.000000 2500.000000); +Layer 21; +Wire 203.200000 (-7750.000000 2500.000000) (7750.000000 2500.000000); +Layer 21; +Wire 203.200000 (7750.000000 2500.000000) (7750.000000 -2500.000000); +Layer 21; +Wire 203.200000 (7750.000000 -2500.000000) (-7750.000000 -2500.000000); +Change Drill 1200.000000; +Pad 1879.600000 Round R0.0 'P$1' (-10160.000000 0.000000); +Change Drill 1200.000000; +Pad 1879.600000 Round R0.0 'P$2' (10160.000000 0.000000); +Layer 25; +CHANGE FONT VECTOR; +Change Size 812.800000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-7620.000000 3175.000000); +Layer 21; +CHANGE FONT VECTOR; +Change Size 812.800000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-5969.000000 -381.000000); +DESCRIPTION '2W Resistor, 0.8" wide

\n\nYageo CFR series http://www.yageo.com/pdf/yageo/Leaded-R_CFR_2008.pdf'; + +Edit 'AXIAL-5MM.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (-1140.000000 762.000000) (1140.000000 762.000000); +Layer 21; +Wire 203.200000 (1140.000000 762.000000) (1140.000000 0.000000); +Layer 21; +Wire 203.200000 (1140.000000 0.000000) (1140.000000 -762.000000); +Layer 21; +Wire 203.200000 (1140.000000 -762.000000) (-1140.000000 -762.000000); +Layer 21; +Wire 203.200000 (-1140.000000 -762.000000) (-1140.000000 0.000000); +Layer 21; +Wire 203.200000 (-1140.000000 0.000000) (-1140.000000 762.000000); +Layer 21; +Wire 203.200000 (1140.000000 0.000000) (1394.000000 0.000000); +Layer 21; +Wire 203.200000 (-1140.000000 0.000000) (-1394.000000 0.000000); +Change Drill 900.000000; +Pad 1879.600000 Round R0.0 'P$1' (-2500.000000 0.000000); +Change Drill 900.000000; +Pad 1879.600000 Round R0.0 'P$2' (2500.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 400.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-2540.000000 1170.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 400.000000; +Change Ratio 15; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-1032.000000 -208.000000); +DESCRIPTION ''; + +Edit 'CAP-PTH-5MM.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (0.000000 635.000000) (0.000000 -635.000000); +Change Drill 700.000000; +Pad 1651.000000 Round R0.0 '1' (-2500.000000 0.000000); +Change Drill 700.000000; +Pad 1651.000000 Round R0.0 '2' (2500.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-762.000000 1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-1016.000000 -1524.000000); +DESCRIPTION ''; + +Edit 'CAP-PTH-LARGE.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (0.000000 635.000000) (0.000000 0.000000); +Layer 21; +Wire 203.200000 (0.000000 0.000000) (0.000000 -635.000000); +Layer 21; +Wire 203.200000 (0.000000 0.000000) (-2540.000000 0.000000); +Layer 21; +Wire 203.200000 (0.000000 0.000000) (2540.000000 0.000000); +Change Drill 700.000000; +Pad 1651.000000 Round R0.0 '1' (-4826.000000 0.000000); +Change Drill 700.000000; +Pad 1651.000000 Round R0.0 '2' (4572.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-762.000000 1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-1016.000000 -1524.000000); +DESCRIPTION ''; + +Edit 'CAP-PTH-SMALL.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (1270.000000 635.000000) (1270.000000 -635.000000); +Change Drill 700.000000; +Pad 1651.000000 Round R0.0 '1' (0.000000 0.000000); +Change Drill 700.000000; +Pad 1651.000000 Round R0.0 '2' (2540.000000 0.000000); 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+Layer 30; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 127.000000 (-1402.100000 -947.500000) -90.000000 (-2357.000000 -17.800000) -90.011749 (-1404.600000 957.600000) -90.000000 (-454.600000 -20.400000) -90.024193 (-1402.100000 -947.500000) ; +Layer 29; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 127.000000 (-1404.600000 -439.500000) -90.012891 (-1849.100000 -15.300000) -90.000000 (-1404.600000 452.000000) -90.000000 (-962.700000 -5.100000) -90.012967 (-1404.600000 -439.500000) ; +Layer 30; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 127.000000 (1397.000000 -947.500000) -90.000000 (442.100000 -17.800000) -90.011749 (1394.500000 957.600000) -90.000000 (2344.500000 -20.400000) -90.024193 (1397.000000 -947.500000) ; +Layer 29; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 127.000000 (1394.500000 -439.500000) -90.012891 (950.000000 -15.300000) -90.000000 (1394.500000 452.000000) -90.000000 (1836.400000 -5.100000) -90.012967 (1394.500000 -439.500000) ; +DESCRIPTION ''; + +Edit 'CAP-PTH-SMALL2.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (1270.000000 635.000000) (1270.000000 -635.000000); +Layer 21; +Wire 203.200000 (-1270.000000 1270.000000) (3810.000000 1270.000000); +Layer 21; +Wire 203.200000 (3810.000000 1270.000000) (3810.000000 -1270.000000); +Layer 21; +Wire 203.200000 (3810.000000 -1270.000000) (-1270.000000 -1270.000000); +Layer 21; +Wire 203.200000 (-1270.000000 -1270.000000) (-1270.000000 1270.000000); +Change Drill 700.000000; +Pad 1651.000000 Round R0.0 '1' (0.000000 0.000000); +Change Drill 700.000000; +Pad 1651.000000 Round R0.0 '2' (2540.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 609.600000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-1270.000000 1905.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 609.600000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-1270.000000 -2540.000000); +DESCRIPTION ''; + +Edit 'CTZ3.PAC'; +GRID mic; +Layer 51; +Wire 127.000000 (-1600.000000 1400.000000) (-1600.000000 -2250.000000); +Layer 51; +Wire 127.000000 (-1600.000000 -2250.000000) (1600.000000 -2250.000000); +Layer 51; +Wire 127.000000 (1600.000000 1400.000000) (1600.000000 -2250.000000); +Layer 51; +Wire 127.000000 (-500.000000 0.000000) (500.000000 0.000000); +Layer 51; +Wire 127.000000 (-1600.000000 1400.000000) (-1000.000000 2200.000000); +Layer 51; +Wire 127.000000 (1600.000000 1400.000000) (1000.000000 2200.000000); +Layer 51; +Wire 127.000000 (-1000.000000 2200.000000) (1000.000000 2200.000000); +Layer 51; +Wire 127.000000 (0.000000 800.000000) (0.000000 -800.000000); +Layer 51; +Wire 127.000000 (-800.000000 0.000000) (800.000000 0.000000); +Layer 21; +Wire 127.000000 (-1050.000000 2250.000000) (-1700.000000 1450.000000); +Layer 21; +Wire 127.000000 (-1700.000000 1450.000000) (-1700.000000 -2350.000000); +Layer 21; +Wire 127.000000 (-1700.000000 -2350.000000) (-1050.000000 -2350.000000); +Layer 21; +Wire 127.000000 (1050.000000 2250.000000) (1700.000000 1400.000000); +Layer 21; +Wire 127.000000 (1700.000000 1400.000000) (1700.000000 -2350.000000); +Layer 21; +Wire 127.000000 (1700.000000 -2350.000000) (1050.000000 -2350.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1500.000000 1200.000000 -0 R0.0 '+' (0.000000 2050.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1500.000000 1200.000000 -0 R0.0 '-' (0.000000 -2050.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-2000.000000 3000.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2000.000000 -3400.000000); +DESCRIPTION 'CTZ3 Series land pattern for variable capacitor - CTZ3E-50C-W1-PF'; + +Edit 'GRM43D.PAC'; +GRID mic; +Layer 51; +Wire 127.000000 (2250.000000 1600.000000) (1100.000000 1600.000000); +Layer 51; +Wire 127.000000 (1100.000000 1600.000000) (-1100.000000 1600.000000); +Layer 51; +Wire 127.000000 (-1100.000000 1600.000000) (-2250.000000 1600.000000); +Layer 51; +Wire 127.000000 (-2250.000000 1600.000000) (-2250.000000 -1600.000000); +Layer 51; +Wire 127.000000 (-2250.000000 -1600.000000) (-1100.000000 -1600.000000); +Layer 51; +Wire 127.000000 (-1100.000000 -1600.000000) (1100.000000 -1600.000000); +Layer 51; +Wire 127.000000 (1100.000000 -1600.000000) (2250.000000 -1600.000000); +Layer 51; +Wire 127.000000 (2250.000000 -1600.000000) (2250.000000 1600.000000); +Layer 51; +Wire 127.000000 (1100.000000 1600.000000) (1100.000000 -1600.000000); +Layer 51; +Wire 127.000000 (-1100.000000 1600.000000) (-1100.000000 -1600.000000); +Layer 21; +Wire 127.000000 (-2300.000000 1800.000000) (2300.000000 1800.000000); +Layer 21; +Wire 127.000000 (-2300.000000 -1800.000000) (2300.000000 -1800.000000); +Layer 51; +Rect R0.0 (-2200.000000 -1600.000000) (-1100.000000 1600.000000); +Layer 51; +Rect R0.0 (1100.000000 -1600.000000) (2200.000000 1600.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3200.000000 1650.000000 -0 R90.0 'A' (1927.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3200.000000 1650.000000 -0 R90.0 'C' (-1927.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-2000.000000 2000.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R180.0 '>VALUE' (0.000000 -2000.000000); +DESCRIPTION ''; + +Edit 'R2010.PAC'; +GRID mic; +Layer 51; +Wire 152.400000 (-1662.000000 1245.000000) (1662.000000 1245.000000); +Layer 51; +Wire 152.400000 (-1637.000000 -1245.000000) (1687.000000 -1245.000000); +Layer 39; +Wire 50.800000 (-3473.000000 1483.000000) (3473.000000 1483.000000); +Layer 39; +Wire 50.800000 (3473.000000 1483.000000) (3473.000000 -1483.000000); +Layer 39; +Wire 50.800000 (3473.000000 -1483.000000) (-3473.000000 -1483.000000); +Layer 39; +Wire 50.800000 (-3473.000000 -1483.000000) (-3473.000000 1483.000000); +Layer 21; +Wire 152.400000 (-1027.000000 1245.000000) (1027.000000 1245.000000); +Layer 21; +Wire 152.400000 (-1002.000000 -1245.000000) (1016.000000 -1245.000000); +Layer 51; +Rect R0.0 (-2489.200000 -1320.800000) (-1639.300000 1329.200000); +Layer 51; +Rect R0.0 (1651.000000 -1320.800000) (2500.900000 1329.200000); +Layer 1; +CHANGE Roundness 0; +SMD 1800.000000 2700.000000 -0 R0.0 '1' (-2200.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1800.000000 2700.000000 -0 R0.0 '2' (2200.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-2540.000000 1587.500000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2540.000000 -2032.000000); +DESCRIPTION 'RESISTOR

\nchip'; + +Edit 'R2512.PAC'; +GRID mic; +Layer 51; +Wire 152.400000 (-2362.000000 1473.000000) (2387.000000 1473.000000); +Layer 51; +Wire 152.400000 (-2362.000000 -1473.000000) (2387.000000 -1473.000000); +Layer 51; +Rect R0.0 (-3200.400000 -1549.400000) (-2350.500000 1550.700000); +Layer 51; +Rect R0.0 (2362.200000 -1549.400000) (3212.100000 1550.700000); +Layer 1; +CHANGE Roundness 0; +SMD 1800.000000 3200.000000 -0 R0.0 '1' (-2800.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1800.000000 3200.000000 -0 R0.0 '2' (2800.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-2540.000000 1905.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2540.000000 -3175.000000); +DESCRIPTION ''; + +Edit 'S4B-PH.PAC'; +GRID mic; +Layer 51; +Wire 304.800000 (-6000.000000 2000.000000) (-6000.000000 -7000.000000); +Layer 51; +Wire 304.800000 (-6000.000000 -7000.000000) (6000.000000 -7000.000000); +Layer 51; +Wire 304.800000 (6000.000000 -7000.000000) (6000.000000 2000.000000); +Layer 51; +Wire 304.800000 (6000.000000 2000.000000) (-6000.000000 2000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1000.000000 4600.000000 -0 R0.0 '1' (-3000.000000 -4700.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1000.000000 4600.000000 -0 R0.0 '2' (-1000.000000 -4700.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1000.000000 4600.000000 -0 R0.0 '3' (1000.000000 -4700.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1000.000000 4600.000000 -0 R0.0 '4' (3000.000000 -4700.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3400.000000 1600.000000 -0 R90.0 'P$1' (-5400.000000 500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3400.000000 1600.000000 -0 R90.0 'P$2' (5400.000000 500.000000); +DESCRIPTION ''; + +Edit 'USB-A-H.PAC'; +GRID mic; +Layer 51; +Wire 203.200000 (-17800.000000 6000.000000) (-17800.000000 -6000.000000); +Layer 21; +Wire 203.200000 (-3000.000000 6000.000000) (-3000.000000 -6000.000000); +Layer 51; +Wire 203.200000 (-3000.000000 6000.000000) (-17800.000000 6000.000000); +Layer 51; +Wire 203.200000 (-3000.000000 -6000.000000) (-17800.000000 -6000.000000); +Layer 21; +Wire 203.200000 (-3000.000000 6000.000000) (-2000.000000 6000.000000); +Layer 21; +Wire 203.200000 (-3000.000000 -6000.000000) (-2000.000000 -6000.000000); +Layer 21; +Wire 203.200000 (1000.000000 -4000.000000) (1000.000000 4000.000000); +Layer 51; +Wire 203.200000 (-13500.000000 4300.000000) (-13500.000000 1900.000000); +Layer 51; +Wire 203.200000 (-13500.000000 1900.000000) (-11200.000000 1900.000000); +Layer 51; +Wire 203.200000 (-11200.000000 1900.000000) (-11200.000000 4300.000000); +Layer 51; +Wire 203.200000 (-11200.000000 4300.000000) (-13500.000000 4300.000000); +Layer 51; +Wire 203.200000 (-13500.000000 -1900.000000) (-13500.000000 -4300.000000); +Layer 51; +Wire 203.200000 (-13500.000000 -4300.000000) (-11200.000000 -4300.000000); +Layer 51; +Wire 203.200000 (-11200.000000 -4300.000000) (-11200.000000 -1900.000000); +Layer 51; +Wire 203.200000 (-11200.000000 -1900.000000) (-13500.000000 -1900.000000); +Change Drill 914.400000; +Pad 1879.600000 Round R270.0 'D+' (2400.000000 1127.000000); +Change Drill 914.400000; +Pad 1879.600000 Round R270.0 'D-' (2400.000000 -1127.000000); +Change Drill 914.400000; +Pad 1879.600000 Round R270.0 'GND' (2400.000000 3500.000000); +Change Drill 2200.000000; +Pad 0.000000 Round R270.0 'GND2' (0.000000 -5800.000000); +Change Drill 2200.000000; +Pad 0.000000 Round R270.0 'GND3' (0.000000 5800.000000); +Change Drill 914.400000; +Pad 1879.600000 Round R270.0 'VBUS' (2400.000000 -3500.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (5850.000000 -2700.000000); +Layer 51; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 'PCB Edge' (-3900.000000 -4400.000000); +Change Drill 1100.000000; +Hole (-100.000000 2250.000000); +Change Drill 1100.000000; +Hole (-100.000000 -2250.000000); +DESCRIPTION 'USB Series A Hole Mounted'; + +Edit 'USB-A-PCB.PAC'; +GRID mic; +Layer 51; +Wire 127.000000 (-5000.000000 6000.000000) (3700.000000 6000.000000); +Layer 51; +Wire 127.000000 (3700.000000 6000.000000) (3700.000000 -6000.000000); +Layer 51; +Wire 127.000000 (3700.000000 -6000.000000) (-5000.000000 -6000.000000); +Layer 51; +Wire 127.000000 (-5000.000000 -6000.000000) (-5000.000000 6000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 7500.000000 1500.000000 -0 R0.0 '5V' (-200.000000 -3500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 7500.000000 1500.000000 -0 R0.0 'GND' (-200.000000 3500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 6500.000000 1000.000000 -0 R0.0 'USB_M' (300.000000 -1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 6500.000000 1000.000000 -0 R0.0 'USB_P' (300.000000 1000.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Name' (-1270.000000 5080.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>Value' (-1270.000000 -5080.000000); +DESCRIPTION ''; + +Edit 'USB-A-S.PAC'; +GRID mic; +Layer 21; +Wire 127.000000 (3695.700000 6565.900000) (-10287.000000 6565.900000); +Layer 21; +Wire 127.000000 (3695.700000 -6565.900000) (-10287.000000 -6565.900000); +Layer 21; +Wire 127.000000 (-10287.000000 6477.000000) (-10287.000000 -6477.000000); +Layer 21; +Wire 127.000000 (3708.400000 6502.400000) (3708.400000 -6502.400000); +Layer 21; +Wire 127.000000 (-2540.000000 -5080.000000) (-8890.000000 -4445.000000); +Layer 21; +Wire 127.000000 (-8890.000000 -4445.000000) (-8890.000000 -1270.000000); +Layer 21; +Wire 127.000000 (-8890.000000 -1270.000000) (-2540.000000 -635.000000); +Layer 21; +Wire 127.000000 (-2540.000000 5080.000000) (-8890.000000 4445.000000); +Layer 21; +Wire 127.000000 (-8890.000000 4445.000000) (-8890.000000 1270.000000); +Layer 21; +Wire 127.000000 (-8890.000000 1270.000000) (-2540.000000 635.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'D+' (3450.000000 -1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'D-' (3450.000000 1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'GND' (3450.000000 -3000.000000); +Change Drill 2311.400000; +Pad 0.000000 Round R270.0 'P$5' (0.000000 -6565.900000); +Change Drill 2311.400000; +Pad 0.000000 Round R270.0 'P$6' (0.000000 6565.900000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'VBUS' (3450.000000 3000.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (5715.000000 3810.000000); +DESCRIPTION 'USB Series A Surface Mounted'; + +Edit 'USB-A-S-NOSILK.PAC'; +GRID mic; +Layer 51; +Wire 127.000000 (3695.700000 6565.900000) (-10287.000000 6565.900000); +Layer 51; +Wire 127.000000 (3695.700000 -6565.900000) (-10287.000000 -6565.900000); +Layer 51; +Wire 127.000000 (-10287.000000 6477.000000) (-10287.000000 -6477.000000); +Layer 51; +Wire 127.000000 (3708.400000 6502.400000) (3708.400000 -6502.400000); +Layer 51; +Wire 127.000000 (-2540.000000 -5080.000000) (-8890.000000 -4445.000000); +Layer 51; +Wire 127.000000 (-8890.000000 -4445.000000) (-8890.000000 -1270.000000); +Layer 51; +Wire 127.000000 (-8890.000000 -1270.000000) (-2540.000000 -635.000000); +Layer 51; +Wire 127.000000 (-2540.000000 5080.000000) (-8890.000000 4445.000000); +Layer 51; +Wire 127.000000 (-8890.000000 4445.000000) (-8890.000000 1270.000000); +Layer 51; +Wire 127.000000 (-8890.000000 1270.000000) (-2540.000000 635.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'D+' (3450.000000 -1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'D-' (3450.000000 1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'GND' (3450.000000 -3000.000000); +Change Drill 2311.400000; +Pad 0.000000 Round R270.0 'P$5' (0.000000 -6565.900000); +Change Drill 2311.400000; +Pad 0.000000 Round R270.0 'P$6' (0.000000 6565.900000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'VBUS' (3450.000000 3000.000000); +Layer 51; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (5715.000000 3810.000000); +DESCRIPTION ''; + +Edit 'USB-A-S-NOSILK-FEMALE.PAC'; +GRID mic; +Layer 51; +Wire 127.000000 (3695.700000 6565.900000) (-10287.000000 6565.900000); +Layer 51; +Wire 127.000000 (3695.700000 -6565.900000) (-10287.000000 -6565.900000); +Layer 51; +Wire 127.000000 (-10287.000000 6477.000000) (-10287.000000 -6477.000000); +Layer 51; +Wire 127.000000 (3708.400000 6502.400000) (3708.400000 -6502.400000); +Layer 51; +Wire 127.000000 (-2540.000000 -5080.000000) (-8890.000000 -4445.000000); +Layer 51; +Wire 127.000000 (-8890.000000 -4445.000000) (-8890.000000 -1270.000000); +Layer 51; +Wire 127.000000 (-8890.000000 -1270.000000) (-2540.000000 -635.000000); +Layer 51; +Wire 127.000000 (-2540.000000 5080.000000) (-8890.000000 4445.000000); +Layer 51; +Wire 127.000000 (-8890.000000 4445.000000) (-8890.000000 1270.000000); +Layer 51; +Wire 127.000000 (-8890.000000 1270.000000) (-2540.000000 635.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'D+' (4212.000000 -1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'D-' (4212.000000 1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'GND' (4212.000000 -3500.000000); +Change Drill 2311.400000; +Pad 0.000000 Round R270.0 'P$5' (0.000000 -6565.900000); +Change Drill 2311.400000; +Pad 0.000000 Round R270.0 'P$6' (0.000000 6565.900000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'VBUS' (4212.000000 3500.000000); +Layer 51; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R180.0 '>NAME' (8460.000000 -7205.000000); +DESCRIPTION ''; + +Edit 'USB-A-S-SILK-FEMALE.PAC'; +GRID mic; +Layer 51; +Wire 127.000000 (6695.700000 6565.900000) (-7287.000000 6565.900000); +Layer 51; +Wire 127.000000 (6695.700000 -6565.900000) (-7287.000000 -6565.900000); +Layer 51; +Wire 127.000000 (-7287.000000 6477.000000) (-7287.000000 -6477.000000); +Layer 51; +Wire 127.000000 (6708.400000 6502.400000) (6708.400000 -6502.400000); +Layer 51; +Wire 127.000000 (460.000000 -5080.000000) (-5890.000000 -4445.000000); +Layer 51; +Wire 127.000000 (-5890.000000 -4445.000000) (-5890.000000 -1270.000000); +Layer 51; +Wire 127.000000 (-5890.000000 -1270.000000) (460.000000 -635.000000); +Layer 51; +Wire 127.000000 (460.000000 5080.000000) (-5890.000000 4445.000000); +Layer 51; +Wire 127.000000 (-5890.000000 4445.000000) (-5890.000000 1270.000000); +Layer 51; +Wire 127.000000 (-5890.000000 1270.000000) (460.000000 635.000000); +Layer 21; +Wire 203.200000 (-7366.000000 6604.000000) (508.000000 6604.000000); +Layer 21; +Wire 203.200000 (-7366.000000 6604.000000) (-7366.000000 -6604.000000); +Layer 21; +Wire 203.200000 (-7366.000000 -6604.000000) (508.000000 -6604.000000); +Layer 21; +Wire 203.200000 (5080.000000 -6604.000000) (6858.000000 -6604.000000); +Layer 21; +Wire 203.200000 (6858.000000 -6604.000000) (6858.000000 -4318.000000); +Layer 21; +Wire 203.200000 (6858.000000 4318.000000) (6858.000000 6604.000000); +Layer 21; +Wire 203.200000 (6858.000000 6604.000000) (5080.000000 6604.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'D+' (7212.000000 -1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'D-' (7212.000000 1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'GND' (7212.000000 -3500.000000); +Change Drill 2311.400000; +Pad 0.000000 Round R270.0 'P$5' (3000.000000 -6565.900000); +Change Drill 2311.400000; +Pad 0.000000 Round R270.0 'P$6' (3000.000000 6565.900000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 900.000000 -0 R0.0 'VBUS' (7212.000000 3500.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-3810.000000 2540.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-3810.000000 -3810.000000); +DESCRIPTION ''; + +Edit 'USB-A-SMT-MALE.PAC'; +GRID mic; +Layer 51; +Wire 203.200000 (6000.000000 16530.000000) (-6000.000000 16530.000000); +Layer 21; +Wire 203.200000 (6000.000000 1730.000000) (-6000.000000 1730.000000); +Layer 51; +Wire 203.200000 (6000.000000 1730.000000) (6000.000000 16530.000000); +Layer 51; +Wire 203.200000 (-6000.000000 1730.000000) (-6000.000000 16530.000000); +Layer 21; +Wire 203.200000 (6000.000000 1730.000000) (6000.000000 730.000000); +Layer 21; +Wire 203.200000 (-6000.000000 1730.000000) (-6000.000000 730.000000); +Layer 21; +Wire 203.200000 (-4000.000000 -2270.000000) (4000.000000 -2270.000000); +Layer 51; +Wire 203.200000 (4300.000000 12230.000000) (1900.000000 12230.000000); +Layer 51; +Wire 203.200000 (1900.000000 12230.000000) (1900.000000 9930.000000); +Layer 51; +Wire 203.200000 (1900.000000 9930.000000) (4300.000000 9930.000000); +Layer 51; +Wire 203.200000 (4300.000000 9930.000000) (4300.000000 12230.000000); +Layer 51; +Wire 203.200000 (-1900.000000 12230.000000) (-4300.000000 12230.000000); +Layer 51; +Wire 203.200000 (-4300.000000 12230.000000) (-4300.000000 9930.000000); +Layer 51; +Wire 203.200000 (-4300.000000 9930.000000) (-1900.000000 9930.000000); +Layer 51; +Wire 203.200000 (-1900.000000 9930.000000) (-1900.000000 12230.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2000.000000 1200.000000 -0 R270.0 'D+1' (1027.000000 -3670.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2000.000000 1200.000000 -0 R270.0 'D-1' (-1027.000000 -3670.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2000.000000 1200.000000 -0 R270.0 'GND1' (3500.000000 -3670.000000); +Change Drill 800.000000; +Pad 1500.000000 Long R90.0 'P$1' (5850.000000 -1100.000000); +Change Drill 800.000000; +Pad 1500.000000 Long R90.0 'P$3' (-5850.000000 -1100.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2000.000000 1200.000000 -0 R270.0 'VBUS1' (-3500.000000 -3670.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-2700.000000 -7120.000000); +Layer 51; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'PCB Edge' (-4400.000000 2630.000000); +Change Drill 1100.000000; +Hole (2250.000000 -1170.000000); +Change Drill 1100.000000; +Hole (-2250.000000 -1170.000000); +Change Drill 800.000000; +Hole (-5850.000000 -1500.000000); +Change Drill 800.000000; +Hole (-5850.000000 -1900.000000); +Change Drill 800.000000; +Hole (-5850.000000 -700.000000); +Change Drill 800.000000; +Hole (-5850.000000 -300.000000); +Change Drill 800.000000; +Hole (5850.000000 -1500.000000); +Change Drill 800.000000; +Hole (5850.000000 -1900.000000); +Change Drill 800.000000; +Hole (5850.000000 -700.000000); +Change Drill 800.000000; +Hole (5850.000000 -300.000000); +DESCRIPTION ''; + +Edit 'USB-B-PTH.PAC'; +GRID mic; +Layer 51; +Wire 203.200000 (-12500.000000 6000.000000) (-8600.000000 6000.000000); +Layer 51; +Wire 203.200000 (-8600.000000 6000.000000) (-8600.000000 -6000.000000); +Layer 51; +Wire 203.200000 (-8600.000000 -6000.000000) (-12500.000000 -6000.000000); +Layer 51; +Wire 203.200000 (-12500.000000 -6000.000000) (-12500.000000 6000.000000); +Layer 21; +Wire 203.200000 (-8600.000000 6000.000000) (-4800.000000 6000.000000); +Layer 21; +Wire 203.200000 (-8600.000000 -6000.000000) (-4800.000000 -6000.000000); +Layer 21; +Wire 203.200000 (-600.000000 -6000.000000) (3300.000000 -6000.000000); +Layer 21; +Wire 203.200000 (3300.000000 -6000.000000) (3300.000000 6000.000000); +Layer 21; +Wire 203.200000 (3300.000000 6000.000000) (-600.000000 6000.000000); +Change Drill 914.400000; +Pad 1676.400000 Round R270.0 'D+' (0.000000 1250.000000); +Change Drill 914.400000; +Pad 1676.400000 Round R90.0 'D-' (1981.200000 1250.000000); +Change Drill 914.400000; +Pad 1676.400000 Round R270.0 'GND' (0.000000 -1250.000000); +Change Drill 2286.000000; +Pad 0.000000 Round R0.0 'S1' (-2717.800000 -6019.800000); +Change Drill 2286.000000; +Pad 0.000000 Round R0.0 'S2' (-2717.800000 6019.800000); +Change Drill 914.400000; +Pad 1676.400000 Round R90.0 'VBUS' (1981.200000 -1250.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1270.000000 3810.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1270.000000 2540.000000); +DESCRIPTION 'USB Series B Hole Mounted'; + +Edit 'USB-B-PTH-VERTICAL.PAC'; +GRID mic; +Layer 21; +Wire 254.000000 (0.000000 0.000000) (11938.000000 0.000000); +Layer 21; +Wire 254.000000 (11938.000000 0.000000) (11938.000000 11303.000000); +Layer 21; +Wire 254.000000 (11938.000000 11303.000000) (0.000000 11303.000000); +Layer 21; +Wire 254.000000 (0.000000 11303.000000) (0.000000 0.000000); +Layer 51; +Wire 254.000000 (1270.000000 1270.000000) (10795.000000 1270.000000); +Layer 51; +Wire 254.000000 (10795.000000 1270.000000) (10795.000000 8255.000000); +Layer 51; +Wire 254.000000 (10795.000000 8255.000000) (8890.000000 10160.000000); +Layer 51; +Wire 254.000000 (8890.000000 10160.000000) (3175.000000 10160.000000); +Layer 51; +Wire 254.000000 (3175.000000 10160.000000) (1270.000000 8255.000000); +Layer 51; +Wire 254.000000 (1270.000000 8255.000000) (1270.000000 1270.000000); +Change Drill 914.400000; +Pad 1676.400000 Round R270.0 'D+' (4826.000000 4394.200000); +Change Drill 914.400000; +Pad 1676.400000 Round R270.0 'D-' (4826.000000 7594.600000); +Change Drill 914.400000; +Pad 1676.400000 Round R90.0 'GND' (7315.200000 4394.200000); +Change Drill 2286.000000; +Pad 0.000000 Round R0.0 'P$1' (0.000000 4902.200000); +Change Drill 2286.000000; +Pad 0.000000 Round R0.0 'P$2' (12039.600000 4902.200000); +Change Drill 914.400000; +Pad 1676.400000 Round R90.0 'VBUS' (7315.200000 7594.600000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 812.800000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (8890.000000 -1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 812.800000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (0.000000 -1270.000000); +DESCRIPTION 'USB Series B Hole Mounted'; + +Edit 'USB-B-SMT.PAC'; +GRID mic; +Layer 51; +Wire 203.200000 (-1000.000000 -6000.000000) (2400.000000 -6000.000000); +Layer 51; +Wire 203.200000 (2400.000000 6000.000000) (-1000.000000 6000.000000); +Layer 51; +Wire 203.200000 (2400.000000 6000.000000) (2400.000000 7300.000000); +Layer 51; +Wire 203.200000 (2400.000000 7300.000000) (2200.000000 7500.000000); +Layer 51; +Wire 203.200000 (2200.000000 7500.000000) (1900.000000 7500.000000); +Layer 51; +Wire 203.200000 (1900.000000 7500.000000) (1400.000000 7000.000000); +Layer 51; +Wire 203.200000 (-1000.000000 6000.000000) (-1000.000000 7300.000000); +Layer 51; +Wire 203.200000 (-800.000000 7500.000000) (-500.000000 7500.000000); +Layer 51; +Wire 203.200000 (-500.000000 7500.000000) (0.000000 7000.000000); +Layer 51; +Wire 203.200000 (0.000000 7000.000000) (1400.000000 7000.000000); +Layer 51; +Wire 203.200000 (-1000.000000 -6000.000000) (-1000.000000 -7300.000000); +Layer 51; +Wire 203.200000 (-1000.000000 -7300.000000) (-800.000000 -7500.000000); +Layer 51; +Wire 203.200000 (-800.000000 -7500.000000) (-500.000000 -7500.000000); +Layer 51; +Wire 203.200000 (-500.000000 -7500.000000) (0.000000 -7000.000000); +Layer 51; +Wire 203.200000 (1900.000000 -7500.000000) (1400.000000 -7000.000000); +Layer 51; +Wire 203.200000 (1400.000000 -7000.000000) (0.000000 -7000.000000); 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+Layer 21; +Wire 203.200000 (7000.000000 3000.000000) (7000.000000 6000.000000); +Layer 21; +Wire 203.200000 (7000.000000 6000.000000) (4000.000000 6000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 6040.000000 3400.000000 -0 R0.0 '5' (580.000000 6800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 6040.000000 3400.000000 -0 R0.0 '6' (580.000000 -6800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 700.000000 -0 R0.0 'D+' (7000.000000 1875.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 700.000000 -0 R0.0 'D-' (7000.000000 625.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 700.000000 -0 R0.0 'GND' (7000.000000 -625.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3000.000000 700.000000 -0 R0.0 'VUSB' (7000.000000 -1875.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (4300.000000 -7795.000000); +Change Drill 1400.000000; +Hole (0.000000 2250.000000); +Change Drill 1400.000000; +Hole (0.000000 -2250.000000); +DESCRIPTION 'USB Series B Surface Mounted'; + +Edit 'USB-MB-H.PAC'; +GRID mic; +Layer 22; +Wire 127.000000 (-3750.000000 3900.000000) (-3750.000000 -3900.000000); +Layer 22; +Wire 127.000000 (5250.000000 3900.000000) (5250.000000 -3900.000000); +Layer 22; +Wire 127.000000 (-3750.000000 3900.000000) (5250.000000 3900.000000); +Layer 22; +Wire 127.000000 (-3750.000000 -3900.000000) (5250.000000 -3900.000000); +Layer 22; +Wire 127.000000 (750.000000 3500.000000) (-3250.000000 3000.000000); +Layer 22; +Wire 127.000000 (-3250.000000 3000.000000) (-3250.000000 2000.000000); +Layer 22; +Wire 127.000000 (-3250.000000 2000.000000) (750.000000 1500.000000); +Layer 22; +Wire 127.000000 (1250.000000 -3500.000000) (-3250.000000 -3000.000000); +Layer 22; +Wire 127.000000 (-3250.000000 -3000.000000) (-3250.000000 -2000.000000); +Layer 22; +Wire 127.000000 (-3250.000000 -2000.000000) (1250.000000 -1500.000000); +Layer 22; +Wire 127.000000 (-3250.000000 1250.000000) (1750.000000 750.000000); +Layer 22; +Wire 127.000000 (1750.000000 750.000000) (1750.000000 -750.000000); +Layer 22; +Wire 127.000000 (1750.000000 -750.000000) (-3250.000000 -1250.000000); +Layer 43; +Rect R0.0 (3250.000000 3000.000000) (5750.000000 4400.000000); +Layer 43; +Rect R0.0 (3250.000000 -4400.000000) (5750.000000 -3000.000000); +Layer 43; +Rect R0.0 (-3750.000000 -3100.000000) (-1425.000000 3100.000000); +Layer 43; +Rect R0.0 (-1425.000000 -2325.000000) (-650.000000 2325.000000); +Change Drill 800.000000; +Pad 0.000000 Round R0.0 'D+' (5100.000000 0.000000); +Change Drill 800.000000; +Pad 0.000000 Round R0.0 'D-' (3900.000000 800.000000); +Change Drill 800.000000; +Pad 0.000000 Round R0.0 'GND' (5100.000000 -1600.000000); +Change Drill 800.000000; +Pad 0.000000 Round R0.0 'ID' (3900.000000 -800.000000); +Change Drill 1900.000000; +Pad 0.000000 Round R0.0 'P$6' (0.000000 -3650.000000); +Change Drill 1900.000000; +Pad 0.000000 Round R0.0 'P$7' (0.000000 3650.000000); +Change Drill 800.000000; +Pad 0.000000 Round R0.0 'VBUS' (5100.000000 1600.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (7250.000000 1500.000000); +DESCRIPTION 'USB Series Mini-B Hole Mounted'; + +Edit 'USB-MICROB.PAC'; +GRID mic; +Layer 51; +Wire 127.000000 (-3400.000000 -2150.000000) (-3000.000000 -2150.000000); +Layer 51; +Wire 127.000000 (3000.000000 -2150.000000) (3400.000000 -2150.000000); +Layer 51; +Wire 127.000000 (-3400.000000 -2150.000000) (-3400.000000 -1450.000000); +Layer 51; +Wire 127.000000 (-3400.000000 -1450.000000) (-3400.000000 2850.000000); +Layer 51; +Wire 127.000000 (3400.000000 2850.000000) (2200.000000 2850.000000); +Layer 51; +Wire 127.000000 (3400.000000 2850.000000) (3400.000000 -1450.000000); +Layer 51; +Wire 127.000000 (3400.000000 -1450.000000) (3400.000000 -2150.000000); +Layer 51; +Wire 127.000000 (-3400.000000 -1450.000000) (3400.000000 -1450.000000); +Layer 21; +Wire 203.200000 (-3400.000000 1250.000000) (-3400.000000 2850.000000); +Layer 21; +Wire 203.200000 (-3400.000000 2850.000000) (-2200.000000 2850.000000); +Layer 21; +Wire 203.200000 (3400.000000 2850.000000) (2200.000000 2850.000000); +Layer 21; +Wire 203.200000 (3400.000000 1250.000000) (3400.000000 2850.000000); +Layer 21; +Wire 203.200000 (-3400.000000 -1450.000000) (3400.000000 -1450.000000); +Layer 51; +Wire 127.000000 (-2200.000000 1450.000000) (2200.000000 1450.000000); +Layer 51; +Wire 127.000000 (2200.000000 1450.000000) (2200.000000 2850.000000); +Layer 51; +Wire 127.000000 (-2200.000000 1450.000000) (-2200.000000 2850.000000); +Layer 51; +Wire 127.000000 (-3400.000000 2850.000000) (-2200.000000 2850.000000); +Layer 21; +Wire 203.200000 (-2200.000000 2850.000000) (-2200.000000 1450.000000); +Layer 21; +Wire 203.200000 (-2200.000000 1450.000000) (2200.000000 1450.000000); +Layer 21; +Wire 203.200000 (2200.000000 1450.000000) (2200.000000 2850.000000); +Layer 51; +Wire 203.200000 (-3400.000000 -2150.000000) (-4000.000000 -2750.000000); +Layer 51; +Wire 203.200000 (3400.000000 -2150.000000) (4000.000000 -2750.000000); +Layer 51; +Wire 127.000000 (-3000.000000 -2150.000000) (-3000.000000 -2550.000000); +Layer 51; +Wire 127.000000 (-2800.000000 -2800.000000) (2750.000000 -2800.000000); +Layer 51; +Wire 127.000000 (3000.000000 -2600.000000) (3000.000000 -2150.000000); +Layer 51; +WIRE 127.000000 ROUND (-3000.000000 -2550.000000) +84.547378 (-2800.000000 -2800.000000); +Layer 51; +WIRE 127.000000 ROUND (2750.000000 -2800.000000) +84.547378 (3000.000000 -2600.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1400.000000 350.000000 -0 R90.0 'D+' (0.000000 2650.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1400.000000 350.000000 -0 R90.0 'D-' (-650.000000 2650.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1400.000000 350.000000 -0 R90.0 'GND' (1300.000000 2650.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1400.000000 350.000000 -0 R90.0 'ID' (650.000000 2650.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1800.000000 1900.000000 -0 R0.0 'MT1' (-4000.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1800.000000 1900.000000 -0 R0.0 'MT2' (4000.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1900.000000 1900.000000 -0 R0.0 'P$1' (-1270.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1900.000000 1900.000000 -0 R0.0 'P$2' (1270.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1400.000000 350.000000 -0 R90.0 'VBUS' (-1300.000000 2650.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 762.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1600.000000 -350.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 762.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1905.000000 -3175.000000); +DESCRIPTION 'Micro USB Package'; + +Edit 'USB-MINIB.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (-1300.000000 3800.000000) (800.000000 3800.000000); +Layer 21; +Wire 203.200000 (3300.000000 3100.000000) (3300.000000 2200.000000); +Layer 21; +Wire 203.200000 (3300.000000 -2200.000000) (3300.000000 -3100.000000); +Layer 21; +Wire 203.200000 (800.000000 -3800.000000) (-1300.000000 -3800.000000); +Layer 51; +Wire 203.200000 (-5900.000000 3800.000000) (-5900.000000 -3800.000000); +Layer 51; +Wire 203.200000 (-5900.000000 -3800.000000) (-4500.000000 -3800.000000); +Layer 51; +Wire 203.200000 (-5900.000000 3800.000000) (-4500.000000 3800.000000); +Layer 31; +Rect R0.0 (1500.000000 1400.000000) (3500.000000 1800.000000); +Layer 31; +Rect R0.0 (1500.000000 600.000000) (3500.000000 1000.000000); +Layer 31; +Rect R0.0 (1500.000000 -200.000000) (3500.000000 200.000000); +Layer 31; +Rect R0.0 (1500.000000 -1000.000000) (3500.000000 -600.000000); +Layer 31; +Rect R0.0 (1500.000000 -1800.000000) (3500.000000 -1400.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 NOCREAM 'D+' (2500.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 NOCREAM 'D-' (2500.000000 800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 NOCREAM 'GND' (2500.000000 -1600.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 NOCREAM 'ID' (2500.000000 -800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 'MTN1' (-3000.000000 4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 'MTN2' (2500.000000 4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 'MTN3' (-3000.000000 -4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 'MTN4' (2500.000000 -4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 NOCREAM 'VBUS' (2500.000000 1600.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-3810.000000 1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-3810.000000 0.000000); +Change Drill 900.000000; +Hole (0.000000 2200.000000); +Change Drill 900.000000; +Hole (0.000000 -2200.000000); +DESCRIPTION 'USB Series Mini-B Surface Mounted'; + +Edit 'USB-MINIB-NOSTOP.PAC'; +GRID mic; +Layer 29; +Circle 410.000000 (0.000000 2200.000000) (350.000000 2200.000000); +Layer 29; +Circle 410.000000 (0.000000 -2200.000000) (350.000000 -2200.000000); +Layer 21; +Wire 203.200000 (-1300.000000 3800.000000) (800.000000 3800.000000); +Layer 21; +Wire 203.200000 (3300.000000 3100.000000) (3300.000000 2200.000000); +Layer 21; +Wire 203.200000 (3300.000000 -2200.000000) (3300.000000 -3100.000000); +Layer 21; +Wire 203.200000 (800.000000 -3800.000000) (-1300.000000 -3800.000000); +Layer 51; +Wire 203.200000 (-5900.000000 3800.000000) (-5900.000000 -3800.000000); +Layer 51; +Wire 203.200000 (-5900.000000 -3800.000000) (-4500.000000 -3800.000000); +Layer 51; +Wire 203.200000 (-5900.000000 3800.000000) (-4500.000000 3800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 'D+' (2500.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 'D-' (2500.000000 800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 'G1' (-3000.000000 -4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 'G2' (-3000.000000 4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 'G3' (2500.000000 4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 'G4' (2500.000000 -4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 'GND' (2500.000000 -1600.000000); +Change Drill 900.000000; +Pad 800.000000 Round R0.0 NOSTOP 'H1' (0.000000 2200.000000); +Change Drill 900.000000; +Pad 787.400000 Round R0.0 NOSTOP 'H2' (0.000000 -2200.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 'ID' (2500.000000 -800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 500.000000 -0 R0.0 'VBUS' (2500.000000 1600.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-3810.000000 1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-3810.000000 0.000000); +DESCRIPTION ''; + +Edit 'USB-MINIB-OLD.PAC'; +GRID mic; +Layer 21; +Wire 127.000000 (-1500.000000 3800.000000) (900.000000 3800.000000); +Layer 21; +Wire 127.000000 (3300.000000 3100.000000) (3300.000000 2100.000000); +Layer 21; +Wire 127.000000 (3300.000000 -2100.000000) (3300.000000 -3100.000000); +Layer 21; +Wire 127.000000 (1000.000000 -3800.000000) (-1500.000000 -3800.000000); +Layer 51; +Wire 127.000000 (-5900.000000 3800.000000) (-5900.000000 -3800.000000); +Layer 51; +Wire 127.000000 (-5900.000000 -3800.000000) (-4500.000000 -3800.000000); +Layer 51; +Wire 127.000000 (-5900.000000 3800.000000) (-4500.000000 3800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 '1' (-3000.000000 -4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2500.000000 2000.000000 -0 R0.0 '2' (-3000.000000 4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3500.000000 2000.000000 -0 R0.0 '3' (3000.000000 -4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3500.000000 2000.000000 -0 R0.0 '4' (3000.000000 4500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3500.000000 500.000000 -0 R0.0 'D+' (3000.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3500.000000 500.000000 -0 R0.0 'D-' (3000.000000 800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3500.000000 500.000000 -0 R0.0 'GND' (3000.000000 -1600.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3500.000000 500.000000 -0 R0.0 'ID' (3000.000000 -800.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3500.000000 500.000000 -0 R0.0 'VBUS' (3010.000000 1610.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-3810.000000 -1270.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 406.400000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-3810.000000 0.000000); +Change Drill 900.000000; +Hole (0.000000 2200.000000); +Change Drill 900.000000; +Hole (0.000000 -2200.000000); +DESCRIPTION 'USB Series Mini-B Surface Mounted'; + +Edit 'IDC20.PAC'; +GRID mic; +Layer 21; +Wire 203.200000 (-1900.000000 -3002.500000) (-1900.000000 -4030.000000); +Layer 21; +Wire 203.200000 (1900.000000 -3002.500000) (1900.000000 -4030.000000); +Layer 21; +Wire 406.400000 (-13850.000000 -1970.000000) (-13150.000000 -3040.000000); +Layer 21; +Wire 406.400000 (-13150.000000 -3040.000000) (-12450.000000 -1970.000000); +Layer 21; +Wire 406.400000 (-12450.000000 -1970.000000) (-13850.000000 -1970.000000); +Layer 21; +Wire 203.200000 (-16560.000000 -4100.000000) (-16560.000000 4100.000000); +Layer 21; +Wire 203.200000 (-16560.000000 -4100.000000) (16560.000000 -4100.000000); +Layer 21; +Wire 203.200000 (16560.000000 -4100.000000) (16560.000000 4100.000000); +Layer 21; +Wire 203.200000 (16560.000000 4100.000000) (-16560.000000 4100.000000); +Layer 51; +Wire 203.200000 (-15760.000000 -3300.000000) (-15760.000000 3300.000000); +Layer 51; +Wire 203.200000 (-15760.000000 3300.000000) (15760.000000 3300.000000); +Layer 51; +Wire 203.200000 (15760.000000 3300.000000) (15760.000000 -3300.000000); +Layer 51; +Wire 203.200000 (15760.000000 -3300.000000) (1900.000000 -3300.000000); +Layer 51; +Wire 203.200000 (-1900.000000 -3300.000000) (-15760.000000 -3300.000000); +Layer 21; +Wire 203.200000 (-1905.000000 -2857.500000) (1905.000000 -2857.500000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '1' (-11430.000000 -1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '2' (-11430.000000 1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '3' (-8890.000000 -1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '4' (-8890.000000 1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '5' (-6350.000000 -1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '6' (-6350.000000 1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '7' (-3810.000000 -1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '8' (-3810.000000 1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '9' (-1270.000000 -1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '10' (-1270.000000 1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '11' (1270.000000 -1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '12' (1270.000000 1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '13' (3810.000000 -1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '14' (3810.000000 1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '15' (6350.000000 -1270.000000); +Change Drill 1000.000000; +Pad 1778.000000 Round R0.0 '16' (6350.000000 1270.000000); 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\nseries 057 contact pc board low profile headers

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\nStandard 50-pin edge connector for Apple ][ systems\n
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+SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '22' (-19685.000000 4445.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '23' (-17145.000000 4445.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '24' (-14605.000000 4445.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '25' (-12065.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '26' (-12065.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '27' (-14605.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '28' (-17145.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '29' (-19685.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '30' (-22225.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '31' (-24765.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '32' (-27305.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '33' (-29845.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '34' (-32385.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '35' (-34925.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '36' (-37465.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '37' (-40005.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '38' (-42545.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '39' (-45085.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '40' (-47625.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '41' (-50165.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '42' (-52705.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '43' (-55245.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '44' (-57785.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '45' (-60325.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '46' (-62865.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '47' (-65405.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '48' (-67945.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '49' (-70485.000000 4445.000000); +Layer 16; +CHANGE Roundness 0; +SMD 1524.000000 6477.000000 -0 R0.0 NOCREAM '50' (-73025.000000 4445.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-5715.000000 3175.000000); +Layer 48; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '7,87 mm' (-94513.400000 2971.800000); +Layer 48; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '74.93 mm +2.950"' (-40843.200000 -9296.400000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-5715.000000 -635.000000); +DESCRIPTION 'Apple ][ Peripheral Card\n
\nStandard 50-pin edge connector for Apple ][ systems\n
\nDimensions for slot #4 to #7\n
\nDimensions taken from Tech Note #28'; + +Edit 'CHIP-LED0603.PAC'; +GRID mic; +Layer 51; +Wire 101.600000 (-400.000000 450.000000) (-400.000000 -450.000000); +Layer 51; +Wire 101.600000 (400.000000 450.000000) (400.000000 -450.000000); +Layer 51; +Rect R0.0 (-450.000000 450.000000) (450.000000 850.000000); +Layer 51; +Rect R0.0 (-450.000000 -850.000000) (450.000000 -450.000000); +Layer 21; +Rect R0.0 (-450.000000 0.000000) (-300.000000 300.000000); +Layer 21; +Rect R0.0 (300.000000 0.000000) (450.000000 300.000000); +Layer 21; +Rect R0.0 (-150.000000 0.000000) (150.000000 300.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 800.000000 -0 R0.0 'A' (0.000000 -750.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 800.000000 -0 R0.0 'C' (0.000000 750.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-635.000000 -635.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (1905.000000 -635.000000); +DESCRIPTION 'Hyper CHIPLED Hyper-Bright LED

\nLB Q993
\nSource: http://www.osram.convergy.de/ ... Lb_q993.pdf'; + +Edit 'CHIP-LED0805.PAC'; +GRID mic; +Layer 51; +Wire 101.600000 (-625.000000 450.000000) (-625.000000 -450.000000); +Layer 51; +Wire 101.600000 (625.000000 450.000000) (625.000000 -475.000000); +Layer 21; +Rect R0.0 (-675.000000 0.000000) (-525.000000 300.000000); +Layer 21; +Rect R0.0 (525.000000 0.000000) (675.000000 300.000000); +Layer 21; +Rect R0.0 (-150.000000 0.000000) (150.000000 300.000000); +Layer 51; +Rect R0.0 (-675.000000 450.000000) (675.000000 1050.000000); +Layer 51; +Rect R0.0 (-675.000000 -1050.000000) (675.000000 -450.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1200.000000 1200.000000 -0 R0.0 'A' (0.000000 -1050.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1200.000000 1200.000000 -0 R0.0 'C' (0.000000 1050.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-1270.000000 -1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (2540.000000 -1270.000000); +DESCRIPTION 'Hyper CHIPLED Hyper-Bright LED

\nLB R99A
\nSource: http://www.osram.convergy.de/ ... lb_r99a.pdf'; + +Edit 'CHIPLED-0603-TTW.PAC'; +GRID mic; +Layer 51; +Circle 50.800000 (-350.000000 625.000000) (-275.000000 625.000000); +Layer 51; +WIRE 101.600000 ROUND (-300.000000 800.000000) +170.055574 (300.000000 800.000000); +Layer 51; +WIRE 50.800000 ROUND (-275.000000 -825.000000) -180.000000 (275.000000 -825.000000); +Layer 51; +Wire 101.600000 (-400.000000 375.000000) (-400.000000 -350.000000); +Layer 51; +Wire 101.600000 (400.000000 350.000000) (400.000000 -350.000000); +Layer 51; +Rect R0.0 (-450.000000 700.000000) (-250.000000 850.000000); +Layer 51; +Rect R0.0 (-275.000000 550.000000) (-225.000000 600.000000); +Layer 51; +Rect R0.0 (-450.000000 350.000000) (-400.000000 725.000000); +Layer 51; +Rect R0.0 (250.000000 550.000000) (450.000000 850.000000); +Layer 51; +Rect R0.0 (-450.000000 350.000000) (450.000000 575.000000); +Layer 51; +Rect R0.0 (-450.000000 -850.000000) (-250.000000 -350.000000); +Layer 51; +Rect R0.0 (250.000000 -850.000000) (450.000000 -350.000000); +Layer 51; +Rect R0.0 (-275.000000 -575.000000) (275.000000 -350.000000); +Layer 51; +Rect R0.0 (-275.000000 -650.000000) (-175.000000 -550.000000); +Layer 51; +Rect R0.0 (175.000000 -650.000000) (275.000000 -550.000000); +Layer 21; +Rect R0.0 (-125.000000 0.000000) (125.000000 250.000000); +Layer 29; +Rect R0.0 (-175.000000 325.000000) (175.000000 700.000000); +Layer 29; +Rect R0.0 (-400.000000 625.000000) (400.000000 1125.000000); +Layer 29; +Rect R0.0 (-400.000000 -1125.000000) (400.000000 -625.000000); +Layer 29; +Rect R0.0 (-175.000000 -675.000000) (175.000000 -325.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 500.000000 -0 R0.0 NOSTOP NOCREAM 'A' (0.000000 -875.000000); +Layer 1; +CHANGE Roundness 0; +SMD 350.000000 350.000000 -0 R0.0 'A@1' (0.000000 -500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 500.000000 -0 R0.0 NOSTOP NOCREAM 'C' (0.000000 875.000000); +Layer 1; +CHANGE Roundness 0; +SMD 350.000000 350.000000 -0 R0.0 'C@1' (0.000000 500.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-635.000000 -1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (1905.000000 -1270.000000); +DESCRIPTION 'CHIPLED-0603

\nRecommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603
\nPackage able to withstand TTW-soldering heat
\nPackage suitable for TTW-soldering
\nSource: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf'; + +Edit 'CHIPLED_0603.PAC'; +GRID mic; +Layer 51; +Circle 50.800000 (-350.000000 625.000000) (-275.000000 625.000000); +Layer 51; +WIRE 101.600000 ROUND (-300.000000 800.000000) +170.055574 (300.000000 800.000000); +Layer 51; +WIRE 50.800000 ROUND (-275.000000 -825.000000) -180.000000 (275.000000 -825.000000); +Layer 51; +Wire 101.600000 (-400.000000 375.000000) (-400.000000 -350.000000); +Layer 51; +Wire 101.600000 (400.000000 350.000000) (400.000000 -350.000000); +Layer 51; +Rect R0.0 (-450.000000 700.000000) (-250.000000 850.000000); +Layer 51; +Rect R0.0 (-275.000000 550.000000) (-225.000000 600.000000); +Layer 51; +Rect R0.0 (-450.000000 350.000000) (-400.000000 725.000000); +Layer 51; +Rect R0.0 (250.000000 550.000000) (450.000000 850.000000); +Layer 51; +Rect R0.0 (-450.000000 350.000000) (450.000000 575.000000); +Layer 51; +Rect R0.0 (-450.000000 -850.000000) (-250.000000 -350.000000); +Layer 51; +Rect R0.0 (250.000000 -850.000000) (450.000000 -350.000000); +Layer 51; +Rect R0.0 (-275.000000 -575.000000) (275.000000 -350.000000); +Layer 51; +Rect R0.0 (-275.000000 -650.000000) (-175.000000 -550.000000); +Layer 51; +Rect R0.0 (175.000000 -650.000000) (275.000000 -550.000000); +Layer 21; +Rect R0.0 (-125.000000 0.000000) (125.000000 250.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 800.000000 -0 R0.0 'A' (0.000000 -750.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 800.000000 -0 R0.0 'C' (0.000000 750.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-635.000000 -1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (1905.000000 -1270.000000); +DESCRIPTION 'CHIPLED

\nSource: http://www.osram.convergy.de/ ... LG_LY Q971.pdf'; + +Edit 'CHIPLED_0805.PAC'; +GRID mic; +Layer 51; +Circle 101.600000 (-450.000000 850.000000) (-347.000000 850.000000); +Layer 51; +WIRE 101.600000 ROUND (-350.000000 925.000000) +162.394521 (350.000000 925.000000); +Layer 51; +WIRE 101.600000 ROUND (-350.000000 -925.000000) -162.394521 (350.000000 -925.000000); +Layer 51; +Wire 101.600000 (575.000000 525.000000) (575.000000 -525.000000); +Layer 51; +Wire 101.600000 (-575.000000 -500.000000) (-575.000000 925.000000); +Layer 51; +Rect R0.0 (300.000000 500.000000) (625.000000 1000.000000); +Layer 51; +Rect R0.0 (-325.000000 500.000000) (-175.000000 750.000000); +Layer 51; +Rect R0.0 (175.000000 500.000000) (325.000000 750.000000); +Layer 51; +Rect R0.0 (-200.000000 500.000000) (200.000000 675.000000); +Layer 51; +Rect R0.0 (300.000000 -1000.000000) (625.000000 -500.000000); +Layer 51; +Rect R0.0 (-625.000000 -1000.000000) (-300.000000 -500.000000); +Layer 51; +Rect R0.0 (175.000000 -750.000000) (325.000000 -500.000000); +Layer 51; +Rect R0.0 (-325.000000 -750.000000) (-175.000000 -500.000000); +Layer 51; +Rect R0.0 (-200.000000 -675.000000) (200.000000 -500.000000); +Layer 21; +Rect R0.0 (-100.000000 0.000000) (100.000000 200.000000); +Layer 51; +Rect R0.0 (-600.000000 500.000000) (-300.000000 800.000000); +Layer 51; +Rect R0.0 (-625.000000 925.000000) (-300.000000 1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1200.000000 1200.000000 -0 R0.0 'A' (0.000000 -1050.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1200.000000 1200.000000 -0 R0.0 'C' (0.000000 1050.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-1270.000000 -1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (2540.000000 -1270.000000); +DESCRIPTION 'CHIPLED

\nSource: http://www.osram.convergy.de/ ... LG_R971.pdf'; + +Edit 'CHIPLED_1206.PAC'; +GRID mic; +Layer 51; +Circle 101.600000 (-550.000000 1425.000000) (-450.000000 1425.000000); +Layer 51; +WIRE 101.600000 ROUND (-400.000000 1600.000000) +172.619069 (400.000000 1600.000000); +Layer 51; +Wire 101.600000 (-800.000000 -950.000000) (-800.000000 950.000000); +Layer 51; +Wire 101.600000 (800.000000 950.000000) (800.000000 -950.000000); +Layer 51; +Rect R0.0 (-850.000000 1525.000000) (-350.000000 1650.000000); +Layer 51; +Rect R0.0 (-850.000000 1225.000000) (-625.000000 1550.000000); +Layer 51; +Rect R0.0 (-450.000000 1225.000000) (-325.000000 1450.000000); +Layer 51; +Rect R0.0 (-650.000000 1225.000000) (-225.000000 1350.000000); +Layer 51; +Rect R0.0 (350.000000 1300.000000) (850.000000 1650.000000); +Layer 51; +Rect R0.0 (250.000000 1225.000000) (850.000000 1350.000000); +Layer 51; +Rect R0.0 (-850.000000 950.000000) (850.000000 1250.000000); +Layer 51; +Rect R0.0 (-850.000000 -1650.000000) (850.000000 -950.000000); +Layer 21; +Rect R0.0 (-850.000000 350.000000) (-525.000000 775.000000); +Layer 21; +Rect R0.0 (525.000000 350.000000) (850.000000 775.000000); +Layer 21; +Rect R0.0 (-175.000000 0.000000) (175.000000 350.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1500.000000 1500.000000 -0 R0.0 'A' (0.000000 -1750.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1500.000000 1500.000000 -0 R0.0 'C' (0.000000 1750.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-1270.000000 -1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (2540.000000 -1270.000000); +DESCRIPTION 'CHIPLED

\nSource: http://www.osram.convergy.de/ ... LG_LY N971.pdf'; + +Edit 'IRL80A.PAC'; +GRID mic; +Layer 21; +Wire 152.400000 (889.000000 2286.000000) (889.000000 1778.000000); +Layer 51; +Wire 152.400000 (889.000000 1778.000000) (889.000000 762.000000); +Layer 21; +Wire 152.400000 (889.000000 762.000000) (889.000000 -635.000000); +Layer 51; +Wire 152.400000 (889.000000 -635.000000) (889.000000 -1778.000000); +Layer 21; +Wire 152.400000 (889.000000 -1778.000000) (889.000000 -2286.000000); +Layer 21; +Wire 152.400000 (889.000000 -2286.000000) (-889.000000 -2286.000000); +Layer 21; +Wire 152.400000 (-889.000000 2286.000000) (-889.000000 1778.000000); +Layer 51; +Wire 152.400000 (-889.000000 1778.000000) (-889.000000 762.000000); +Layer 21; +Wire 152.400000 (-889.000000 762.000000) (-889.000000 -762.000000); +Layer 51; +Wire 152.400000 (-889.000000 -762.000000) (-889.000000 -1778.000000); +Layer 21; +Wire 152.400000 (-889.000000 -1778.000000) (-889.000000 -2286.000000); +Layer 21; +Wire 152.400000 (-889.000000 2286.000000) (889.000000 2286.000000); +Layer 21; +WIRE 152.400000 ROUND (-889.000000 -762.000000) -180.000000 (-889.000000 762.000000); +Layer 21; +Wire 50.800000 (-1397.000000 254.000000) (-1397.000000 -254.000000); +Layer 21; +Wire 50.800000 (-1143.000000 508.000000) (-1143.000000 -508.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'A' (0.000000 -1270.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'K' (0.000000 1270.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (1270.000000 381.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (1270.000000 -1651.000000); +DESCRIPTION 'IR LED

\nIR transmitter Siemens'; + +Edit 'KA-3528ASYC.PAC'; +GRID mic; +Layer 51; +Circle 101.600000 (0.000000 0.000000) (1150.000000 0.000000); +Layer 21; +Wire 101.600000 (-1550.000000 1350.000000) (1550.000000 1350.000000); +Layer 51; +Wire 101.600000 (1550.000000 1350.000000) (1550.000000 -1350.000000); +Layer 21; +Wire 101.600000 (1550.000000 -1350.000000) (-1550.000000 -1350.000000); +Layer 51; +Wire 101.600000 (-1550.000000 -1350.000000) (-1550.000000 1350.000000); +Layer 21; +WIRE 101.600000 ROUND (-650.000000 950.000000) -68.408130 (650.000000 950.000000); +Layer 21; +WIRE 101.600000 ROUND (650.000000 -950.000000) -68.408130 (-650.000000 -950.000000); +Layer 51; +Rect R0.0 (-1750.000000 600.000000) (-1600.000000 1100.000000); +Layer 51; +Rect R0.0 (-1750.000000 -1100.000000) (-1600.000000 -600.000000); +Layer 51; +Rect R180.0 (1600.000000 -1100.000000) (1750.000000 -600.000000); +Layer 51; +Rect R180.0 (1600.000000 600.000000) (1750.000000 1100.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1500.000000 2200.000000 -0 R0.0 'A' (-1550.000000 0.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1500.000000 2200.000000 -0 R0.0 'C' (1550.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1905.000000 1905.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1905.000000 -3175.000000); +Layer 51; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 101.600000 (1550.000000 -1350.000000) +0.000000 (1550.000000 -625.000000) +0.000000 (825.000000 -1350.000000) +0.000000 (1550.000000 -1350.000000) ; +Layer 21; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 101.600000 (1550.000000 -1350.000000) +0.000000 (1550.000000 -1175.000000) +0.000000 (1000.000000 -1175.000000) +0.000000 (825.000000 -1350.000000) +0.000000 (1550.000000 -1350.000000) ; +DESCRIPTION 'SURFACE MOUNT LED LAMP 3.5x2.8mm

\nSource: http://www.kingbright.com/manager/upload/pdf/KA-3528ASYC(Ver1189474662.1)'; + +Edit 'LD260.PAC'; +GRID mic; +Layer 21; +Wire 152.400000 (-1270.000000 -1270.000000) (0.000000 -1270.000000); +Layer 21; +Wire 152.400000 (0.000000 -1270.000000) (1270.000000 -1270.000000); +Layer 21; +Wire 152.400000 (1270.000000 1270.000000) (0.000000 1270.000000); +Layer 21; +Wire 152.400000 (0.000000 1270.000000) (-1270.000000 1270.000000); +Layer 21; +Wire 152.400000 (1270.000000 -1270.000000) (1270.000000 -889.000000); +Layer 21; +Wire 152.400000 (1270.000000 1270.000000) (1270.000000 889.000000); +Layer 51; +Wire 152.400000 (1270.000000 889.000000) (1270.000000 0.000000); +Layer 51; +Wire 152.400000 (1270.000000 0.000000) (1270.000000 -889.000000); +Layer 21; +Wire 152.400000 (-1270.000000 1270.000000) (-1270.000000 889.000000); +Layer 21; +Wire 152.400000 (-1270.000000 -1270.000000) (-1270.000000 -889.000000); +Layer 51; +Wire 152.400000 (-1270.000000 -889.000000) (-1270.000000 0.000000); +Layer 51; +Wire 152.400000 (-1270.000000 0.000000) (-1270.000000 889.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 1270.000000) -51.339230 (991.700000 793.400000); +Layer 21; +WIRE 152.400000 ROUND (-991.700000 793.400000) -51.339230 (0.000000 1270.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -1270.000000) +51.339230 (991.700000 -793.400000); +Layer 21; +WIRE 152.400000 ROUND (-991.700000 -793.400000) +51.339230 (0.000000 -1270.000000); +Layer 51; +WIRE 152.400000 ROUND (955.800000 -836.300000) +41.185419 (1270.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (975.600000 813.000000) -39.806332 (1269.900000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-1270.000000 0.000000) +40.600331 (-964.300000 -826.500000); +Layer 51; +WIRE 152.400000 ROUND (-1270.000000 0.000000) -40.600331 (-964.300000 826.500000); +Layer 51; +WIRE 152.400000 ROUND (-889.000000 0.000000) -90.000000 (0.000000 889.000000); +Layer 51; +WIRE 152.400000 ROUND (-508.000000 0.000000) -90.000000 (0.000000 508.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -508.000000) +90.000000 (508.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -889.000000) +90.000000 (889.000000 0.000000); +Layer 51; +Rect R0.0 (1270.000000 -635.000000) (2032.000000 635.000000); +Layer 21; +Rect R0.0 (1905.000000 -635.000000) (2032.000000 635.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'A' (-1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1295.400000 1473.200000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1270.000000 -2489.200000); +DESCRIPTION 'LED

\n5 mm, square, Siemens'; + +Edit 'LED2X5.PAC'; +GRID mic; +Layer 21; +Wire 152.400000 (-2540.000000 -1270.000000) (2540.000000 -1270.000000); +Layer 21; +Wire 152.400000 (2540.000000 1270.000000) (2540.000000 -1270.000000); +Layer 21; +Wire 152.400000 (2540.000000 1270.000000) (-2540.000000 1270.000000); +Layer 21; +Wire 152.400000 (-2540.000000 -1270.000000) (-2540.000000 1270.000000); +Layer 51; +Wire 152.400000 (-1905.000000 0.000000) (508.000000 0.000000); +Layer 51; +Wire 152.400000 (-508.000000 381.000000) (-508.000000 -381.000000); +Layer 51; +Wire 152.400000 (-508.000000 381.000000) (508.000000 0.000000); +Layer 51; +Wire 152.400000 (508.000000 0.000000) (1778.000000 0.000000); +Layer 51; +Wire 152.400000 (508.000000 0.000000) (-508.000000 -381.000000); +Layer 51; +Wire 152.400000 (508.000000 381.000000) (508.000000 0.000000); +Layer 51; +Wire 152.400000 (508.000000 0.000000) (508.000000 -381.000000); +Layer 51; +Wire 152.400000 (889.000000 -254.000000) (1143.000000 -762.000000); +Layer 51; +Wire 152.400000 (1143.000000 -762.000000) (1143.000000 -508.000000); +Layer 51; +Wire 152.400000 (1143.000000 -762.000000) (939.800000 -609.600000); +Layer 51; +Wire 152.400000 (939.800000 -609.600000) (1143.000000 -508.000000); +Layer 51; +Wire 152.400000 (1397.000000 -254.000000) (1651.000000 -762.000000); +Layer 51; +Wire 152.400000 (1651.000000 -762.000000) (1651.000000 -508.000000); +Layer 51; +Wire 152.400000 (1651.000000 -762.000000) (1447.800000 -609.600000); +Layer 51; +Wire 152.400000 (1447.800000 -609.600000) (1651.000000 -508.000000); +Layer 21; +Rect R0.0 (2159.000000 -1270.000000) (2413.000000 1270.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'A' (-1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-2540.000000 1397.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2540.000000 -2413.000000); +DESCRIPTION 'LED

\n2 x 5 mm, rectangle'; + +Edit 'LED3MM.PAC'; +GRID mic; +Layer 51; +Wire 254.000000 (1574.800000 -1270.000000) (1574.800000 1270.000000); +Layer 51; +WIRE 152.400000 ROUND (-1524.000000 0.000000) -39.803610 (-1170.800000 975.600000); +Layer 51; +WIRE 152.400000 ROUND (-1524.000000 0.000000) +41.633208 (-1139.100000 -1012.500000); +Layer 51; +WIRE 152.400000 ROUND (1157.100000 991.800000) -40.601165 (1524.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (1170.800000 -975.600000) +39.803610 (1524.000000 0.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 1524.000000) -54.461337 (1240.100000 885.800000); +Layer 21; +WIRE 152.400000 ROUND (-1219.200000 914.400000) -53.130102 (0.000000 1524.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -1524.000000) +52.126876 (1203.000000 -935.600000); +Layer 21; +WIRE 152.400000 ROUND (-1203.000000 -935.600000) +52.126876 (0.000000 -1524.000000); +Layer 51; +WIRE 152.400000 ROUND (-635.000000 0.000000) -90.000000 (0.000000 635.000000); +Layer 51; +WIRE 152.400000 ROUND (-1016.000000 0.000000) -90.000000 (0.000000 1016.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -635.000000) +90.000000 (635.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -1016.000000) +90.000000 (1016.000000 0.000000); +Layer 21; +WIRE 254.000000 ROUND (0.000000 2032.000000) -50.193108 (1561.000000 1300.900000); +Layer 21; +WIRE 254.000000 ROUND (-1792.900000 956.200000) -61.926949 (0.000000 2032.000000); +Layer 21; +WIRE 254.000000 ROUND (0.000000 -2032.000000) +49.763022 (1551.200000 -1312.600000); +Layer 21; +WIRE 254.000000 ROUND (-1764.300000 -1008.200000) +60.255215 (0.000000 -2032.000000); +Layer 51; +WIRE 254.000000 ROUND (-2032.000000 0.000000) -28.301701 (-1789.100000 963.400000); +Layer 51; +WIRE 254.000000 ROUND (-2032.000000 0.000000) +31.608220 (-1730.600000 -1065.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'A' (-1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (1905.000000 381.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (1905.000000 -1651.000000); +DESCRIPTION 'LED

\n3 mm, round'; + +Edit 'LED5MM.PAC'; +GRID mic; +Layer 21; +Circle 152.400000 (0.000000 0.000000) (2540.000000 0.000000); +Layer 21; +Wire 203.200000 (2540.000000 -1905.000000) (2540.000000 1905.000000); +Layer 21; +WIRE 254.000000 ROUND (2540.000000 -1905.000000) -286.260205 (2540.000000 1905.000000); +Layer 51; +WIRE 152.400000 ROUND (-1143.000000 0.000000) -90.000000 (0.000000 1143.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -1143.000000) +90.000000 (1143.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-1651.000000 0.000000) -90.000000 (0.000000 1651.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -1651.000000) +90.000000 (1651.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-2159.000000 0.000000) -90.000000 (0.000000 2159.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -2159.000000) +90.000000 (2159.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'A' (-1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (3175.000000 533.400000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (3200.400000 -1803.400000); +DESCRIPTION 'LED

\n5 mm, round'; + +Edit 'LED10MM.PAC'; +GRID mic; +Layer 21; +Circle 127.000000 (0.000000 0.000000) (5080.000000 0.000000); +Layer 21; +WIRE 254.000000 ROUND (5080.000000 -2540.000000) -306.869898 (5080.000000 2540.000000); +Layer 21; +WIRE 127.000000 ROUND (4445.000000 0.000000) -90.000000 (0.000000 -4445.000000); +Layer 21; +WIRE 127.000000 ROUND (3810.000000 0.000000) -90.000000 (0.000000 -3810.000000); +Layer 21; +WIRE 127.000000 ROUND (3175.000000 0.000000) -90.000000 (0.000000 -3175.000000); +Layer 21; +WIRE 127.000000 ROUND (2540.000000 0.000000) -90.000000 (0.000000 -2540.000000); +Layer 21; +WIRE 127.000000 ROUND (-4445.000000 0.000000) -90.000000 (0.000000 4445.000000); +Layer 21; +WIRE 127.000000 ROUND (-3810.000000 0.000000) -90.000000 (0.000000 3810.000000); +Layer 21; +WIRE 127.000000 ROUND (-3175.000000 0.000000) -90.000000 (0.000000 3175.000000); +Layer 21; +WIRE 127.000000 ROUND (-2540.000000 0.000000) -90.000000 (0.000000 2540.000000); +Layer 21; +Wire 254.000000 (5080.000000 2540.000000) (5080.000000 -2540.000000); +Change Drill 812.800000; +Pad 1676.400000 Octagon R0.0 'A' (-1270.000000 0.000000); +Change Drill 812.800000; +Pad 1676.400000 Square R0.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (6350.000000 1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (6350.000000 -1270.000000); +DESCRIPTION 'LED

\n10 mm, round'; + +Edit 'LSU260.PAC'; +GRID mic; +Layer 51; +Circle 152.400000 (0.000000 0.000000) (508.000000 0.000000); +Layer 51; +Wire 152.400000 (0.000000 -508.000000) (-1143.000000 -508.000000); +Layer 51; +Wire 152.400000 (-1143.000000 -508.000000) (-1143.000000 -254.000000); +Layer 51; +Wire 152.400000 (-1143.000000 508.000000) (0.000000 508.000000); +Layer 51; +Wire 152.400000 (-1143.000000 -254.000000) (-1397.000000 -254.000000); +Layer 51; +Wire 152.400000 (-1143.000000 -254.000000) (-1143.000000 254.000000); +Layer 51; +Wire 152.400000 (-1397.000000 -254.000000) (-1397.000000 254.000000); +Layer 51; +Wire 152.400000 (-1397.000000 254.000000) (-1143.000000 254.000000); +Layer 51; +Wire 152.400000 (-1143.000000 254.000000) (-1143.000000 508.000000); +Layer 51; +Wire 152.400000 (508.000000 -254.000000) (1397.000000 -254.000000); +Layer 51; +Wire 152.400000 (1397.000000 -254.000000) (1397.000000 254.000000); +Layer 51; +Wire 152.400000 (1397.000000 254.000000) (508.000000 254.000000); +Layer 21; +Wire 152.400000 (381.000000 -381.000000) (254.000000 -508.000000); +Layer 21; +Wire 152.400000 (254.000000 -508.000000) (-254.000000 -508.000000); +Layer 21; +Wire 152.400000 (-381.000000 -381.000000) (-254.000000 -508.000000); +Layer 21; +Wire 152.400000 (381.000000 381.000000) (254.000000 508.000000); +Layer 21; +Wire 152.400000 (254.000000 508.000000) (-254.000000 508.000000); +Layer 21; +Wire 152.400000 (-381.000000 381.000000) (-254.000000 508.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -254.000000) +90.000000 (254.000000 0.000000); +Layer 21; +WIRE 152.400000 ROUND (-254.000000 0.000000) -90.000000 (0.000000 254.000000); +Layer 21; +WIRE 152.400000 ROUND (381.000000 -381.000000) +90.000000 (381.000000 381.000000); +Layer 51; +Rect R0.0 (-1397.000000 -254.000000) (-1143.000000 254.000000); +Layer 51; +Rect R0.0 (508.000000 -254.000000) (1397.000000 254.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'A' (-1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1295.400000 838.200000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1270.000000 -1854.200000); +DESCRIPTION 'LED

\n1 mm, round, Siemens'; + +Edit 'LUMILED.PAC'; +GRID mic; +Layer 51; +Circle 203.200000 (0.000000 0.000000) (2725.000000 0.000000); +Layer 21; +Wire 203.200000 (-3575.000000 2337.500000) (-2337.500000 3575.000000); +Layer 21; +Wire 203.200000 (-2337.500000 3575.000000) (2337.500000 3575.000000); +Layer 21; +Wire 203.200000 (3575.000000 2337.500000) (3575.000000 -3575.000000); +Layer 21; +Wire 203.200000 (3575.000000 -3575.000000) (-2337.500000 -3575.000000); +Layer 21; +Wire 203.200000 (-2337.500000 -3575.000000) (-2500.000000 -3412.500000); +Layer 21; +WIRE 203.200000 ROUND (-2500.000000 -3412.500000) +167.429893 (-3412.500000 -2500.000000); +Layer 21; +Wire 203.200000 (-3412.500000 -2500.000000) (-3575.000000 -2337.500000); +Layer 21; +Wire 203.200000 (-3575.000000 -2337.500000) (-3575.000000 2337.500000); +Layer 21; +Wire 203.200000 (2337.500000 3575.000000) (2500.000000 3412.500000); +Layer 21; +WIRE 203.200000 ROUND (2500.000000 3412.500000) +167.429893 (3412.500000 2500.000000); +Layer 21; +Wire 203.200000 (3412.500000 2500.000000) (3575.000000 2337.500000); +Layer 21; +WIRE 203.200000 ROUND (-1725.000000 2225.000000) -255.449990 (-1062.500000 2562.500000); +Layer 21; +WIRE 203.200000 ROUND (1725.000000 -2225.000000) -255.449990 (1062.500000 -2562.500000); +Layer 51; +Rect R0.0 (-5975.000000 575.000000) (-3625.000000 1600.000000); +Layer 51; +Rect R0.0 (-5975.000000 -1600.000000) (-3625.000000 -575.000000); +Layer 51; +Rect R180.0 (3625.000000 -1600.000000) (5975.000000 -575.000000); +Layer 51; +Rect R180.0 (3625.000000 575.000000) (5975.000000 1600.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2900.000000 1700.000000 -0 R0.0 '1NC' (-5200.000000 1150.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2900.000000 1700.000000 -0 R0.0 '2+' (-5200.000000 -1150.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2900.000000 1700.000000 -0 R180.0 '3NC' (5200.000000 -1150.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2900.000000 1700.000000 -0 R180.0 '4-' (5200.000000 1150.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-3175.000000 3810.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-3175.000000 -5080.000000); +Layer 29; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 406.400000 (2338.300000 1350.000000) +0.000000 (0.000000 2700.000000) +0.000000 (-2338.300000 1350.000000) +0.000000 (-2338.300000 -1350.000000) +0.000000 (0.000000 -2700.000000) +0.000000 (2338.300000 -1350.000000) +0.000000 (2338.300000 1350.000000) ; +Layer 31; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 406.400000 (2338.300000 1350.000000) +0.000000 (0.000000 2700.000000) +0.000000 (-2338.300000 1350.000000) +0.000000 (-2338.300000 -1350.000000) +0.000000 (0.000000 -2700.000000) +0.000000 (2338.300000 -1350.000000) +0.000000 (2338.300000 1350.000000) ; +DESCRIPTION 'Lumileds Lighting. LUXEON® without cool pad

\nSource: K2.pdf'; + +Edit 'LUMILED+.PAC'; +GRID mic; +Layer 51; +Circle 203.200000 (0.000000 0.000000) (2725.000000 0.000000); +Layer 21; +Wire 203.200000 (-3575.000000 2337.500000) (-2337.500000 3575.000000); +Layer 21; +Wire 203.200000 (-2337.500000 3575.000000) (2337.500000 3575.000000); +Layer 21; +Wire 203.200000 (3575.000000 2337.500000) (3575.000000 -3575.000000); +Layer 21; +Wire 203.200000 (3575.000000 -3575.000000) (-2337.500000 -3575.000000); +Layer 21; +Wire 203.200000 (-2337.500000 -3575.000000) (-2500.000000 -3412.500000); +Layer 21; +WIRE 203.200000 ROUND (-2500.000000 -3412.500000) +167.429893 (-3412.500000 -2500.000000); +Layer 21; +Wire 203.200000 (-3412.500000 -2500.000000) (-3575.000000 -2337.500000); +Layer 21; +Wire 203.200000 (-3575.000000 -2337.500000) (-3575.000000 2337.500000); +Layer 21; +Wire 203.200000 (2337.500000 3575.000000) (2500.000000 3412.500000); +Layer 21; +WIRE 203.200000 ROUND (2500.000000 3412.500000) +167.429893 (3412.500000 2500.000000); +Layer 21; +Wire 203.200000 (3412.500000 2500.000000) (3575.000000 2337.500000); +Layer 21; +WIRE 203.200000 ROUND (-1725.000000 2225.000000) -255.449990 (-1062.500000 2562.500000); +Layer 21; +WIRE 203.200000 ROUND (1725.000000 -2225.000000) -255.449990 (1062.500000 -2562.500000); +Layer 51; +Rect R0.0 (-5975.000000 575.000000) (-3625.000000 1600.000000); +Layer 51; +Rect R0.0 (-5975.000000 -1600.000000) (-3625.000000 -575.000000); +Layer 51; +Rect R180.0 (3625.000000 -1600.000000) (5975.000000 -575.000000); +Layer 51; +Rect R180.0 (3625.000000 575.000000) (5975.000000 1600.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2900.000000 1700.000000 -0 R0.0 '1NC' (-5200.000000 1150.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2900.000000 1700.000000 -0 R0.0 '2+' (-5200.000000 -1150.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2900.000000 1700.000000 -0 R180.0 '3NC' (5200.000000 -1150.000000); +Layer 1; +CHANGE Roundness 0; +SMD 2900.000000 1700.000000 -0 R180.0 '4-' (5200.000000 1150.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-3175.000000 3810.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-3175.000000 -5080.000000); +Layer 1; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 406.400000 (2338.300000 1350.000000) +0.000000 (0.000000 2700.000000) +0.000000 (-2338.300000 1350.000000) +0.000000 (-2338.300000 -1350.000000) +0.000000 (0.000000 -2700.000000) +0.000000 (2338.300000 -1350.000000) +0.000000 (2338.300000 1350.000000) ; +Layer 29; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 406.400000 (2338.300000 1350.000000) +0.000000 (0.000000 2700.000000) +0.000000 (-2338.300000 1350.000000) +0.000000 (-2338.300000 -1350.000000) +0.000000 (0.000000 -2700.000000) +0.000000 (2338.300000 -1350.000000) +0.000000 (2338.300000 1350.000000) ; +Layer 31; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 406.400000 (2338.300000 1350.000000) +0.000000 (0.000000 2700.000000) +0.000000 (-2338.300000 1350.000000) +0.000000 (-2338.300000 -1350.000000) +0.000000 (0.000000 -2700.000000) +0.000000 (2338.300000 -1350.000000) +0.000000 (2338.300000 1350.000000) ; +DESCRIPTION 'Lumileds Lighting. LUXEON® with cool pad

\nSource: K2.pdf'; + +Edit 'LZR181.PAC'; +GRID mic; +Layer 21; +Wire 152.400000 (-1270.000000 -1270.000000) (1270.000000 -1270.000000); +Layer 21; +Wire 152.400000 (1270.000000 -1270.000000) (1270.000000 -889.000000); +Layer 21; +Wire 152.400000 (1270.000000 1270.000000) (1270.000000 889.000000); +Layer 51; +Wire 152.400000 (1270.000000 889.000000) (1270.000000 -889.000000); +Layer 21; +Wire 152.400000 (-1270.000000 1270.000000) (-1270.000000 889.000000); +Layer 21; +Wire 152.400000 (-1270.000000 -1270.000000) (-1270.000000 -889.000000); +Layer 51; +Wire 152.400000 (-1270.000000 -889.000000) (-1270.000000 889.000000); +Layer 51; +WIRE 152.400000 ROUND (-889.000000 0.000000) -90.000000 (0.000000 889.000000); +Layer 51; +WIRE 152.400000 ROUND (-508.000000 0.000000) -90.000000 (0.000000 508.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -508.000000) +90.000000 (508.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -889.000000) +90.000000 (889.000000 0.000000); +Layer 21; +WIRE 152.400000 ROUND (-867.800000 743.900000) -49.396139 (0.000000 1143.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 1143.000000) -49.396139 (867.800000 743.900000); +Layer 21; +WIRE 152.400000 ROUND (-867.800000 -743.900000) +49.396139 (0.000000 -1143.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -1143.000000) +49.396139 (867.800000 -743.900000); +Layer 51; +WIRE 152.400000 ROUND (867.800000 743.900000) -40.604135 (1143.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (867.800000 -743.900000) +40.604135 (1143.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-1143.000000 0.000000) -40.604135 (-867.800000 743.900000); +Layer 51; +WIRE 152.400000 ROUND (-1143.000000 0.000000) +40.604135 (-867.800000 -743.900000); +Layer 21; +Wire 152.400000 (-1270.000000 1270.000000) (1270.000000 1270.000000); +Layer 51; +Rect R0.0 (1270.000000 -889.000000) (1524.000000 254.000000); +Layer 51; +Rect R0.0 (-1524.000000 -254.000000) (-1270.000000 254.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'A' (-1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Octagon R0.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1295.400000 1473.200000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1270.000000 -2489.200000); +DESCRIPTION 'LED BLOCK

\n1 LED, Siemens'; + +Edit 'MICRO-SIDELED.PAC'; +GRID mic; +Layer 51; +Wire 101.600000 (650.000000 1100.000000) (-100.000000 1100.000000); +Layer 51; +Wire 101.600000 (-100.000000 1100.000000) (-350.000000 1000.000000); +Layer 21; +Wire 101.600000 (-350.000000 1000.000000) (-350.000000 -900.000000); +Layer 51; +Wire 101.600000 (-350.000000 -900.000000) (-100.000000 -1100.000000); +Layer 51; +Wire 101.600000 (-100.000000 -1100.000000) (650.000000 -1100.000000); +Layer 21; +Wire 101.600000 (650.000000 -1100.000000) (650.000000 1100.000000); +Layer 21; +Wire 50.800000 (600.000000 900.000000) (250.000000 700.000000); +Layer 21; +Wire 50.800000 (250.000000 700.000000) (250.000000 -700.000000); +Layer 21; +Wire 50.800000 (250.000000 -700.000000) (600.000000 -900.000000); +Layer 29; +Rect R0.0 (-400.000000 1100.000000) (400.000000 1800.000000); +Layer 29; +Rect R0.0 (-400.000000 -1800.000000) (400.000000 -1100.000000); +Layer 31; +Rect R0.0 (-350.000000 -1750.000000) (350.000000 -1150.000000); +Layer 31; +Rect R0.0 (-350.000000 1150.000000) (350.000000 1750.000000); +Layer 51; +Rect R0.0 (-125.000000 1125.000000) (125.000000 1750.000000); +Layer 51; +Rect R0.0 (-125.000000 -1750.000000) (125.000000 -1125.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1600.000000 1600.000000 -0 R0.0 NOSTOP NOCREAM 'A' (0.000000 1950.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1600.000000 1600.000000 -0 R0.0 NOSTOP NOCREAM 'C' (0.000000 -1950.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-1270.000000 -1905.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (2540.000000 -1905.000000); +DESCRIPTION 'Hyper Micro SIDELED®

\nSource: http://www.osram.convergy.de/ ... LA_LO_LS_LY Y876.pdf'; + +Edit 'MINI-TOPLED-SANTANA.PAC'; +GRID mic; +Layer 21; +Wire 101.600000 (700.000000 -1000.000000) (350.000000 -1000.000000); +Layer 21; +Wire 101.600000 (350.000000 -1000.000000) (-700.000000 -1000.000000); +Layer 21; +Wire 101.600000 (-700.000000 -1000.000000) (-700.000000 1000.000000); +Layer 21; +Wire 101.600000 (-700.000000 1000.000000) (700.000000 1000.000000); +Layer 21; +Wire 101.600000 (700.000000 1000.000000) (700.000000 -650.000000); +Layer 21; +Wire 101.600000 (700.000000 -650.000000) (700.000000 -1000.000000); +Layer 21; +Wire 101.600000 (450.000000 -700.000000) (-450.000000 -700.000000); +Layer 21; +Wire 101.600000 (-450.000000 -700.000000) (-450.000000 700.000000); +Layer 21; +Wire 101.600000 (-450.000000 700.000000) (450.000000 700.000000); +Layer 21; +Wire 101.600000 (450.000000 700.000000) (450.000000 -700.000000); +Layer 21; +Wire 101.600000 (700.000000 -650.000000) (350.000000 -1000.000000); +Layer 29; +Rect R0.0 (-550.000000 1500.000000) (550.000000 2100.000000); +Layer 29; +Rect R0.0 (-550.000000 -2100.000000) (550.000000 -1500.000000); +Layer 31; +Rect R0.0 (-500.000000 -2050.000000) (500.000000 -1550.000000); +Layer 31; +Rect R0.0 (-500.000000 1550.000000) (500.000000 2050.000000); +Layer 21; +Rect R0.0 (-200.000000 -400.000000) (150.000000 -50.000000); +Layer 51; +Rect R0.0 (-500.000000 -2100.000000) (500.000000 -1400.000000); +Layer 51; +Rect R0.0 (-500.000000 1400.000000) (500.000000 2050.000000); +Layer 21; +Rect R0.0 (-500.000000 1000.000000) (500.000000 1400.000000); +Layer 21; +Rect R0.0 (-500.000000 -1400.000000) (500.000000 -1050.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1600.000000 1600.000000 -0 R0.0 NOSTOP NOCREAM 'A' (0.000000 2200.000000); +Layer 1; +CHANGE Roundness 0; +SMD 1600.000000 1600.000000 -0 R0.0 NOSTOP NOCREAM 'C' (0.000000 -2200.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-1270.000000 -1905.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (2540.000000 -1905.000000); +Change Drill 2700.000000; +Hole (0.000000 0.000000); +DESCRIPTION 'Mini TOPLED Santana®

\nSource: http://www.osram.convergy.de/ ... LG M470.pdf'; + +Edit 'OSRAM-MINI-TOP-LED.PAC'; +GRID mic; +Layer 51; +Wire 101.600000 (-600.000000 900.000000) (-600.000000 -700.000000); +Layer 51; +Wire 101.600000 (-450.000000 -900.000000) (-400.000000 -900.000000); +Layer 51; +Wire 101.600000 (-400.000000 -900.000000) (600.000000 -900.000000); +Layer 51; +Wire 101.600000 (600.000000 -900.000000) (600.000000 900.000000); +Layer 51; +Wire 101.600000 (600.000000 900.000000) (-600.000000 900.000000); +Layer 51; +Wire 101.600000 (-450.000000 950.000000) (-450.000000 1100.000000); +Layer 51; +Wire 101.600000 (-450.000000 1100.000000) (450.000000 1100.000000); +Layer 51; +Wire 101.600000 (450.000000 1100.000000) (450.000000 950.000000); +Layer 51; +Wire 101.600000 (-600.000000 -700.000000) (-400.000000 -900.000000); +Layer 51; +Wire 101.600000 (-450.000000 -900.000000) (-450.000000 -1100.000000); +Layer 51; +Wire 101.600000 (-450.000000 -1100.000000) (450.000000 -1100.000000); +Layer 51; +Wire 101.600000 (450.000000 -1100.000000) (450.000000 -950.000000); +Layer 29; +Rect R0.0 (-500.000000 600.000000) (500.000000 1400.000000); +Layer 29; +Rect R0.0 (-500.000000 -1400.000000) (500.000000 -600.000000); +Layer 51; +Rect R0.0 (-150.000000 -600.000000) (150.000000 -300.000000); +Layer 31; +Rect R0.0 (-450.000000 650.000000) (450.000000 1350.000000); +Layer 31; +Rect R0.0 (-450.000000 -1350.000000) (450.000000 -650.000000); +Layer 1; +CHANGE Roundness 0; +SMD 4000.000000 4000.000000 -0 R0.0 NOSTOP NOCREAM 'A' (0.000000 2600.000000); +Layer 1; +CHANGE Roundness 0; +SMD 4000.000000 4000.000000 -0 R0.0 NOSTOP NOCREAM 'C' (0.000000 -2600.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'A' (-635.000000 1905.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'C' (-635.000000 -3175.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-2540.000000 -1905.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (3810.000000 -1905.000000); +DESCRIPTION 'BLUE LINETM Hyper Mini TOPLED® Hyper-Bright LED

\nSource: http://www.osram.convergy.de/ ... LB M676.pdf'; + +Edit 'OSRAM-SIDELED.PAC'; +GRID mic; +Layer 51; +Wire 101.600000 (-1850.000000 -2050.000000) (-1850.000000 -750.000000); +Layer 51; +Wire 101.600000 (-1850.000000 -750.000000) (-1700.000000 -750.000000); +Layer 51; +Wire 101.600000 (-1700.000000 -750.000000) (-1700.000000 750.000000); +Layer 51; +Wire 101.600000 (-1700.000000 750.000000) (-1850.000000 750.000000); +Layer 51; +Wire 101.600000 (-1850.000000 750.000000) (-1850.000000 2050.000000); +Layer 51; +Wire 101.600000 (-1850.000000 2050.000000) (900.000000 2050.000000); +Layer 51; +Wire 101.600000 (900.000000 2050.000000) (900.000000 -2050.000000); +Layer 51; +Wire 101.600000 (900.000000 -2050.000000) (-1850.000000 -2050.000000); +Layer 51; +Wire 101.600000 (900.000000 -2050.000000) (1050.000000 -2050.000000); +Layer 51; +Wire 101.600000 (1050.000000 -2050.000000) (1850.000000 -1850.000000); +Layer 51; +Wire 101.600000 (1850.000000 -1850.000000) (1850.000000 1850.000000); +Layer 51; +Wire 101.600000 (1850.000000 1850.000000) (1050.000000 2050.000000); +Layer 51; +Wire 101.600000 (1050.000000 2050.000000) (900.000000 2050.000000); +Layer 51; +Wire 101.600000 (1050.000000 2050.000000) (1050.000000 -2050.000000); +Layer 51; +WIRE 101.600000 ROUND (-550.000000 -900.000000) -167.319617 (-550.000000 900.000000); +Layer 51; +Wire 101.600000 (-550.000000 -900.000000) (850.000000 -1200.000000); +Layer 51; +Wire 101.600000 (-550.000000 900.000000) (850.000000 1200.000000); +Layer 29; +Rect R0.0 (-2100.000000 -2200.000000) (2100.000000 -400.000000); +Layer 29; +Rect R0.0 (-2100.000000 400.000000) (2100.000000 2200.000000); +Layer 31; +Rect R0.0 (-1900.000000 -2100.000000) (1900.000000 -600.000000); +Layer 31; +Rect R0.0 (-1900.000000 600.000000) (1900.000000 2100.000000); +Layer 51; +Rect R0.0 (-1850.000000 -2050.000000) (-700.000000 -1000.000000); +Layer 1; +CHANGE Roundness 0; +SMD 4000.000000 4000.000000 -0 R0.0 NOSTOP NOCREAM 'A' (0.000000 2500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 4000.000000 4000.000000 -0 R0.0 NOSTOP NOCREAM 'C' (0.000000 -2500.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 'C' (635.000000 -3175.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 'A' (635.000000 2540.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-2540.000000 -2540.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (3810.000000 -2540.000000); +DESCRIPTION 'Super SIDELED® High-Current LED

\nLG A672, LP A672
\nSource: http://www.osram.convergy.de/ ... LG_LP_A672.pdf (2004.05.13)'; + +Edit 'P-LCC-2.PAC'; +GRID mic; +Layer 51; +Circle 203.200000 (0.000000 0.000000) (1100.000000 0.000000); +Layer 51; +Wire 203.200000 (-1400.000000 -1050.000000) (-1400.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-1400.000000 -1600.000000) (-1100.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-1100.000000 -1600.000000) (-850.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-850.000000 -1600.000000) (1100.000000 -1600.000000); +Layer 51; +Wire 203.200000 (1100.000000 -1600.000000) (1400.000000 -1600.000000); +Layer 51; +Wire 203.200000 (1400.000000 -1600.000000) (1400.000000 1600.000000); +Layer 51; +Wire 203.200000 (1400.000000 1600.000000) (1100.000000 1600.000000); +Layer 51; +Wire 203.200000 (1100.000000 1600.000000) (-1100.000000 1600.000000); +Layer 51; +Wire 203.200000 (-1100.000000 1600.000000) (-1400.000000 1600.000000); +Layer 51; +Wire 101.600000 (-1100.000000 1600.000000) (-1100.000000 1800.000000); +Layer 51; +Wire 101.600000 (-1100.000000 1800.000000) (1100.000000 1800.000000); +Layer 51; +Wire 101.600000 (1100.000000 1800.000000) (1100.000000 1600.000000); +Layer 51; +Wire 101.600000 (-1100.000000 -1600.000000) (-1100.000000 -1800.000000); +Layer 51; +Wire 101.600000 (-1100.000000 -1800.000000) (1100.000000 -1800.000000); +Layer 51; +Wire 101.600000 (1100.000000 -1800.000000) (1100.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-850.000000 -1600.000000) (-1400.000000 -1050.000000); +Layer 51; +Wire 203.200000 (-1400.000000 1600.000000) (-1400.000000 -1050.000000); +Layer 31; +Rect R0.0 (-1300.000000 -2250.000000) (1300.000000 -750.000000); +Layer 31; +Rect R0.0 (-1300.000000 750.000000) (1300.000000 2250.000000); +Layer 21; +Rect R0.0 (-250.000000 -250.000000) (250.000000 250.000000); +Layer 29; +Rect R0.0 (-1400.000000 650.000000) (1400.000000 2350.000000); +Layer 29; +Rect R0.0 (-1400.000000 -2350.000000) (1400.000000 -650.000000); +Layer 1; +CHANGE Roundness 0; +SMD 4000.000000 4000.000000 -0 R0.0 NOSTOP NOCREAM 'A' (0.000000 2750.000000); +Layer 1; +CHANGE Roundness 0; +SMD 4000.000000 4000.000000 -0 R0.0 NOSTOP NOCREAM 'C' (0.000000 -2750.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-2540.000000 -1905.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (3810.000000 -1905.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'A' (-635.000000 2540.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'C' (-635.000000 -3810.000000); +DESCRIPTION 'TOPLED® High-optical Power LED (HOP)

\nSource: http://www.osram.convergy.de/ ... ls_t675.pdf'; + +Edit 'P-LCC-2-TOPLED-RG.PAC'; +GRID mic; +Layer 21; +Circle 203.200000 (0.000000 0.000000) (1100.000000 0.000000); +Layer 51; +Wire 203.200000 (-1400.000000 -1050.000000) (-1400.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-1400.000000 -1600.000000) (-1100.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-1100.000000 -1600.000000) (-850.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-850.000000 -1600.000000) (1100.000000 -1600.000000); +Layer 51; +Wire 203.200000 (1100.000000 -1600.000000) (1400.000000 -1600.000000); +Layer 51; +Wire 203.200000 (1400.000000 -1600.000000) (1400.000000 1600.000000); +Layer 51; +Wire 203.200000 (1400.000000 1600.000000) (1100.000000 1600.000000); +Layer 51; +Wire 203.200000 (1100.000000 1600.000000) (-1100.000000 1600.000000); +Layer 51; +Wire 203.200000 (-1100.000000 1600.000000) (-1400.000000 1600.000000); +Layer 51; +Wire 101.600000 (-1100.000000 1600.000000) (-1100.000000 2450.000000); +Layer 51; +Wire 101.600000 (1100.000000 2450.000000) (1100.000000 1600.000000); +Layer 51; +Wire 101.600000 (-1100.000000 -1600.000000) (-1100.000000 -2450.000000); +Layer 51; +Wire 101.600000 (1100.000000 -2450.000000) (1100.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-850.000000 -1600.000000) (-1400.000000 -1050.000000); +Layer 51; +Wire 203.200000 (-1400.000000 1600.000000) (-1400.000000 -1050.000000); +Layer 31; +Rect R0.0 (-1300.000000 -3000.000000) (1300.000000 -1500.000000); +Layer 31; +Rect R0.0 (-1300.000000 1500.000000) (1300.000000 3000.000000); +Layer 21; +Rect R0.0 (-250.000000 -250.000000) (250.000000 250.000000); +Layer 51; +Rect R0.0 (-1150.000000 2400.000000) (1150.000000 2700.000000); +Layer 51; +Rect R0.0 (-1150.000000 -2700.000000) (1150.000000 -2400.000000); +Layer 29; +Rect R0.0 (-1500.000000 1500.000000) (1500.000000 3200.000000); +Layer 29; +Rect R0.0 (-1500.000000 -3200.000000) (1500.000000 -1500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 4000.000000 4000.000000 -0 R0.0 NOSTOP NOCREAM 'A' (0.000000 3500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 4000.000000 4000.000000 -0 R0.0 NOSTOP NOCREAM 'C' (0.000000 -3500.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-2540.000000 -1905.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (3810.000000 -1905.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'A' (-635.000000 3290.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'C' (-635.000000 -4560.000000); +Change Drill 2800.000000; +Hole (0.000000 0.000000); +DESCRIPTION 'Hyper TOPLED® RG Hyper-Bright LED

\nSource: http://www.osram.convergy.de/ ... LA_LO_LS_LY T776.pdf'; + +Edit 'P-LCC-4.PAC'; +GRID mic; +Layer 51; +Circle 203.200000 (0.000000 0.000000) (1100.000000 0.000000); +Layer 51; +Wire 203.200000 (-1400.000000 -1050.000000) (-1400.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-1400.000000 -1600.000000) (-1000.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-1000.000000 -1600.000000) (-850.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-850.000000 -1600.000000) (1000.000000 -1600.000000); +Layer 51; +Wire 203.200000 (1000.000000 -1600.000000) (1400.000000 -1600.000000); +Layer 51; +Wire 203.200000 (1400.000000 -1600.000000) (1400.000000 1600.000000); +Layer 51; +Wire 203.200000 (1400.000000 1600.000000) (1100.000000 1600.000000); +Layer 51; +Wire 203.200000 (1100.000000 1600.000000) (-1000.000000 1600.000000); +Layer 51; +Wire 203.200000 (-1000.000000 1600.000000) (-1400.000000 1600.000000); +Layer 51; +Wire 101.600000 (-1000.000000 1600.000000) (-1000.000000 1800.000000); +Layer 51; +Wire 101.600000 (-1000.000000 1800.000000) (-500.000000 1800.000000); +Layer 51; +Wire 101.600000 (-500.000000 1800.000000) (-500.000000 1650.000000); +Layer 51; +Wire 101.600000 (500.000000 1650.000000) (500.000000 1800.000000); +Layer 51; +Wire 101.600000 (500.000000 1800.000000) (1100.000000 1800.000000); +Layer 51; +Wire 101.600000 (1100.000000 1800.000000) (1100.000000 1600.000000); +Layer 51; +Wire 101.600000 (-1000.000000 -1600.000000) (-1000.000000 -1800.000000); +Layer 51; +Wire 101.600000 (-1000.000000 -1800.000000) (-500.000000 -1800.000000); +Layer 51; +Wire 101.600000 (-500.000000 -1800.000000) (-500.000000 -1650.000000); +Layer 51; +Wire 101.600000 (500.000000 -1650.000000) (500.000000 -1800.000000); +Layer 51; +Wire 101.600000 (500.000000 -1800.000000) (1000.000000 -1800.000000); +Layer 51; +Wire 101.600000 (1000.000000 -1800.000000) (1000.000000 -1600.000000); +Layer 51; +Wire 203.200000 (-850.000000 -1600.000000) (-1400.000000 -1050.000000); +Layer 51; +Wire 203.200000 (-1400.000000 1600.000000) (-1400.000000 -1050.000000); +Layer 29; +Rect R0.0 (-1150.000000 750.000000) (-350.000000 1850.000000); +Layer 29; +Rect R0.0 (350.000000 750.000000) (1150.000000 1850.000000); +Layer 29; +Rect R0.0 (350.000000 -1850.000000) (1150.000000 -750.000000); +Layer 29; +Rect R0.0 (-1150.000000 -1850.000000) (-350.000000 -750.000000); +Layer 31; +Rect R0.0 (-1100.000000 -1800.000000) (-400.000000 -800.000000); +Layer 31; +Rect R0.0 (400.000000 -1800.000000) (1100.000000 -800.000000); +Layer 31; +Rect R0.0 (400.000000 800.000000) (1100.000000 1800.000000); +Layer 31; +Rect R0.0 (-1100.000000 800.000000) (-400.000000 1800.000000); +Layer 21; +Rect R0.0 (-200.000000 -200.000000) (200.000000 200.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3300.000000 4800.000000 -0 R0.0 NOSTOP NOCREAM 'A' (-2000.000000 3150.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3300.000000 4800.000000 -0 R0.0 NOSTOP NOCREAM 'C@1' (-2000.000000 -3150.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3300.000000 4800.000000 -0 R0.0 NOSTOP NOCREAM 'C@3' (2000.000000 3150.000000); +Layer 1; +CHANGE Roundness 0; +SMD 3300.000000 4800.000000 -0 R0.0 NOSTOP NOCREAM 'C@4' (2000.000000 -3150.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-3810.000000 -2540.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (5080.000000 -2540.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'C' (-1905.000000 -3810.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'A' (-1905.000000 2540.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'C' (1270.000000 2540.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'C' (1270.000000 -3810.000000); +DESCRIPTION 'Power TOPLED®

\nSource: http://www.osram.convergy.de/ ... LA_LO_LA_LY E67B.pdf'; + +Edit 'Q62902-B152.PAC'; +GRID mic; +Layer 21; +Wire 152.400000 (-2971.800000 -1854.200000) (-2971.800000 -254.000000); +Layer 21; +Wire 152.400000 (-2971.800000 -254.000000) (-2971.800000 254.000000); +Layer 21; +Wire 152.400000 (-2971.800000 254.000000) (-2971.800000 1854.200000); +Layer 21; +Wire 152.400000 (2971.800000 -1854.200000) (-2108.200000 -1854.200000); +Layer 21; +Wire 152.400000 (-2108.200000 -1854.200000) (-2540.000000 -1854.200000); +Layer 21; +Wire 152.400000 (-2540.000000 1854.200000) (-2108.200000 1854.200000); +Layer 21; +Wire 152.400000 (-2108.200000 1854.200000) (2971.800000 1854.200000); +Layer 21; +Wire 152.400000 (-2540.000000 -1854.200000) (-2540.000000 1854.200000); +Layer 21; +Wire 152.400000 (-2540.000000 -1854.200000) (-2971.800000 -1854.200000); +Layer 21; +Wire 152.400000 (-2540.000000 1854.200000) (-2971.800000 1854.200000); +Layer 21; +WIRE 152.400000 ROUND (-2971.800000 254.000000) +180.000000 (-2971.800000 -254.000000); +Layer 21; +WIRE 152.400000 ROUND (-1148.600000 881.400000) -52.498642 (0.000000 1447.800000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 1447.800000) -52.433716 (1147.600000 882.700000); +Layer 21; +WIRE 152.400000 ROUND (-1135.100000 -898.700000) +51.629985 (0.000000 -1447.800000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -1447.800000) +51.339172 (1130.500000 -904.400000); +Layer 51; +WIRE 152.400000 ROUND (1128.100000 -907.400000) +38.811177 (1447.800000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (1140.100000 892.300000) -38.048073 (1447.800000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-1447.800000 0.000000) +38.659064 (-1130.500000 -904.400000); +Layer 51; +WIRE 152.400000 ROUND (-1447.800000 0.000000) -37.696376 (-1145.600000 885.300000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 1701.800000) -59.573488 (1467.400000 861.800000); +Layer 21; +WIRE 152.400000 ROUND (-1461.800000 871.400000) -59.200638 (0.000000 1701.800000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -1701.800000) +58.891781 (1457.100000 -879.300000); +Layer 21; +WIRE 152.400000 ROUND (-1457.100000 -879.300000) +58.891781 (0.000000 -1701.800000); +Layer 51; +WIRE 152.400000 ROUND (-1701.800000 0.000000) -31.907626 (-1444.700000 899.500000); +Layer 51; +WIRE 152.400000 ROUND (-1701.800000 0.000000) +31.551992 (-1450.200000 -890.500000); +Layer 51; +WIRE 152.400000 ROUND (1452.100000 887.400000) -31.429586 (1701.800000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (1445.900000 -897.500000) +31.828757 (1701.800000 0.000000); +Layer 21; +Wire 152.400000 (-2108.200000 1854.200000) (-2108.200000 -1854.200000); +Layer 21; +WIRE 152.400000 ROUND (-635.000000 0.000000) -90.000000 (0.000000 635.000000); +Layer 51; +WIRE 152.400000 ROUND (-1016.000000 0.000000) -90.000000 (0.000000 1016.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -635.000000) +90.000000 (635.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (53.900000 -1069.900000) +90.000000 (1069.900000 -53.900000); +Layer 21; +Wire 152.400000 (2971.800000 1854.200000) (2971.800000 -1854.200000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'A' (1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'K' (-1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1905.000000 2286.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1905.000000 -3556.000000); +DESCRIPTION 'LED HOLDER

\nSiemens'; + +Edit 'Q62902-B153.PAC'; +GRID mic; +Layer 21; +Circle 152.400000 (0.000000 0.000000) (2540.000000 0.000000); +Layer 21; +Circle 254.000000 (0.000000 0.000000) (3175.000000 0.000000); +Layer 21; +Wire 152.400000 (-5511.800000 -3505.200000) (-5511.800000 -254.000000); +Layer 21; +Wire 152.400000 (-5511.800000 -254.000000) (-5511.800000 254.000000); +Layer 21; +Wire 152.400000 (-5511.800000 254.000000) (-5511.800000 3505.200000); +Layer 21; +Wire 152.400000 (5511.800000 -3505.200000) (-4648.200000 -3505.200000); +Layer 21; +Wire 152.400000 (-4648.200000 -3505.200000) (-5080.000000 -3505.200000); +Layer 21; +Wire 152.400000 (-5080.000000 3505.200000) (-4648.200000 3505.200000); +Layer 21; +Wire 152.400000 (-4648.200000 3505.200000) (5511.800000 3505.200000); +Layer 21; +Wire 152.400000 (-5080.000000 -3505.200000) (-5080.000000 3505.200000); +Layer 21; +Wire 152.400000 (-5080.000000 -3505.200000) (-5511.800000 -3505.200000); +Layer 21; +Wire 152.400000 (-5080.000000 3505.200000) (-5511.800000 3505.200000); +Layer 21; +WIRE 152.400000 ROUND (-5511.800000 254.000000) +180.000000 (-5511.800000 -254.000000); +Layer 21; +Wire 152.400000 (-4648.200000 3505.200000) (-4648.200000 -3505.200000); +Layer 21; +Wire 152.400000 (5511.800000 3505.200000) (5511.800000 -3505.200000); +Layer 21; +Wire 254.000000 (-2540.000000 1905.000000) (-2540.000000 -1905.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -1143.000000) +90.000000 (1143.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-1143.000000 0.000000) -90.000000 (0.000000 1143.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -1651.000000) +90.000000 (1651.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-1651.000000 0.000000) -90.000000 (0.000000 1651.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -2159.000000) +90.000000 (2159.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-2212.900000 53.900000) -90.010616 (-53.900000 2212.900000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'A' (1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'K' (-1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-4191.000000 3937.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-4318.000000 -5080.000000); +DESCRIPTION 'LED HOLDER

\nSiemens'; + +Edit 'Q62902-B155.PAC'; +GRID mic; +Layer 21; +Wire 152.400000 (-1270.000000 -3048.000000) (-1270.000000 -2540.000000); +Layer 21; +Wire 152.400000 (10033.000000 3048.000000) (2921.000000 3048.000000); +Layer 21; +Wire 152.400000 (10033.000000 3048.000000) (10033.000000 -3048.000000); +Layer 21; +Wire 152.400000 (-1270.000000 -3048.000000) (2921.000000 -3048.000000); +Layer 21; +Wire 152.400000 (2921.000000 -3048.000000) (2921.000000 3048.000000); +Layer 21; +Wire 152.400000 (2921.000000 -3048.000000) (10033.000000 -3048.000000); +Layer 21; +Wire 152.400000 (2921.000000 3048.000000) (-1270.000000 3048.000000); +Layer 21; +Wire 152.400000 (-1270.000000 2540.000000) (-5207.000000 2540.000000); +Layer 21; +Wire 152.400000 (-1270.000000 2540.000000) (-1270.000000 3048.000000); +Layer 21; +Wire 152.400000 (-5207.000000 -2540.000000) (-1270.000000 -2540.000000); +Layer 21; +Wire 152.400000 (-1270.000000 -2540.000000) (-1270.000000 2540.000000); +Layer 21; +WIRE 152.400000 ROUND (-5207.000000 2540.000000) +180.000000 (-5207.000000 -2540.000000); +Layer 21; +Wire 152.400000 (-6985.000000 635.000000) (-6985.000000 -635.000000); +Layer 21; +Wire 152.400000 (-6096.000000 1397.000000) (-6096.000000 -1397.000000); +Layer 21; +Wire 152.400000 (-5207.000000 1905.000000) (-5207.000000 -1905.000000); +Layer 21; +Rect R0.0 (2921.000000 1016.000000) (6731.000000 1524.000000); +Layer 21; +Rect R0.0 (2921.000000 -1524.000000) (6731.000000 -1016.000000); +Change Drill 812.800000; +Pad 0.000000 Long R0.0 'A' (7620.000000 -1270.000000); +Change Drill 812.800000; +Pad 0.000000 Long R0.0 'K' (7620.000000 1270.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 14; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'A+' (3302.000000 -2794.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 14; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 'K-' (3302.000000 1778.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (11684.000000 -2794.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (635.000000 -4445.000000); +Change Drill 812.800000; +Hole (0.000000 0.000000); +DESCRIPTION 'LED HOLDER

\nSiemens'; + +Edit 'Q62902-B156.PAC'; +GRID mic; +Layer 21; +Circle 152.400000 (0.000000 0.000000) (2540.000000 0.000000); +Layer 21; +Circle 254.000000 (0.000000 0.000000) (3175.000000 0.000000); +Layer 21; +Wire 152.400000 (2540.000000 -1905.000000) (2540.000000 1905.000000); +Layer 51; +WIRE 152.400000 ROUND (-1143.000000 0.000000) -90.000000 (0.000000 1143.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -1143.000000) +90.000000 (1143.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-1651.000000 0.000000) -90.000000 (0.000000 1651.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -1651.000000) +90.000000 (1651.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-2159.000000 0.000000) -90.000000 (0.000000 2159.000000); +Layer 51; +WIRE 152.400000 ROUND (53.900000 -2212.900000) +90.005308 (2212.900000 -53.900000); +Layer 21; +Wire 152.400000 (2540.000000 3810.000000) (3810.000000 2540.000000); +Layer 21; +Wire 152.400000 (2540.000000 3810.000000) (-3810.000000 3810.000000); +Layer 21; +Wire 152.400000 (-3810.000000 -3810.000000) (-3810.000000 3810.000000); +Layer 21; +Wire 152.400000 (3810.000000 2540.000000) (3810.000000 -3810.000000); +Layer 21; +Wire 152.400000 (-3810.000000 -3810.000000) (-2540.000000 -3810.000000); +Layer 21; +Wire 152.400000 (-2540.000000 -3302.000000) (-2540.000000 -3810.000000); +Layer 21; +Wire 152.400000 (3810.000000 -3810.000000) (2540.000000 -3810.000000); +Layer 21; +Wire 152.400000 (2540.000000 -3302.000000) (2540.000000 -3810.000000); +Layer 21; +Wire 152.400000 (2540.000000 -3302.000000) (-2540.000000 -3302.000000); +Change Drill 1016.000000; +Pad 0.000000 Long R90.0 'A' (-1270.000000 0.000000); +Change Drill 1016.000000; +Pad 0.000000 Long R90.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-3810.000000 4089.400000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-3784.600000 -5359.400000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 14; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '+' (-3556.000000 -3302.000000); +Layer 21; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 14; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '-' (2794.000000 -3302.000000); +DESCRIPTION 'LED HOLDER

\nSiemens'; + +Edit 'SFH480.PAC'; +GRID mic; +Layer 21; +Circle 152.400000 (0.000000 0.000000) (2667.000000 0.000000); +Layer 21; +Circle 254.000000 (0.000000 0.000000) (2413.000000 0.000000); +Layer 21; +Wire 152.400000 (-2159.000000 1524.000000) (-2794.000000 2159.000000); +Layer 21; +Wire 152.400000 (-2794.000000 2159.000000) (-2159.000000 2794.000000); +Layer 21; +Wire 152.400000 (-1524.000000 2159.000000) (-2159.000000 2794.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 1778.000000) -59.743278 (1535.800000 895.900000); +Layer 21; +WIRE 152.400000 ROUND (-1535.800000 895.900000) -59.743278 (0.000000 1778.000000); +Layer 21; +WIRE 152.400000 ROUND (-1535.800000 -895.900000) +59.743278 (0.000000 -1778.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -1778.000000) +59.743278 (1535.800000 -895.900000); +Layer 51; +WIRE 152.400000 ROUND (1514.200000 931.800000) -31.606487 (1778.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (1500.000000 -954.600000) +32.472615 (1778.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-1778.000000 0.000000) +31.606487 (-1514.200000 -931.800000); +Layer 51; +WIRE 152.400000 ROUND (-1778.000000 0.000000) -32.472615 (-1500.000000 954.600000); +Layer 51; +WIRE 152.400000 ROUND (-635.000000 0.000000) -90.000000 (0.000000 635.000000); +Layer 51; +WIRE 152.400000 ROUND (-1016.000000 0.000000) -90.000000 (0.000000 1016.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -635.000000) +90.000000 (635.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (53.900000 -1069.900000) +90.000000 (1069.900000 -53.900000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'A' (1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'K' (-1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1270.000000 3048.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1270.000000 -4318.000000); +DESCRIPTION 'IR LED

\ninfrared emitting diode, Infineon\nTO-18, lead spacing 2.54 mm, cathode marking

\nInifineon'; + +Edit 'SFH482.PAC'; +GRID mic; +Layer 21; +Circle 152.400000 (0.000000 0.000000) (2667.000000 0.000000); +Layer 21; +Circle 254.000000 (0.000000 0.000000) (2413.000000 0.000000); +Layer 21; +Wire 152.400000 (-2159.000000 1524.000000) (-2794.000000 2159.000000); +Layer 21; +Wire 152.400000 (-2794.000000 2159.000000) (-2159.000000 2794.000000); +Layer 21; +Wire 152.400000 (-1524.000000 2159.000000) (-2159.000000 2794.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 1778.000000) -59.743278 (1535.800000 895.900000); +Layer 21; +WIRE 152.400000 ROUND (-1535.800000 895.900000) -59.743278 (0.000000 1778.000000); +Layer 21; +WIRE 152.400000 ROUND (-1535.800000 -895.900000) +59.743278 (0.000000 -1778.000000); +Layer 21; +WIRE 152.400000 ROUND (0.000000 -1778.000000) +59.743278 (1535.800000 -895.900000); +Layer 51; +WIRE 152.400000 ROUND (1514.200000 931.800000) -31.606487 (1778.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (1500.000000 -954.600000) +32.472615 (1778.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (-1778.000000 0.000000) +31.606487 (-1514.200000 -931.800000); +Layer 51; +WIRE 152.400000 ROUND (-1778.000000 0.000000) -32.472615 (-1500.000000 954.600000); +Layer 51; +WIRE 152.400000 ROUND (-635.000000 0.000000) -90.000000 (0.000000 635.000000); +Layer 51; +WIRE 152.400000 ROUND (-1016.000000 0.000000) -90.000000 (0.000000 1016.000000); +Layer 51; +WIRE 152.400000 ROUND (0.000000 -635.000000) +90.000000 (635.000000 0.000000); +Layer 51; +WIRE 152.400000 ROUND (53.900000 -1069.900000) +90.000000 (1069.900000 -53.900000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'A' (-1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1270.000000 3048.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1270.000000 -4318.000000); +DESCRIPTION 'IR LED

\ninfrared emitting diode, Infineon\nTO-18, lead spacing 2.54 mm, cathode marking

\nInifineon'; + +Edit 'SMART-LED.PAC'; +GRID mic; +Layer 51; +Wire 101.600000 (-350.000000 600.000000) (350.000000 600.000000); +Layer 21; +Wire 101.600000 (350.000000 600.000000) (350.000000 -600.000000); +Layer 51; +Wire 101.600000 (350.000000 -600.000000) (150.000000 -600.000000); +Layer 51; +Wire 101.600000 (150.000000 -600.000000) (-350.000000 -600.000000); +Layer 21; +Wire 101.600000 (-350.000000 -600.000000) (-350.000000 600.000000); +Layer 51; +Wire 101.600000 (350.000000 -400.000000) (150.000000 -600.000000); +Layer 21; +Rect R0.0 (-150.000000 -350.000000) (150.000000 -50.000000); +Layer 51; +Rect R0.0 (-150.000000 600.000000) (150.000000 850.000000); +Layer 51; +Rect R0.0 (-150.000000 -850.000000) (150.000000 -600.000000); +Layer 1; +CHANGE Roundness 0; +SMD 350.000000 350.000000 -0 R0.0 'A' (0.000000 725.000000); +Layer 1; +CHANGE Roundness 0; +SMD 350.000000 350.000000 -0 R0.0 'B' (0.000000 -725.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-635.000000 -635.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1016.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (1905.000000 -635.000000); +DESCRIPTION 'SmartLEDTM Hyper-Bright LED

\nSource: http://www.osram.convergy.de/ ... LA_LO_LS_LY L896.pdf'; + +Edit 'SMARTLED-TTW.PAC'; +GRID mic; +Layer 51; +Wire 101.600000 (-350.000000 600.000000) (350.000000 600.000000); +Layer 21; +Wire 101.600000 (350.000000 600.000000) (350.000000 -600.000000); +Layer 51; +Wire 101.600000 (350.000000 -600.000000) (150.000000 -600.000000); +Layer 51; +Wire 101.600000 (150.000000 -600.000000) (-350.000000 -600.000000); +Layer 21; +Wire 101.600000 (-350.000000 -600.000000) (-350.000000 600.000000); +Layer 51; +Wire 101.600000 (350.000000 -400.000000) (150.000000 -600.000000); +Layer 29; +Rect R0.0 (-175.000000 325.000000) (175.000000 700.000000); +Layer 21; +Rect R0.0 (-150.000000 -350.000000) (150.000000 -50.000000); +Layer 51; +Rect R0.0 (-150.000000 600.000000) (150.000000 850.000000); +Layer 51; +Rect R0.0 (-150.000000 -850.000000) (150.000000 -600.000000); +Layer 31; +Rect R0.0 (-225.000000 300.000000) (225.000000 975.000000); +Layer 29; +Rect R180.0 (-175.000000 -700.000000) (175.000000 -325.000000); +Layer 31; +Rect R180.0 (-225.000000 -975.000000) (225.000000 -300.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 500.000000 -0 R0.0 NOSTOP NOCREAM 'A' (0.000000 -875.000000); +Layer 1; +CHANGE Roundness 0; +SMD 350.000000 350.000000 -0 R0.0 NOSTOP NOCREAM 'A@1' (0.000000 -500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 800.000000 500.000000 -0 R0.0 NOSTOP NOCREAM 'C' (0.000000 875.000000); +Layer 1; +CHANGE Roundness 0; +SMD 350.000000 350.000000 -0 R0.0 NOSTOP NOCREAM 'C@1' (0.000000 500.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (-635.000000 -1270.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (1905.000000 -1270.000000); +DESCRIPTION 'SmartLED TTW

\nRecommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603
\nPackage able to withstand TTW-soldering heat
\nPackage suitable for TTW-soldering
\nSource: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf'; + +Edit 'U57X32.PAC'; +GRID mic; +Layer 21; +Wire 152.400000 (-3175.000000 1905.000000) (3175.000000 1905.000000); +Layer 21; +Wire 152.400000 (3175.000000 -1905.000000) (3175.000000 1905.000000); +Layer 21; +Wire 152.400000 (3175.000000 -1905.000000) (-3175.000000 -1905.000000); +Layer 21; +Wire 152.400000 (-3175.000000 1905.000000) (-3175.000000 -1905.000000); +Layer 21; +Wire 152.400000 (-2667.000000 1397.000000) (2667.000000 1397.000000); +Layer 21; +Wire 152.400000 (2667.000000 -1397.000000) (2667.000000 1397.000000); +Layer 21; +Wire 152.400000 (2667.000000 -1397.000000) (-2667.000000 -1397.000000); +Layer 21; +Wire 152.400000 (-2667.000000 1397.000000) (-2667.000000 -1397.000000); +Layer 51; +Wire 152.400000 (-2540.000000 1016.000000) (2540.000000 1016.000000); +Layer 51; +Wire 152.400000 (2286.000000 1270.000000) (2286.000000 -1270.000000); +Layer 51; +Wire 152.400000 (-2540.000000 508.000000) (2540.000000 508.000000); +Layer 51; +Wire 152.400000 (-2540.000000 0.000000) (2540.000000 0.000000); +Layer 51; +Wire 152.400000 (-2540.000000 -508.000000) (2540.000000 -508.000000); +Layer 51; +Wire 152.400000 (-2540.000000 -1016.000000) (2540.000000 -1016.000000); +Layer 51; +Wire 152.400000 (-2286.000000 1270.000000) (-2286.000000 -1270.000000); +Layer 51; +Wire 152.400000 (-1778.000000 1270.000000) (-1778.000000 -1270.000000); +Layer 51; +Wire 152.400000 (-1270.000000 1270.000000) (-1270.000000 -1270.000000); +Layer 51; +Wire 152.400000 (-762.000000 1270.000000) (-762.000000 -1270.000000); +Layer 51; +Wire 152.400000 (-254.000000 1270.000000) (-254.000000 -1270.000000); +Layer 51; +Wire 152.400000 (254.000000 1270.000000) (254.000000 -1270.000000); +Layer 51; +Wire 152.400000 (762.000000 1270.000000) (762.000000 -1270.000000); +Layer 51; +Wire 152.400000 (1270.000000 1270.000000) (1270.000000 -1270.000000); +Layer 51; +Wire 152.400000 (1778.000000 1270.000000) (1778.000000 -1270.000000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'A' (-1270.000000 0.000000); +Change Drill 812.800000; +Pad 0.000000 Long R90.0 'K' (1270.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (3683.000000 254.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (3683.000000 -1524.000000); +DESCRIPTION 'LED

\nrectangle, 5.7 x 3.2 mm'; + +Edit 'MA04-1.PAC'; +GRID mic; +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '1' (-3810.000000 0.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '2' (-1270.000000 0.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '3' (1270.000000 0.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '4' (3810.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-5080.000000 1651.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2540.000000 -2921.000000); +DESCRIPTION ''; + +Edit 'MA04-1-LOCK.PAC'; +GRID mic; +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '1' (-3810.000000 -127.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '2' (-1270.000000 127.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '3' (1270.000000 -127.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '4' (3810.000000 127.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-2540.000000 1651.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2540.000000 -2921.000000); +DESCRIPTION ''; + +Edit 'MA06-1.PAC'; +GRID mic; +Layer 51; +Rect R0.0 (-4064.000000 -254.000000) (-3556.000000 254.000000); +Layer 51; +Rect R0.0 (-6604.000000 -254.000000) (-6096.000000 254.000000); +Layer 51; +Rect R0.0 (-1524.000000 -254.000000) (-1016.000000 254.000000); +Layer 51; +Rect R0.0 (3556.000000 -254.000000) (4064.000000 254.000000); +Layer 51; +Rect R0.0 (1016.000000 -254.000000) (1524.000000 254.000000); +Layer 51; +Rect R0.0 (6096.000000 -254.000000) (6604.000000 254.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '1' (-6350.000000 0.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '2' (-3810.000000 0.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '3' (-1270.000000 0.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '4' (1270.000000 0.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '5' (3810.000000 0.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '6' (6350.000000 0.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-7620.000000 1651.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2540.000000 -2921.000000); +DESCRIPTION 'PIN HEADER'; + +Edit 'MA06-1-LOCK.PAC'; +GRID mic; +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '1' (-6350.000000 127.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '2' (-3810.000000 -127.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '3' (-1270.000000 127.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '4' (1270.000000 -127.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '5' (3810.000000 127.000000); +Change Drill 1016.000000; +Pad 1930.400000 Round R90.0 '6' (6350.000000 -127.000000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-7620.000000 1651.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 10; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2540.000000 -2921.000000); +DESCRIPTION ''; + +Edit 'SOT23-5.PAC'; +GRID mic; +Layer 21; +Wire 152.400000 (1422.400000 810.400000) (1422.400000 -810.400000); +Layer 51; +Wire 152.400000 (1422.400000 -810.400000) (-1422.400000 -810.400000); +Layer 21; +Wire 152.400000 (-1422.400000 -810.400000) (-1422.400000 810.400000); +Layer 51; +Wire 152.400000 (-1422.400000 810.400000) (1422.400000 810.400000); +Layer 21; +Wire 152.400000 (-522.400000 810.400000) (522.400000 810.400000); +Layer 21; +Wire 152.400000 (-427.600000 -810.400000) (-522.400000 -810.400000); +Layer 21; +Wire 152.400000 (522.400000 -810.400000) (427.600000 -810.400000); +Layer 21; +Wire 152.400000 (-1327.600000 -810.400000) (-1422.400000 -810.400000); +Layer 21; +Wire 152.400000 (1422.400000 -810.400000) (1327.600000 -810.400000); +Layer 21; +Wire 152.400000 (1327.600000 810.400000) (1422.400000 810.400000); +Layer 21; +Wire 152.400000 (-1422.400000 810.400000) (-1327.600000 810.400000); +Layer 51; +Rect R0.0 (-1200.000000 -1500.000000) (-700.000000 -850.000000); +Layer 51; +Rect R0.0 (-250.000000 -1500.000000) (250.000000 -850.000000); +Layer 51; +Rect R0.0 (700.000000 -1500.000000) (1200.000000 -850.000000); +Layer 51; +Rect R0.0 (700.000000 850.000000) (1200.000000 1500.000000); +Layer 51; +Rect R0.0 (-1200.000000 850.000000) (-700.000000 1500.000000); +Layer 1; +CHANGE Roundness 0; +SMD 550.000000 1200.000000 -0 R0.0 '1' (-950.000000 -1300.100000); +Layer 1; +CHANGE Roundness 0; +SMD 550.000000 1200.000000 -0 R0.0 '2' (0.000000 -1300.100000); +Layer 1; +CHANGE Roundness 0; +SMD 550.000000 1200.000000 -0 R0.0 '3' (950.000000 -1300.100000); +Layer 1; +CHANGE Roundness 0; +SMD 550.000000 1200.000000 -0 R0.0 '4' (950.000000 1300.100000); +Layer 1; +CHANGE Roundness 0; +SMD 550.000000 1200.000000 -0 R0.0 '5' (-950.000000 1300.100000); +Layer 25; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1905.000000 1905.000000); +Layer 27; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1905.000000 -3175.000000); +DESCRIPTION 'Small Outline Transistor'; + +Edit 'CAP.SYM'; +Layer 94; +Rect R0.0 (-2032.000000 508.000000) (2032.000000 1016.000000); +Layer 94; +Rect R0.0 (-2032.000000 1524.000000) (2032.000000 2032.000000); +Layer 94; +Wire 152.400000 (0.000000 2540.000000) (0.000000 2032.000000); +Layer 94; +Wire 152.400000 (0.000000 0.000000) (0.000000 508.000000); +Pin '1' Pas None Short R270 Off 1 (0.000000 5080.000000); +Pin '2' Pas None Short R90 Off 1 (0.000000 -2540.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (1524.000000 2921.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (1524.000000 -2159.000000); +DESCRIPTION ''; + +Edit 'RESISTOR.SYM'; +Layer 94; +Wire 152.400000 (-2540.000000 0.000000) (-2159.000000 1016.000000); +Layer 94; +Wire 152.400000 (-2159.000000 1016.000000) (-1524.000000 -1016.000000); +Layer 94; +Wire 152.400000 (-1524.000000 -1016.000000) (-889.000000 1016.000000); +Layer 94; +Wire 152.400000 (-889.000000 1016.000000) (-254.000000 -1016.000000); +Layer 94; +Wire 152.400000 (-254.000000 -1016.000000) (381.000000 1016.000000); +Layer 94; +Wire 152.400000 (381.000000 1016.000000) (1016.000000 -1016.000000); +Layer 94; +Wire 152.400000 (1016.000000 -1016.000000) (1651.000000 1016.000000); +Layer 94; +Wire 152.400000 (1651.000000 1016.000000) (2286.000000 -1016.000000); +Layer 94; +Wire 152.400000 (2286.000000 -1016.000000) (2540.000000 0.000000); +Pin '1' Pas None Short R0 Off 1 (-5080.000000 0.000000); +Pin '2' Pas None Short R180 Off 1 (5080.000000 0.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-3810.000000 1498.600000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-3810.000000 -3302.000000); +DESCRIPTION ''; + +Edit 'USB.SYM'; +Layer 94; +Wire 254.000000 (5080.000000 8890.000000) (0.000000 8890.000000); +Layer 94; +Wire 254.000000 (0.000000 8890.000000) (0.000000 -1270.000000); +Layer 94; +Wire 254.000000 (0.000000 -1270.000000) (5080.000000 -1270.000000); +Pin 'D+' IO None Short R0 Pad 0 (-2540.000000 7620.000000); +Pin 'D-' IO None Short R0 Pad 0 (-2540.000000 5080.000000); +Pin 'GND' IO None Short R0 Pad 0 (-2540.000000 0.000000); +Pin 'VBUS' IO None Short R0 Pad 0 (-2540.000000 2540.000000); +Layer 94; +CHANGE FONT PROPORTIONAL; +Change Size 2540.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 'USB' (3810.000000 0.000000); +DESCRIPTION ''; + +Edit '244.SYM'; +Layer 94; +Wire 406.400000 (-7620.000000 -17780.000000) (7620.000000 -17780.000000); +Layer 94; +Wire 406.400000 (7620.000000 -17780.000000) (7620.000000 15240.000000); +Layer 94; +Wire 406.400000 (7620.000000 15240.000000) (-7620.000000 15240.000000); +Layer 94; +Wire 406.400000 (-7620.000000 15240.000000) (-7620.000000 -17780.000000); +Pin '!OEA' In None Middle R0 Both 0 (-12700.000000 -12700.000000); +Pin '!OEB' In None Middle R0 Both 0 (-12700.000000 -15240.000000); +Pin 'DA0' In None Middle R0 Both 0 (-12700.000000 12700.000000); +Pin 'DA1' In None Middle R0 Both 0 (-12700.000000 10160.000000); +Pin 'DA2' In None Middle R0 Both 0 (-12700.000000 7620.000000); +Pin 'DA3' In None Middle R0 Both 0 (-12700.000000 5080.000000); +Pin 'DB0' In None Middle R0 Both 0 (-12700.000000 0.000000); +Pin 'DB1' In None Middle R0 Both 0 (-12700.000000 -2540.000000); +Pin 'DB2' In None Middle R0 Both 0 (-12700.000000 -5080.000000); +Pin 'DB3' In None Middle R0 Both 0 (-12700.000000 -7620.000000); +Pin 'OA0' Out None Middle R180 Both 0 (12700.000000 12700.000000); +Pin 'OA1' Out None Middle R180 Both 0 (12700.000000 10160.000000); +Pin 'OA2' Out None Middle R180 Both 0 (12700.000000 7620.000000); +Pin 'OA3' Out None Middle R180 Both 0 (12700.000000 5080.000000); +Pin 'OB0' Out None Middle R180 Both 0 (12700.000000 0.000000); +Pin 'OB1' Out None Middle R180 Both 0 (12700.000000 -2540.000000); +Pin 'OB2' Out None Middle R180 Both 0 (12700.000000 -5080.000000); +Pin 'OB3' Out None Middle R180 Both 0 (12700.000000 -7620.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-7620.000000 15875.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-7620.000000 -20320.000000); +DESCRIPTION ''; + +Edit 'M10X2.SYM'; +Layer 94; +Wire 609.600000 (-1270.000000 5080.000000) (-2540.000000 5080.000000); +Layer 94; +Wire 609.600000 (-1270.000000 7620.000000) (-2540.000000 7620.000000); +Layer 94; +Wire 609.600000 (-1270.000000 10160.000000) (-2540.000000 10160.000000); +Layer 94; +Wire 406.400000 (-3810.000000 12700.000000) (-3810.000000 -15240.000000); +Layer 94; +Wire 609.600000 (-1270.000000 0.000000) (-2540.000000 0.000000); +Layer 94; +Wire 609.600000 (-1270.000000 2540.000000) (-2540.000000 2540.000000); +Layer 94; +Wire 609.600000 (-1270.000000 -2540.000000) (-2540.000000 -2540.000000); +Layer 94; +Wire 609.600000 (-1270.000000 -5080.000000) (-2540.000000 -5080.000000); +Layer 94; +Wire 609.600000 (-1270.000000 -7620.000000) (-2540.000000 -7620.000000); +Layer 94; +Wire 609.600000 (-1270.000000 -10160.000000) (-2540.000000 -10160.000000); +Layer 94; +Wire 609.600000 (-1270.000000 -12700.000000) (-2540.000000 -12700.000000); +Layer 94; +Wire 406.400000 (3810.000000 -15240.000000) (-3810.000000 -15240.000000); +Layer 94; +Wire 609.600000 (1270.000000 -7620.000000) (2540.000000 -7620.000000); +Layer 94; +Wire 609.600000 (1270.000000 -10160.000000) (2540.000000 -10160.000000); +Layer 94; +Wire 609.600000 (1270.000000 -12700.000000) (2540.000000 -12700.000000); +Layer 94; +Wire 406.400000 (3810.000000 -15240.000000) (3810.000000 12700.000000); +Layer 94; +Wire 406.400000 (-3810.000000 12700.000000) (3810.000000 12700.000000); +Layer 94; +Wire 609.600000 (1270.000000 -2540.000000) (2540.000000 -2540.000000); +Layer 94; +Wire 609.600000 (1270.000000 -5080.000000) (2540.000000 -5080.000000); +Layer 94; +Wire 609.600000 (1270.000000 0.000000) (2540.000000 0.000000); +Layer 94; +Wire 609.600000 (1270.000000 2540.000000) (2540.000000 2540.000000); +Layer 94; +Wire 609.600000 (1270.000000 5080.000000) (2540.000000 5080.000000); +Layer 94; +Wire 609.600000 (1270.000000 7620.000000) (2540.000000 7620.000000); +Layer 94; +Wire 609.600000 (1270.000000 10160.000000) (2540.000000 10160.000000); +Pin '1' Pas None Middle R0 Pad 1 (-7620.000000 10160.000000); +Pin '2' Pas None Middle R180 Pad 1 (7620.000000 10160.000000); +Pin '3' Pas None Middle R0 Pad 1 (-7620.000000 7620.000000); +Pin '4' Pas None Middle R180 Pad 1 (7620.000000 7620.000000); +Pin '5' Pas None Middle R0 Pad 1 (-7620.000000 5080.000000); +Pin '6' Pas None Middle R180 Pad 1 (7620.000000 5080.000000); +Pin '7' Pas None Middle R0 Pad 1 (-7620.000000 2540.000000); +Pin '8' Pas None Middle R180 Pad 1 (7620.000000 2540.000000); +Pin '9' Pas None Middle R0 Pad 1 (-7620.000000 0.000000); +Pin '10' Pas None Middle R180 Pad 1 (7620.000000 0.000000); +Pin '11' Pas None Middle R0 Pad 1 (-7620.000000 -2540.000000); +Pin '12' Pas None Middle R180 Pad 1 (7620.000000 -2540.000000); +Pin '13' Pas None Middle R0 Pad 1 (-7620.000000 -5080.000000); +Pin '14' Pas None Middle R180 Pad 1 (7620.000000 -5080.000000); +Pin '15' Pas None Middle R0 Pad 1 (-7620.000000 -7620.000000); +Pin '16' Pas None Middle R180 Pad 1 (7620.000000 -7620.000000); +Pin '17' Pas None Middle R0 Pad 1 (-7620.000000 -10160.000000); +Pin '18' Pas None Middle R180 Pad 1 (7620.000000 -10160.000000); +Pin '19' Pas None Middle R0 Pad 1 (-7620.000000 -12700.000000); +Pin '20' Pas None Middle R180 Pad 1 (7620.000000 -12700.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2540.000000 -17780.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-2540.000000 13970.000000); +DESCRIPTION ''; + +Edit 'VCCGND.SYM'; +Pin 'GND' Pwr None Middle R90 Pad 0 (0.000000 -7620.000000); +Pin 'VCC' Pwr None Middle R270 Pad 0 (0.000000 7620.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-635.000000 -635.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 'GND' (1905.000000 -5842.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1270.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 'VCC' (1905.000000 2413.000000); +DESCRIPTION ''; + +Edit 'LCMXO2-640HC-4TG100C.SYM'; +Layer 94; +Wire 254.000000 (-53340.000000 -50800.000000) (48260.000000 -50800.000000); +Layer 94; +Wire 254.000000 (48260.000000 -50800.000000) (48260.000000 50800.000000); +Layer 94; +Wire 254.000000 (48260.000000 50800.000000) (-53340.000000 50800.000000); +Layer 94; +Wire 254.000000 (-53340.000000 50800.000000) (-53340.000000 -50800.000000); +Pin 'CSSPIN/PB4A' IO None Short R90 Both 0 (-30480.000000 -53340.000000); +Pin 'DONE/PT11D' IO None Short R270 Both 0 (27940.000000 53340.000000); +Pin 'GND@1' Pwr None Short R0 Both 0 (-55880.000000 17780.000000); +Pin 'GND@2' Pwr None Short R0 Both 0 (-55880.000000 -22860.000000); +Pin 'GND@3' Pwr None Short R90 Both 0 (-15240.000000 -53340.000000); +Pin 'GND@4' Pwr None Short R90 Both 0 (12700.000000 -53340.000000); +Pin 'GND@5' Pwr None Short R180 Both 0 (50800.000000 -17780.000000); +Pin 'GND@6' Pwr None Short R180 Both 0 (50800.000000 22860.000000); +Pin 'GND@7' Pwr None Short R270 Both 0 (20320.000000 53340.000000); +Pin 'GND@8' Pwr None Short R270 Both 0 (-12700.000000 53340.000000); +Pin 'INITN/PT11C' IO None Short R270 Both 0 (25400.000000 53340.000000); +Pin 'JTAGENB/PT10C' IO None Short R270 Both 0 (12700.000000 53340.000000); +Pin 'MCLK/CCLK/PB6A' IO None Short R90 Both 0 (-20320.000000 -53340.000000); +Pin 'NC' NC None Short R270 Both 0 (-5080.000000 53340.000000); +Pin 'NC@1' NC None Short R0 Both 0 (-55880.000000 5080.000000); +Pin 'NC@2' NC None Short R180 Both 0 (50800.000000 -5080.000000); +Pin 'PB4B' IO None Short R90 Both 0 (-27940.000000 -53340.000000); +Pin 'PB4C' IO None Short R90 Both 0 (-25400.000000 -53340.000000); +Pin 'PB4D' IO None Short R90 Both 0 (-22860.000000 -53340.000000); +Pin 'PB6C/PCLKT2_0' IO None Short R90 Both 0 (-12700.000000 -53340.000000); +Pin 'PB6D/PCLKC2_0' IO None Short R90 Both 0 (-10160.000000 -53340.000000); +Pin 'PB10A' IO None Short R90 Both 0 (-7620.000000 -53340.000000); +Pin 'PB10B' IO None Short R90 Both 0 (-5080.000000 -53340.000000); +Pin 'PB10C/PCLKT2_1' IO None Short R90 Both 0 (-2540.000000 -53340.000000); +Pin 'PB10D/PCLKC2_0' IO None Short R90 Both 0 (0.000000 -53340.000000); +Pin 'PB12A' IO None Short R90 Both 0 (2540.000000 -53340.000000); +Pin 'PB12B' IO None Short R90 Both 0 (5080.000000 -53340.000000); +Pin 'PB12C' IO None Short R90 Both 0 (7620.000000 -53340.000000); +Pin 'PB12D' IO None Short R90 Both 0 (10160.000000 -53340.000000); +Pin 'PB14A' IO None Short R90 Both 0 (15240.000000 -53340.000000); +Pin 'PB14B' IO None Short R90 Both 0 (20320.000000 -53340.000000); +Pin 'PL2A' IO None Short R0 Both 0 (-55880.000000 30480.000000); +Pin 'PL2B' IO None Short R0 Both 0 (-55880.000000 27940.000000); +Pin 'PL2C/PCLKT3_2' IO None Short R0 Both 0 (-55880.000000 25400.000000); +Pin 'PL2D/PCLKC3_2' IO None Short R0 Both 0 (-55880.000000 22860.000000); +Pin 'PL3A' IO None Short R0 Both 0 (-55880.000000 15240.000000); +Pin 'PL3B' IO None Short R0 Both 0 (-55880.000000 12700.000000); +Pin 'PL3C' IO None Short R0 Both 0 (-55880.000000 10160.000000); +Pin 'PL3D' IO None Short R0 Both 0 (-55880.000000 7620.000000); +Pin 'PL5A/PCLKT3_1' IO None Short R0 Both 0 (-55880.000000 2540.000000); +Pin 'PL5B/PCLKC3_1' IO None Short R0 Both 0 (-55880.000000 0.000000); +Pin 'PL5C' IO None Short R0 Both 0 (-55880.000000 -2540.000000); +Pin 'PL5D' IO None Short R0 Both 0 (-55880.000000 -5080.000000); +Pin 'PL6A' IO None Short R0 Both 0 (-55880.000000 -7620.000000); +Pin 'PL6B' IO None Short R0 Both 0 (-55880.000000 -10160.000000); +Pin 'PL6C' IO None Short R0 Both 0 (-55880.000000 -12700.000000); +Pin 'PL6D' IO None Short R0 Both 0 (-55880.000000 -15240.000000); +Pin 'PL7A/PCLKT3_0' IO None Short R0 Both 0 (-55880.000000 -17780.000000); +Pin 'PL7B/PCLKC3_0' IO None Short R0 Both 0 (-55880.000000 -20320.000000); +Pin 'PL7C' IO None Short R0 Both 0 (-55880.000000 -27940.000000); +Pin 'PL7D' IO None Short R0 Both 0 (-55880.000000 -30480.000000); +Pin 'PR2A' IO None Short R180 Both 0 (50800.000000 30480.000000); +Pin 'PR2B' IO None Short R180 Both 0 (50800.000000 27940.000000); +Pin 'PR2C' IO None Short R180 Both 0 (50800.000000 20320.000000); +Pin 'PR2D' IO None Short R180 Both 0 (50800.000000 17780.000000); +Pin 'PR3A' IO None Short R180 Both 0 (50800.000000 15240.000000); +Pin 'PR3B' IO None Short R180 Both 0 (50800.000000 12700.000000); +Pin 'PR3C' IO None Short R180 Both 0 (50800.000000 10160.000000); +Pin 'PR3D' IO None Short R180 Both 0 (50800.000000 7620.000000); +Pin 'PR5A' IO None Short R180 Both 0 (50800.000000 5080.000000); +Pin 'PR5B' IO None Short R180 Both 0 (50800.000000 2540.000000); +Pin 'PR5C/PCLKT1_0' IO None Short R180 Both 0 (50800.000000 0.000000); +Pin 'PR5D/PCLKC1_0' IO None Short R180 Both 0 (50800.000000 -2540.000000); +Pin 'PR6A' Pwr None Short R180 Both 0 (50800.000000 -7620.000000); +Pin 'PR6B' Pwr None Short R180 Both 0 (50800.000000 -10160.000000); +Pin 'PR6C' IO None Short R180 Both 0 (50800.000000 -12700.000000); +Pin 'PR6D' IO None Short R180 Both 0 (50800.000000 -15240.000000); +Pin 'PR7A' IO None Short R180 Both 0 (50800.000000 -22860.000000); +Pin 'PR7B' IO None Short R180 Both 0 (50800.000000 -25400.000000); +Pin 'PR7C' IO None Short R180 Both 0 (50800.000000 -27940.000000); +Pin 'PR7D' IO None Short R180 Both 0 (50800.000000 -30480.000000); +Pin 'PROGRAMN/PT10D' IO None Short R270 Both 0 (15240.000000 53340.000000); +Pin 'PT6A' IO None Short R270 Both 0 (-30480.000000 53340.000000); +Pin 'PT6B' IO None Short R270 Both 0 (-27940.000000 53340.000000); +Pin 'PT6C' IO None Short R270 Both 0 (-25400.000000 53340.000000); +Pin 'PT6D' IO None Short R270 Both 0 (-22860.000000 53340.000000); +Pin 'PT9A/PCLKT0_1' IO None Short R270 Both 0 (-2540.000000 53340.000000); +Pin 'PT9B/PCLKC0_1' IO None Short R270 Both 0 (0.000000 53340.000000); +Pin 'PT10A' IO None Short R270 Both 0 (7620.000000 53340.000000); +Pin 'PT10B' IO None Short R270 Both 0 (10160.000000 53340.000000); +Pin 'PT11A' IO None Short R270 Both 0 (22860.000000 53340.000000); +Pin 'SCL/PCLKT0_0' IO None Short R270 Both 0 (2540.000000 53340.000000); +Pin 'SDA/PCLKC0_0/PT9D' IO None Short R270 Both 0 (5080.000000 53340.000000); +Pin 'SI/SISPI/PB14D' IO None Short R90 Both 0 (25400.000000 -53340.000000); +Pin 'SN/PB14C' IO None Short R90 Both 0 (22860.000000 -53340.000000); +Pin 'SO/SPISO/PB6B' IO None Short R90 Both 0 (-17780.000000 -53340.000000); +Pin 'TCK/PT7C' IO None Short R270 Both 0 (-10160.000000 53340.000000); +Pin 'TDI/PT7B' IO None Short R270 Both 0 (-17780.000000 53340.000000); +Pin 'TDO/PT7A' IO None Short R270 Both 0 (-20320.000000 53340.000000); +Pin 'TMS/PT7D' IO None Short R270 Both 0 (-7620.000000 53340.000000); +Pin 'VCC@1' Pwr None Short R90 Both 0 (27940.000000 -53340.000000); +Pin 'VCC@2' Pwr None Short R270 Both 0 (-33020.000000 53340.000000); +Pin 'VCCIO0@1' Pwr None Short R270 Both 0 (17780.000000 53340.000000); +Pin 'VCCIO0@2' Pwr None Short R270 Both 0 (-15240.000000 53340.000000); +Pin 'VCCIO1@1' Pwr None Short R180 Both 0 (50800.000000 -20320.000000); +Pin 'VCCIO1@2' Pwr None Short R180 Both 0 (50800.000000 25400.000000); +Pin 'VCCIO2@1' Pwr None Short R90 Both 0 (-33020.000000 -53340.000000); +Pin 'VCCIO2@2' Pwr None Short R90 Both 0 (17780.000000 -53340.000000); +Pin 'VCCIO3@1' Pwr None Short R0 Both 0 (-55880.000000 20320.000000); +Pin 'VCCIO3@2' Pwr None Short R0 Both 0 (-55880.000000 -25400.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-5080.000000 1270.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-5080.000000 -2540.000000); +DESCRIPTION ''; + +Edit 'ATPIN.SYM'; +Layer 94; +Wire 304.800000 (0.000000 635.000000) (3175.000000 635.000000); +Layer 94; +Wire 304.800000 (3175.000000 635.000000) (3175.000000 -635.000000); +Layer 94; +Wire 304.800000 (3175.000000 -635.000000) (0.000000 -635.000000); +Layer 94; +Wire 304.800000 (0.000000 -635.000000) (0.000000 635.000000); +Pin 'P' IO None Short R0 Pad 1 (-2540.000000 0.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (4445.000000 -965.200000); +DESCRIPTION ''; + +Edit 'LED.SYM'; +Layer 94; +Wire 254.000000 (1270.000000 0.000000) (0.000000 -2540.000000); +Layer 94; +Wire 254.000000 (0.000000 -2540.000000) (-1270.000000 0.000000); +Layer 94; +Wire 254.000000 (1270.000000 -2540.000000) (0.000000 -2540.000000); +Layer 94; +Wire 254.000000 (0.000000 -2540.000000) (-1270.000000 -2540.000000); +Layer 94; +Wire 254.000000 (1270.000000 0.000000) (0.000000 0.000000); +Layer 94; +Wire 254.000000 (0.000000 0.000000) (-1270.000000 0.000000); +Layer 94; +Wire 152.400000 (0.000000 0.000000) (0.000000 -2540.000000); +Layer 94; +Wire 152.400000 (-2032.000000 -762.000000) (-3429.000000 -2159.000000); +Layer 94; +Wire 152.400000 (-1905.000000 -1905.000000) (-3302.000000 -3302.000000); +Pin 'A' Pas None Short R270 Off 0 (0.000000 2540.000000); +Pin 'C' Pas None Short R90 Off 0 (0.000000 -5080.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>NAME' (3556.000000 -4572.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (5715.000000 -4572.000000); +Layer 94; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 152.400000 (-3429.000000 -2159.000000) +0.000000 (-3048.000000 -1270.000000) +0.000000 (-2540.000000 -1778.000000) +0.000000 (-3429.000000 -2159.000000) ; +Layer 94; +Change Spacing 1270.000000; +Change Pour Solid; +Polygon 152.400000 (-3302.000000 -3302.000000) +0.000000 (-2921.000000 -2413.000000) +0.000000 (-2413.000000 -2921.000000) +0.000000 (-3302.000000 -3302.000000) ; +DESCRIPTION ''; + +Edit 'MA04-1.SYM'; +Layer 94; +Wire 406.400000 (-1270.000000 -7620.000000) (-6350.000000 -7620.000000); +Layer 94; +Wire 609.600000 (-3810.000000 0.000000) (-2540.000000 0.000000); +Layer 94; +Wire 609.600000 (-3810.000000 -2540.000000) (-2540.000000 -2540.000000); +Layer 94; +Wire 609.600000 (-3810.000000 -5080.000000) (-2540.000000 -5080.000000); +Layer 94; +Wire 609.600000 (-3810.000000 2540.000000) (-2540.000000 2540.000000); +Layer 94; +Wire 406.400000 (-6350.000000 5080.000000) (-6350.000000 -7620.000000); +Layer 94; +Wire 406.400000 (-1270.000000 -7620.000000) (-1270.000000 5080.000000); +Layer 94; +Wire 406.400000 (-6350.000000 5080.000000) (-1270.000000 5080.000000); +Pin '1' Pas None Middle R180 Pad 1 (2540.000000 -5080.000000); +Pin '2' Pas None Middle R180 Pad 1 (2540.000000 -2540.000000); +Pin '3' Pas None Middle R180 Pad 1 (2540.000000 0.000000); +Pin '4' Pas None Middle R180 Pad 1 (2540.000000 2540.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-6350.000000 -10160.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-6350.000000 5842.000000); +DESCRIPTION ''; + +Edit 'MA06-1.SYM'; +Layer 94; +Wire 406.400000 (3810.000000 -10160.000000) (-1270.000000 -10160.000000); +Layer 94; +Wire 609.600000 (1270.000000 -2540.000000) (2540.000000 -2540.000000); +Layer 94; +Wire 609.600000 (1270.000000 -5080.000000) (2540.000000 -5080.000000); +Layer 94; +Wire 609.600000 (1270.000000 -7620.000000) (2540.000000 -7620.000000); +Layer 94; +Wire 609.600000 (1270.000000 2540.000000) (2540.000000 2540.000000); +Layer 94; +Wire 609.600000 (1270.000000 0.000000) (2540.000000 0.000000); +Layer 94; +Wire 609.600000 (1270.000000 5080.000000) (2540.000000 5080.000000); +Layer 94; +Wire 406.400000 (-1270.000000 7620.000000) (-1270.000000 -10160.000000); +Layer 94; +Wire 406.400000 (3810.000000 -10160.000000) (3810.000000 7620.000000); +Layer 94; +Wire 406.400000 (-1270.000000 7620.000000) (3810.000000 7620.000000); +Pin '1' Pas None Middle R180 Pad 1 (7620.000000 -7620.000000); +Pin '2' Pas None Middle R180 Pad 1 (7620.000000 -5080.000000); +Pin '3' Pas None Middle R180 Pad 1 (7620.000000 -2540.000000); +Pin '4' Pas None Middle R180 Pad 1 (7620.000000 0.000000); +Pin '5' Pas None Middle R180 Pad 1 (7620.000000 2540.000000); +Pin '6' Pas None Middle R180 Pad 1 (7620.000000 5080.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-1270.000000 -12700.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-1270.000000 8382.000000); +DESCRIPTION ''; + +Edit '+3V3.SYM'; +Layer 94; +Wire 254.000000 (1270.000000 -1905.000000) (0.000000 0.000000); +Layer 94; +Wire 254.000000 (0.000000 0.000000) (-1270.000000 -1905.000000); +Pin '+3V3' Sup None Short R90 Off 0 (0.000000 -2540.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (-2540.000000 -5080.000000); +DESCRIPTION ''; + +Edit '+5V.SYM'; +Layer 94; +Wire 254.000000 (1270.000000 -1905.000000) (0.000000 0.000000); +Layer 94; +Wire 254.000000 (0.000000 0.000000) (-1270.000000 -1905.000000); +Pin '+5V' Sup None Short R90 Off 0 (0.000000 -2540.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R90.0 '>VALUE' (-2540.000000 -5080.000000); +DESCRIPTION ''; + +Edit 'GND.SYM'; +Layer 94; +Wire 254.000000 (-1905.000000 0.000000) (1905.000000 0.000000); +Pin 'GND' Sup None Short R270 Off 0 (0.000000 2540.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (-2540.000000 -2540.000000); +DESCRIPTION ''; + +Edit 'MIC5219B.SYM'; +Layer 94; +Wire 254.000000 (-7620.000000 7620.000000) (7620.000000 7620.000000); +Layer 94; +Wire 254.000000 (7620.000000 7620.000000) (7620.000000 -7620.000000); +Layer 94; +Wire 254.000000 (7620.000000 -7620.000000) (-7620.000000 -7620.000000); +Layer 94; +Wire 254.000000 (-7620.000000 -7620.000000) (-7620.000000 7620.000000); +Pin 'BYP' Pas None Short R0 Both 0 (-10160.000000 -5080.000000); +Pin 'EN' In None Short R0 Both 0 (-10160.000000 0.000000); +Pin 'GND' Pwr None Short R90 Both 0 (2540.000000 -10160.000000); +Pin 'IN' In None Short R0 Both 0 (-10160.000000 5080.000000); +Pin 'OUT' Out None Short R180 Both 0 (10160.000000 5080.000000); +Layer 95; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>NAME' (-7620.000000 8890.000000); +Layer 96; +CHANGE FONT PROPORTIONAL; +Change Size 1778.000000; +Change Ratio 8; +Change Align BOTTOM LEFT; +Change Linedistance 50; +Text R0.0 '>VALUE' (10160.000000 -7620.000000); +DESCRIPTION ''; + +Edit 'CAP.DEV'; +DESCRIPTION 'Capacitor\nStandard 0603 ceramic capacitor, and 0.1" leaded capacitor.'; +PREFIX 'C'; +VALUE On; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'CAP' 'G$1' (0.000000 0.000000); +PACKAGE '0402-CAP' 0402-CAP; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE '0603-CAP' 0603-CAP; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE '0805' 0805; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE '1206' 1206; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE '1210' 1210; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'CTZ3' ASMD; +CONNECT ALL 'G$1.1' '+'; +CONNECT ALL 'G$1.2' '-'; +TECHNOLOGY ''''''; +PACKAGE 'CAP-PTH-SMALL-KIT' KIT; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'CAP-PTH-SMALL' PTH; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'CAP-PTH-5MM' PTH1; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'CAP-PTH-SMALL2' PTH2; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'CAP-PTH-LARGE' PTH3; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'GRM43D' SMD; +CONNECT ALL 'G$1.1' 'A'; +CONNECT ALL 'G$1.2' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'AXIAL-5MM' _; +CONNECT ALL 'G$1.1' 'P$1'; +CONNECT ALL 'G$1.2' 'P$2'; +TECHNOLOGY ''''''; + +Edit 'RESISTOR.DEV'; +DESCRIPTION 'Resistor\nBasic schematic elements and footprints for 0603, 1206, and PTH resistors.'; +PREFIX 'R'; +VALUE On; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'RESISTOR' 'G$1' (0.000000 0.000000); +PACKAGE '0402-RES' 0402-RES; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE '0603-RES' 0603-RES; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE '0805' 0805-RES; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE '1206' 1206; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'R2010' 2010; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'R2512' 2512; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'AXIAL-0.3' AXIAL-0.3; +CONNECT ALL 'G$1.1' 'P$1'; +CONNECT ALL 'G$1.2' 'P$2'; +TECHNOLOGY ''''''; +PACKAGE 'AXIAL-0.3-KIT' KIT; +CONNECT ALL 'G$1.1' 'P$1'; +CONNECT ALL 'G$1.2' 'P$2'; +TECHNOLOGY ''''''; +PACKAGE 'AXIAL-0.5' PTH-1/2W; +CONNECT ALL 'G$1.1' 'P$1'; +CONNECT ALL 'G$1.2' 'P$2'; +TECHNOLOGY ''''''; +PACKAGE 'AXIAL-0.4' PTH-1/4W; +CONNECT ALL 'G$1.1' 'P$1'; +CONNECT ALL 'G$1.2' 'P$2'; +TECHNOLOGY ''''''; +PACKAGE '1/6W-RES$1' PTH-1/6W; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +TECHNOLOGY ''''''; +PACKAGE 'AXIAL-0.6' PTH-1W; +CONNECT ALL 'G$1.1' 'P$1'; +CONNECT ALL 'G$1.2' 'P$2'; +TECHNOLOGY ''''''; +PACKAGE 'AXIAL-0.8' PTH-2W; +CONNECT ALL 'G$1.1' 'P$1'; +CONNECT ALL 'G$1.2' 'P$2'; +TECHNOLOGY ''''''; + +Edit 'USB.DEV'; +DESCRIPTION 'USB Connectors\n

USB-B-PTH is fully proven SKU : PRT-00139/CONN-08278\n

USB-miniB is fully proven SKU : PRT-00587\n

USB-A-PCB is untested.\n

USB-A-H is throughly reviewed, but untested. Spark Fun Electronics SKU : PRT-00437\n

USB-B-SMT is throughly reviewed, but untested. Needs silkscreen touching up.\n

USB-A-S has not been used/tested\n

USB-MB-H has not been used/tested\n

USB-MICROB has been used. CONN-09505'; +PREFIX 'JP'; +VALUE Off; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'USB' 'G$1' (0.000000 0.000000); +PACKAGE 'USB-A-H' -A-H; +CONNECT ALL 'G$1.D+' 'D-'; +CONNECT ALL 'G$1.D-' 'D+'; +CONNECT ALL 'G$1.GND' 'VBUS'; +CONNECT ALL 'G$1.VBUS' 'GND'; +TECHNOLOGY ''''''; +PACKAGE 'USB-A-S' -A-S; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +PACKAGE 'USB-A-S-NOSILK-FEMALE' -A-SMD; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +ATTRIBUTE 'PROD_ID' 'CONN-09520' CONSTANT +PACKAGE 'USB-B-SMT' -B-S; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VUSB'; +TECHNOLOGY ''''''; +PACKAGE 'S4B-PH' -JST-2MM-SMT; +CONNECT ALL 'G$1.D+' '2'; +CONNECT ALL 'G$1.D-' '3'; +CONNECT ALL 'G$1.GND' '1'; +CONNECT ALL 'G$1.VBUS' '4'; +TECHNOLOGY ''''''; +PACKAGE 'USB-MB-H' -MB-H; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +PACKAGE 'USB-MICROB' -MICROB; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND MT1 MT2'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +ATTRIBUTE 'PROD_ID' 'CONN-09505' CONSTANT +PACKAGE 'USB-MINIB-NOSTOP' -SMD-NS; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +PACKAGE 'USB-A-SMT-MALE' A-SMD-MALE; +CONNECT ALL 'G$1.D+' 'D+1'; +CONNECT ALL 'G$1.D-' 'D-1'; +CONNECT ALL 'G$1.GND' 'GND1'; +CONNECT ALL 'G$1.VBUS' 'VBUS1'; +TECHNOLOGY ''''''; +PACKAGE 'USB-MINIB-OLD' OLD; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +PACKAGE 'USB-A-PCB' PCB; +CONNECT ALL 'G$1.D+' 'USB_P'; +CONNECT ALL 'G$1.D-' 'USB_M'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' '5V'; +TECHNOLOGY ''''''; +PACKAGE 'USB-B-PTH' PTH; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +ATTRIBUTE 'PROD_ID' 'CONN-08278' +ATTRIBUTE 'VALUE' 'USB-B' +PACKAGE 'USB-B-PTH-VERTICAL' PTH-VERTICAL; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +PACKAGE 'USB-MINIB' SMD; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +PACKAGE 'USB-A-S-NOSILK' USB-A-S-NOSILK; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; +PACKAGE 'USB-A-S-SILK-FEMALE' _; +CONNECT ALL 'G$1.D+' 'D+'; +CONNECT ALL 'G$1.D-' 'D-'; +CONNECT ALL 'G$1.GND' 'GND'; +CONNECT ALL 'G$1.VBUS' 'VBUS'; +TECHNOLOGY ''''''; + +Edit '74X244.DEV'; +DESCRIPTION 'MEMORY'; +PREFIX 'IC'; +VALUE On; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD '244' 'G$1' (0.000000 0.000000); +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'VCCGND' 'P' (-22860.000000 2540.000000); +PACKAGE 'SSOP20' ''; +CONNECT ALL 'G$1.!OEA' '1'; +CONNECT ALL 'G$1.!OEB' '19'; +CONNECT ALL 'G$1.DA0' '2'; +CONNECT ALL 'G$1.DA1' '4'; +CONNECT ALL 'G$1.DA2' '6'; +CONNECT ALL 'G$1.DA3' '8'; +CONNECT ALL 'G$1.DB0' '17'; +CONNECT ALL 'G$1.DB1' '15'; +CONNECT ALL 'G$1.DB2' '13'; +CONNECT ALL 'G$1.DB3' '11'; +CONNECT ALL 'G$1.OA0' '18'; +CONNECT ALL 'G$1.OA1' '16'; +CONNECT ALL 'G$1.OA2' '14'; +CONNECT ALL 'G$1.OA3' '12'; +CONNECT ALL 'G$1.OB0' '3'; +CONNECT ALL 'G$1.OB1' '5'; +CONNECT ALL 'G$1.OB2' '7'; +CONNECT ALL 'G$1.OB3' '9'; +CONNECT ALL 'P.GND' '10'; +CONNECT ALL 'P.VCC' '20'; +TECHNOLOGY ''''''; + +Edit 'IDC20.DEV'; +DESCRIPTION ''; +PREFIX ''; +VALUE Off; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'M10X2' 'G$1' (0.000000 0.000000); +PACKAGE 'IDC20' ''; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +CONNECT ALL 'G$1.3' '3'; +CONNECT ALL 'G$1.4' '4'; +CONNECT ALL 'G$1.5' '5'; +CONNECT ALL 'G$1.6' '6'; +CONNECT ALL 'G$1.7' '7'; +CONNECT ALL 'G$1.8' '8'; +CONNECT ALL 'G$1.9' '9'; +CONNECT ALL 'G$1.10' '10'; +CONNECT ALL 'G$1.11' '11'; +CONNECT ALL 'G$1.12' '12'; +CONNECT ALL 'G$1.13' '13'; +CONNECT ALL 'G$1.14' '14'; +CONNECT ALL 'G$1.15' '15'; +CONNECT ALL 'G$1.16' '16'; +CONNECT ALL 'G$1.17' '17'; +CONNECT ALL 'G$1.18' '18'; +CONNECT ALL 'G$1.19' '19'; +CONNECT ALL 'G$1.20' '20'; +TECHNOLOGY ''''''; + +Edit 'LCMXO2-640HC-4TG100C.DEV'; +DESCRIPTION ''; +PREFIX ''; +VALUE Off; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'LCMXO2-640HC-4TG100C' 'G$1' (0.000000 0.000000); +PACKAGE 'TQFP100' ''; +CONNECT ALL 'G$1.CSSPIN/PB4A' '27'; +CONNECT ALL 'G$1.DONE/PT11D' '76'; +CONNECT ALL 'G$1.GND@1' '6'; +CONNECT ALL 'G$1.GND@2' '22'; +CONNECT ALL 'G$1.GND@3' '33'; +CONNECT ALL 'G$1.GND@4' '44'; +CONNECT ALL 'G$1.GND@5' '56'; +CONNECT ALL 'G$1.GND@6' '72'; +CONNECT ALL 'G$1.GND@7' '79'; +CONNECT ALL 'G$1.GND@8' '92'; +CONNECT ALL 'G$1.INITN/PT11C' '77'; +CONNECT ALL 'G$1.JTAGENB/PT10C' '82'; +CONNECT ALL 'G$1.MCLK/CCLK/PB6A' '31'; +CONNECT ALL 'G$1.NC' '89'; +CONNECT ALL 'G$1.NC@1' '11'; +CONNECT ALL 'G$1.NC@2' '61'; +CONNECT ALL 'G$1.PB4B' '28'; +CONNECT ALL 'G$1.PB4C' '29'; +CONNECT ALL 'G$1.PB4D' '30'; +CONNECT ALL 'G$1.PB6C/PCLKT2_0' '34'; +CONNECT ALL 'G$1.PB6D/PCLKC2_0' '35'; +CONNECT ALL 'G$1.PB10A' '36'; +CONNECT ALL 'G$1.PB10B' '37'; +CONNECT ALL 'G$1.PB10C/PCLKT2_1' '38'; +CONNECT ALL 'G$1.PB10D/PCLKC2_0' '39'; +CONNECT ALL 'G$1.PB12A' '40'; +CONNECT ALL 'G$1.PB12B' '41'; +CONNECT ALL 'G$1.PB12C' '42'; +CONNECT ALL 'G$1.PB12D' '43'; +CONNECT ALL 'G$1.PB14A' '45'; +CONNECT ALL 'G$1.PB14B' '47'; +CONNECT ALL 'G$1.PL2A' '1'; +CONNECT ALL 'G$1.PL2B' '2'; +CONNECT ALL 'G$1.PL2C/PCLKT3_2' '3'; +CONNECT ALL 'G$1.PL2D/PCLKC3_2' '4'; +CONNECT ALL 'G$1.PL3A' '7'; +CONNECT ALL 'G$1.PL3B' '8'; +CONNECT ALL 'G$1.PL3C' '9'; +CONNECT ALL 'G$1.PL3D' '10'; +CONNECT ALL 'G$1.PL5A/PCLKT3_1' '12'; +CONNECT ALL 'G$1.PL5B/PCLKC3_1' '13'; +CONNECT ALL 'G$1.PL5C' '14'; +CONNECT ALL 'G$1.PL5D' '15'; +CONNECT ALL 'G$1.PL6A' '16'; +CONNECT ALL 'G$1.PL6B' '17'; +CONNECT ALL 'G$1.PL6C' '18'; +CONNECT ALL 'G$1.PL6D' '19'; +CONNECT ALL 'G$1.PL7A/PCLKT3_0' '20'; +CONNECT ALL 'G$1.PL7B/PCLKC3_0' '21'; +CONNECT ALL 'G$1.PL7C' '24'; +CONNECT ALL 'G$1.PL7D' '25'; +CONNECT ALL 'G$1.PR2A' '75'; +CONNECT ALL 'G$1.PR2B' '74'; +CONNECT ALL 'G$1.PR2C' '71'; +CONNECT ALL 'G$1.PR2D' '70'; +CONNECT ALL 'G$1.PR3A' '69'; +CONNECT ALL 'G$1.PR3B' '68'; +CONNECT ALL 'G$1.PR3C' '67'; +CONNECT ALL 'G$1.PR3D' '66'; +CONNECT ALL 'G$1.PR5A' '65'; +CONNECT ALL 'G$1.PR5B' '64'; +CONNECT ALL 'G$1.PR5C/PCLKT1_0' '63'; +CONNECT ALL 'G$1.PR5D/PCLKC1_0' '62'; +CONNECT ALL 'G$1.PR6A' '60'; +CONNECT ALL 'G$1.PR6B' '59'; +CONNECT ALL 'G$1.PR6C' '58'; +CONNECT ALL 'G$1.PR6D' '57'; +CONNECT ALL 'G$1.PR7A' '54'; +CONNECT ALL 'G$1.PR7B' '53'; +CONNECT ALL 'G$1.PR7C' '52'; +CONNECT ALL 'G$1.PR7D' '51'; +CONNECT ALL 'G$1.PROGRAMN/PT10D' '81'; +CONNECT ALL 'G$1.PT6A' '99'; +CONNECT ALL 'G$1.PT6B' '98'; +CONNECT ALL 'G$1.PT6C' '97'; +CONNECT ALL 'G$1.PT6D' '96'; +CONNECT ALL 'G$1.PT9A/PCLKT0_1' '88'; +CONNECT ALL 'G$1.PT9B/PCLKC0_1' '87'; +CONNECT ALL 'G$1.PT10A' '84'; +CONNECT ALL 'G$1.PT10B' '83'; +CONNECT ALL 'G$1.PT11A' '78'; +CONNECT ALL 'G$1.SCL/PCLKT0_0' '86'; +CONNECT ALL 'G$1.SDA/PCLKC0_0/PT9D' '85'; +CONNECT ALL 'G$1.SI/SISPI/PB14D' '49'; +CONNECT ALL 'G$1.SN/PB14C' '48'; +CONNECT ALL 'G$1.SO/SPISO/PB6B' '32'; +CONNECT ALL 'G$1.TCK/PT7C' '91'; +CONNECT ALL 'G$1.TDI/PT7B' '94'; +CONNECT ALL 'G$1.TDO/PT7A' '95'; +CONNECT ALL 'G$1.TMS/PT7D' '90'; +CONNECT ALL 'G$1.VCC@1' '50'; +CONNECT ALL 'G$1.VCC@2' '100'; +CONNECT ALL 'G$1.VCCIO0@1' '80'; +CONNECT ALL 'G$1.VCCIO0@2' '93'; +CONNECT ALL 'G$1.VCCIO1@1' '55'; +CONNECT ALL 'G$1.VCCIO1@2' '73'; +CONNECT ALL 'G$1.VCCIO2@1' '26'; +CONNECT ALL 'G$1.VCCIO2@2' '46'; +CONNECT ALL 'G$1.VCCIO3@1' '5'; +CONNECT ALL 'G$1.VCCIO3@2' '23'; +TECHNOLOGY ''''''; + +Edit 'A2-50PIN.DEV'; +DESCRIPTION 'Apple ][ Peripheral Card Connector\n
\nThis is the, default, 50-pin connector for slot #1 to #7\n
\nPins are laid out as seen from the top of the slot'; +PREFIX 'ST'; +VALUE On; +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_+5V' (27940.000000 22860.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_+12V' (-5080.000000 -38100.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_-5V' (-5080.000000 2540.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_-12V' (-5080.000000 5080.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_00' (-5080.000000 -12700.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_01' (-5080.000000 -7620.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_7M' (-5080.000000 -2540.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A00' (27940.000000 -35560.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A01' (27940.000000 -33020.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A02' (27940.000000 -30480.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A03' (27940.000000 -27940.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A04' (27940.000000 -25400.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A05' (27940.000000 -22860.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A06' (27940.000000 -20320.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A07' (27940.000000 -17780.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A08' (27940.000000 -15240.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A09' (27940.000000 -12700.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A10' (27940.000000 -10160.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A11' (27940.000000 -7620.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A12' (27940.000000 -5080.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A13' (27940.000000 -2540.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A14' (27940.000000 0.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_A15' (27940.000000 2540.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_D0' (-5080.000000 -35560.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_D1' (-5080.000000 -33020.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_D2' (-5080.000000 -30480.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_D3' (-5080.000000 -27940.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_D4' (-5080.000000 -25400.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_D5' (-5080.000000 -22860.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_D6' (-5080.000000 -20320.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_D7' (-5080.000000 -17780.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_DEVSELECT\' (-5080.000000 -15240.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_DMA\' (27940.000000 15240.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_DMA_IN' (-5080.000000 20320.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_DMA_OUT' (27940.000000 20320.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_GND' (-5080.000000 22860.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_INH\' (-5080.000000 7620.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_INT_IN' (-5080.000000 17780.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_INT_OUT' (27940.000000 17780.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_IOSELECT\' (27940.000000 -38100.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_IOSTR\' (27940.000000 10160.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_IRQ\' (-5080.000000 12700.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_NC@1' (27940.000000 7620.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_NC@2' (-5080.000000 0.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_NMI\' (-5080.000000 15240.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_Q3' (-5080.000000 -5080.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_RDY' (27940.000000 12700.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_RES\' (-5080.000000 10160.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_RW' (27940.000000 5080.000000); +CHANGE Addlevel Always; +CHANGE Swaplevel 0; +ADD 'ATPIN' '_USER1' (-5080.000000 -10160.000000); +PACKAGE 'A2-50PIN-MINI' MINI; +CONNECT ALL '_+5V.P' '25'; +CONNECT ALL '_+12V.P' '50'; +CONNECT ALL '_-5V.P' '34'; +CONNECT ALL '_-12V.P' '33'; +CONNECT ALL '_00.P' '40'; +CONNECT ALL '_01.P' '38'; +CONNECT ALL '_7M.P' '36'; +CONNECT ALL '_A00.P' '02'; +CONNECT ALL '_A01.P' '03'; +CONNECT ALL '_A02.P' '04'; +CONNECT ALL '_A03.P' '05'; +CONNECT ALL '_A04.P' '06'; +CONNECT ALL '_A05.P' '07'; +CONNECT ALL '_A06.P' '08'; +CONNECT ALL '_A07.P' '09'; +CONNECT ALL '_A08.P' '10'; +CONNECT ALL '_A09.P' '11'; +CONNECT ALL '_A10.P' '12'; +CONNECT ALL '_A11.P' '13'; +CONNECT ALL '_A12.P' '14'; +CONNECT ALL '_A13.P' '15'; +CONNECT ALL '_A14.P' '16'; +CONNECT ALL '_A15.P' '17'; +CONNECT ALL '_D0.P' '49'; +CONNECT ALL '_D1.P' '48'; +CONNECT ALL '_D2.P' '47'; +CONNECT ALL '_D3.P' '46'; +CONNECT ALL '_D4.P' '45'; +CONNECT ALL '_D5.P' '44'; +CONNECT ALL '_D6.P' '43'; +CONNECT ALL '_D7.P' '42'; +CONNECT ALL '_DEVSELECT\.P' '41'; +CONNECT ALL '_DMA\.P' '22'; +CONNECT ALL '_DMA_IN.P' '27'; +CONNECT ALL '_DMA_OUT.P' '24'; +CONNECT ALL '_GND.P' '26'; +CONNECT ALL '_INH\.P' '32'; +CONNECT ALL '_INT_IN.P' '28'; +CONNECT ALL '_INT_OUT.P' '23'; +CONNECT ALL '_IOSELECT\.P' '01'; +CONNECT ALL '_IOSTR\.P' '20'; +CONNECT ALL '_IRQ\.P' '30'; +CONNECT ALL '_NC@1.P' '19'; +CONNECT ALL '_NC@2.P' '35'; +CONNECT ALL '_NMI\.P' '29'; +CONNECT ALL '_Q3.P' '37'; +CONNECT ALL '_RDY.P' '21'; +CONNECT ALL '_RES\.P' '31'; +CONNECT ALL '_RW.P' '18'; +CONNECT ALL '_USER1.P' '39'; +TECHNOLOGY ''''''; +PACKAGE 'A2-50PIN-SL1-3' SLOT1-3; +CONNECT ALL '_+5V.P' '25'; +CONNECT ALL '_+12V.P' '50'; +CONNECT ALL '_-5V.P' '34'; +CONNECT ALL '_-12V.P' '33'; +CONNECT ALL '_00.P' '40'; +CONNECT ALL '_01.P' '38'; +CONNECT ALL '_7M.P' '36'; +CONNECT ALL '_A00.P' '02'; +CONNECT ALL '_A01.P' '03'; +CONNECT ALL '_A02.P' '04'; +CONNECT ALL '_A03.P' '05'; +CONNECT ALL '_A04.P' '06'; +CONNECT ALL '_A05.P' '07'; +CONNECT ALL '_A06.P' '08'; +CONNECT ALL '_A07.P' '09'; +CONNECT ALL '_A08.P' '10'; +CONNECT ALL '_A09.P' '11'; +CONNECT ALL '_A10.P' '12'; +CONNECT ALL '_A11.P' '13'; +CONNECT ALL '_A12.P' '14'; +CONNECT ALL '_A13.P' '15'; +CONNECT ALL '_A14.P' '16'; +CONNECT ALL '_A15.P' '17'; +CONNECT ALL '_D0.P' '49'; +CONNECT ALL '_D1.P' '48'; +CONNECT ALL '_D2.P' '47'; +CONNECT ALL '_D3.P' '46'; +CONNECT ALL '_D4.P' '45'; +CONNECT ALL '_D5.P' '44'; +CONNECT ALL '_D6.P' '43'; +CONNECT ALL '_D7.P' '42'; +CONNECT ALL '_DEVSELECT\.P' '41'; +CONNECT ALL '_DMA\.P' '22'; +CONNECT ALL '_DMA_IN.P' '27'; +CONNECT ALL '_DMA_OUT.P' '24'; +CONNECT ALL '_GND.P' '26'; +CONNECT ALL '_INH\.P' '32'; +CONNECT ALL '_INT_IN.P' '28'; +CONNECT ALL '_INT_OUT.P' '23'; +CONNECT ALL '_IOSELECT\.P' '01'; +CONNECT ALL '_IOSTR\.P' '20'; +CONNECT ALL '_IRQ\.P' '30'; +CONNECT ALL '_NC@1.P' '19'; +CONNECT ALL '_NC@2.P' '35'; +CONNECT ALL '_NMI\.P' '29'; +CONNECT ALL '_Q3.P' '37'; +CONNECT ALL '_RDY.P' '21'; +CONNECT ALL '_RES\.P' '31'; +CONNECT ALL '_RW.P' '18'; +CONNECT ALL '_USER1.P' '39'; +TECHNOLOGY ''''''; +PACKAGE 'A2-50PIN-SL4-7' SLOT4-7; +CONNECT ALL '_+5V.P' '25'; +CONNECT ALL '_+12V.P' '50'; +CONNECT ALL '_-5V.P' '34'; +CONNECT ALL '_-12V.P' '33'; +CONNECT ALL '_00.P' '40'; +CONNECT ALL '_01.P' '38'; +CONNECT ALL '_7M.P' '36'; +CONNECT ALL '_A00.P' '02'; +CONNECT ALL '_A01.P' '03'; +CONNECT ALL '_A02.P' '04'; +CONNECT ALL '_A03.P' '05'; +CONNECT ALL '_A04.P' '06'; +CONNECT ALL '_A05.P' '07'; +CONNECT ALL '_A06.P' '08'; +CONNECT ALL '_A07.P' '09'; +CONNECT ALL '_A08.P' '10'; +CONNECT ALL '_A09.P' '11'; +CONNECT ALL '_A10.P' '12'; +CONNECT ALL '_A11.P' '13'; +CONNECT ALL '_A12.P' '14'; +CONNECT ALL '_A13.P' '15'; +CONNECT ALL '_A14.P' '16'; +CONNECT ALL '_A15.P' '17'; +CONNECT ALL '_D0.P' '49'; +CONNECT ALL '_D1.P' '48'; +CONNECT ALL '_D2.P' '47'; +CONNECT ALL '_D3.P' '46'; +CONNECT ALL '_D4.P' '45'; +CONNECT ALL '_D5.P' '44'; +CONNECT ALL '_D6.P' '43'; +CONNECT ALL '_D7.P' '42'; +CONNECT ALL '_DEVSELECT\.P' '41'; +CONNECT ALL '_DMA\.P' '22'; +CONNECT ALL '_DMA_IN.P' '27'; +CONNECT ALL '_DMA_OUT.P' '24'; +CONNECT ALL '_GND.P' '26'; +CONNECT ALL '_INH\.P' '32'; +CONNECT ALL '_INT_IN.P' '28'; +CONNECT ALL '_INT_OUT.P' '23'; +CONNECT ALL '_IOSELECT\.P' '01'; +CONNECT ALL '_IOSTR\.P' '20'; +CONNECT ALL '_IRQ\.P' '30'; +CONNECT ALL '_NC@1.P' '19'; +CONNECT ALL '_NC@2.P' '35'; +CONNECT ALL '_NMI\.P' '29'; +CONNECT ALL '_Q3.P' '37'; +CONNECT ALL '_RDY.P' '21'; +CONNECT ALL '_RES\.P' '31'; +CONNECT ALL '_RW.P' '18'; +CONNECT ALL '_USER1.P' '39'; +TECHNOLOGY ''''''; + +Edit 'LED.DEV'; +DESCRIPTION 'LED

\nOSRAM:
\n\n- CHIPLED
\nLG R971, LG N971, LY N971, LG Q971, LY Q971, LO R971, LY R971\nLH N974, LH R974
\nLS Q976, LO Q976, LY Q976
\nLO Q996
\n\n- Hyper CHIPLED
\nLW Q18S
\nLB Q993, LB Q99A, LB R99A
\n\n- SideLED
\nLS A670, LO A670, LY A670, LG A670, LP A670
\nLB A673, LV A673, LT A673, LW A673
\nLH A674
\nLY A675
\nLS A676, LA A676, LO A676, LY A676, LW A676
\nLS A679, LY A679, LG A679
\n\n- Hyper Micro SIDELED®
\nLS Y876, LA Y876, LO Y876, LY Y876
\nLT Y87S
\n\n- SmartLED
\nLW L88C, LW L88S
\nLB L89C, LB L89S, LG L890
\nLS L89K, LO L89K, LY L89K
\nLS L896, LA L896, LO L896, LY L896
\n\n- TOPLED
\nLS T670, LO T670, LY T670, LG T670, LP T670
\nLSG T670, LSP T670, LSY T670, LOP T670, LYG T670
\nLG T671, LOG T671, LSG T671
\nLB T673, LV T673, LT T673, LW T673
\nLH T674
\nLS T676, LA T676, LO T676, LY T676, LB T676, LH T676, LSB T676, LW T676
\nLB T67C, LV T67C, LT T67C, LS T67K, LO T67K, LY T67K, LW E67C
\nLS E67B, LA E67B, LO E67B, LY E67B, LB E67C, LV E67C, LT E67C
\nLW T67C
\nLS T679, LY T679, LG T679
\nLS T770, LO T770, LY T770, LG T770, LP T770
\nLB T773, LV T773, LT T773, LW T773
\nLH T774
\nLS E675, LA E675, LY E675, LS T675
\nLS T776, LA T776, LO T776, LY T776, LB T776
\nLHGB T686
\nLT T68C, LB T68C
\n\n- Hyper Mini TOPLED®
\nLB M676
\n\n- Mini TOPLED Santana®
\nLG M470
\nLS M47K, LO M47K, LY M47K\n

\nSource: http://www.osram.convergy.de

\n\nLUXEON:
\n- LUMILED®
\nLXK2-PW12-R00, LXK2-PW12-S00, LXK2-PW14-U00, LXK2-PW14-V00
\nLXK2-PM12-R00, LXK2-PM12-S00, LXK2-PM14-U00
\nLXK2-PE12-Q00, LXK2-PE12-R00, LXK2-PE12-S00, LXK2-PE14-T00, LXK2-PE14-U00
\nLXK2-PB12-K00, LXK2-PB12-L00, LXK2-PB12-M00, LXK2-PB14-N00, LXK2-PB14-P00, LXK2-PB14-Q00
\nLXK2-PR12-L00, LXK2-PR12-M00, LXK2-PR14-Q00, LXK2-PR14-R00
\nLXK2-PD12-Q00, LXK2-PD12-R00, LXK2-PD12-S00
\nLXK2-PH12-R00, LXK2-PH12-S00
\nLXK2-PL12-P00, LXK2-PL12-Q00, LXK2-PL12-R00\n

\nSource: www.luxeon.com

\n\nKINGBRIGHT:

\nKA-3528ASYC
\nSource: www.kingbright.com'; +PREFIX 'LED'; +VALUE On; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'LED' 'G$1' (0.000000 0.000000); +PACKAGE 'SMARTLED-TTW' ''; +CONNECT ALL 'G$1.A' 'A@1'; +CONNECT ALL 'G$1.C' 'C@1'; +TECHNOLOGY ''''''; +PACKAGE 'LUMILED' -LUMILED; +CONNECT ALL 'G$1.A' '2+'; +CONNECT ALL 'G$1.C' '4-'; +TECHNOLOGY ''''''; +PACKAGE 'LUMILED+' -LUMILED+; +CONNECT ALL 'G$1.A' '2+'; +CONNECT ALL 'G$1.C' '4-'; +TECHNOLOGY ''''''; +PACKAGE 'LED3MM' 3MM; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'LED5MM' 5MM; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'LED10MM' 10MM; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'Q62902-B152' B152; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'Q62902-B153' B153; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'Q62902-B155' B155; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'Q62902-B156' B156; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'CHIP-LED0603' CHIP-LED0603; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'CHIP-LED0805' CHIP-LED0805; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'CHIPLED-0603-TTW' CHIPLED-0603-TTW; +CONNECT ALL 'G$1.A' 'A@1'; +CONNECT ALL 'G$1.C' 'C@1'; +TECHNOLOGY ''''''; +PACKAGE 'CHIPLED_0603' CHIPLED_0603; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'CHIPLED_0805' CHIPLED_0805; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'CHIPLED_1206' CHIPLED_1206; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'IRL80A' IRL80A; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'KA-3528ASYC' KA-3528ASYC; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'LD260' LD260; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'LSU260' LSU260; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'LZR181' LZR181; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'MICRO-SIDELED' MICRO-SIDELED; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'OSRAM-MINI-TOP-LED' MINI-TOP; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'P-LCC-2' P-LCC-2; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'P-LCC-2-TOPLED-RG' P-LCC-2-BACK; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'P-LCC-4' P-LCC-4; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C@4'; +TECHNOLOGY ''''''; +PACKAGE 'SFH480' SFH480; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'SFH482' SFH482; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'OSRAM-SIDELED' SIDELED; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'SMART-LED' SMART-LED; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'B'; +TECHNOLOGY ''''''; +PACKAGE '1206' SMT1206; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; +PACKAGE 'LED2X5' SQR2X5; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'U57X32' SQR5.7X3.2; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'K'; +TECHNOLOGY ''''''; +PACKAGE 'MINI-TOPLED-SANTANA' TOPLED-SANTANA; +CONNECT ALL 'G$1.A' 'A'; +CONNECT ALL 'G$1.C' 'C'; +TECHNOLOGY ''''''; + +Edit 'MA04-1.DEV'; +DESCRIPTION ''; +PREFIX ''; +VALUE Off; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'MA04-1' 'G$1' (0.000000 0.000000); +PACKAGE 'MA04-1-LOCK' LOCK; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +CONNECT ALL 'G$1.3' '3'; +CONNECT ALL 'G$1.4' '4'; +TECHNOLOGY ''''''; +PACKAGE 'MA04-1' S; +CONNECT ALL 'G$1.1' '1'; +CONNECT ALL 'G$1.2' '2'; +CONNECT ALL 'G$1.3' '3'; +CONNECT ALL 'G$1.4' '4'; +TECHNOLOGY ''''''; + +Edit 'MA06-1.DEV'; +DESCRIPTION 'PIN HEADER'; +PREFIX 'SV'; +VALUE On; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'MA06-1' '1' (0.000000 0.000000); +PACKAGE 'MA06-1-LOCK' LOCK; +CONNECT ALL '1.1' '1'; +CONNECT ALL '1.2' '2'; +CONNECT ALL '1.3' '3'; +CONNECT ALL '1.4' '4'; +CONNECT ALL '1.5' '5'; +CONNECT ALL '1.6' '6'; +TECHNOLOGY ''''''; +PACKAGE 'MA06-1' NORMAL; +CONNECT ALL '1.1' '1'; +CONNECT ALL '1.2' '2'; +CONNECT ALL '1.3' '3'; +CONNECT ALL '1.4' '4'; +CONNECT ALL '1.5' '5'; +CONNECT ALL '1.6' '6'; +TECHNOLOGY ''''''; +ATTRIBUTE 'MF' '' +ATTRIBUTE 'MPN' '' +ATTRIBUTE 'OC_FARNELL' 'unknown' +ATTRIBUTE 'OC_NEWARK' 'unknown' + +Edit '+3V3.DEV'; +DESCRIPTION 'SUPPLY SYMBOL'; +PREFIX '+3V3'; +VALUE Off; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD '+3V3' 'G$1' (0.000000 0.000000); +TECHNOLOGY ''''''; + +Edit '+5V.DEV'; +DESCRIPTION 'SUPPLY SYMBOL'; +PREFIX 'P+'; +VALUE Off; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD '+5V' '1' (0.000000 0.000000); +TECHNOLOGY ''''''; + +Edit 'GND.DEV'; +DESCRIPTION 'SUPPLY SYMBOL'; +PREFIX 'GND'; +VALUE Off; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'GND' '1' (0.000000 0.000000); +TECHNOLOGY ''''''; + +Edit 'MIC5219XX.DEV'; +DESCRIPTION 'VOLTAGE REGULATOR'; +PREFIX 'IC'; +VALUE On; +CHANGE Addlevel Next; +CHANGE Swaplevel 0; +ADD 'MIC5219B' 'G1' (0.000000 0.000000); +PACKAGE 'SOT23-5' ''; +CONNECT ALL 'G1.BYP' '4'; +CONNECT ALL 'G1.EN' '3'; +CONNECT ALL 'G1.GND' '2'; +CONNECT ALL 'G1.IN' '1'; +CONNECT ALL 'G1.OUT' '5'; +TECHNOLOGY ''''''; +ATTRIBUTE 'MF' '' +ATTRIBUTE 'MPN' '' +ATTRIBUTE 'OC_FARNELL' 'unknown' +ATTRIBUTE 'OC_NEWARK' 'unknown' +WRITE; +Set Undo_log On; +Set Select_factor 0.02; +Grid last; diff --git a/eagle/FPGA disk controller/bmowdisk1.lbr b/eagle/FPGA disk controller/bmowdisk1.lbr new file mode 100644 index 0000000..1c3a836 --- /dev/null +++ b/eagle/FPGA disk controller/bmowdisk1.lbr @@ -0,0 +1,502 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +TQFP 100 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/eagle/FPGA disk controller/bom.xlsx b/eagle/FPGA disk controller/bom.xlsx new file mode 100644 index 0000000..3d57adb Binary files /dev/null and b/eagle/FPGA disk controller/bom.xlsx differ diff --git a/eagle/FPGA disk controller/con-apple2.lbr b/eagle/FPGA disk controller/con-apple2.lbr new file mode 100644 index 0000000..e54e4d6 --- /dev/null +++ b/eagle/FPGA disk controller/con-apple2.lbr @@ -0,0 +1,913 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Apple ][ Expansion Card Templates</b> +<br /> +Dimensions are taken from the Apple IIgs Tech Note #28 + + +<B>Apple ][ Peripheral Card</B> +<br /> +Standard 50-pin edge connector for Apple ][ systems +<br /> +Dimensions for slot #1 to #3 +<br /> +Dimensions taken from Tech Note #28 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +7,87 mm +74.93 mm +2.950" +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<B>Apple ][ Peripheral Card</B> +<br /> +Standard 50-pin edge connector for Apple ][ systems +<br /> +Dimensions for slot #4 to #7 +<br /> +Dimensions taken from Tech Note #28 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +7,87 mm +74.93 mm +2.950" +>VALUE + + + + +<B>Apple IIgs Memory Expansion Card</B> +<br /> +The maximum PCB dimensions for an Apple IIgs Memory Expansion Card +<br /> +Dimensions taken from Tech Note #28 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +7,87 mm +57,658 mm +2.270" +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +7,87 mm +74.93 mm +2.950" + + + + + + + + + +>NAME + + + + + +<B>Apple ][ Peripheral Card Connector</B> +<br /> +This is the, default, 50-pin connector for slot #1 to #7 +<br /> +Pins are laid out as seen from the top of the slot + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<B>Apple IIgs Memory Expansion Slot 44-pin</B> +<br /> +This is the 44-pin board dimensions for an Apple IIgs Memory Expansion Card +<br /> +Pins are laid out as seen from the top of the slot. Pin 1 is towards the front of the case/keyboard + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Since Version 6.2.2 text objects can contain more than one line, +which will not be processed correctly with this version. + + + diff --git a/eagle/FPGA disk controller/eagle.epf b/eagle/FPGA disk controller/eagle.epf new file mode 100644 index 0000000..ad9a5e5 --- /dev/null +++ b/eagle/FPGA disk controller/eagle.epf @@ -0,0 +1,469 @@ +[Eagle] +Version="06 06 00" +Platform="Windows" +Serial="62191E841E-LSR-WLM-1EL" +Globals="Globals" +Desktop="Desktop" + +[Globals] +AutoSaveProject=1 +UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/19inch.lbr" +UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/40xx.lbr" +UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/41xx.lbr" +UsedLibrary="C:/Program Files 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+DimensionPrecision=2 +DimensionShowUnit=0 +PinDirection=3 +PinFunction=0 +PinLength=2 +PinVisible=3 +SwapLevel=0 +ArcDirection=0 +AddLevel=2 +PadsSameType=0 +Layer=91 +Views=" 1: -107.888 -36.8209 227.882 130.005" +Sheet=1 + +[Desktop] +Screen="1920 1080" +Window="Win_1" +Window="Win_2" +Window="Win_3" diff --git a/eagle/Liron - original/74xx-us.lbr b/eagle/Liron - original/74xx-us.lbr new file mode 100644 index 0000000..f33ff6c --- /dev/null +++ b/eagle/Liron - original/74xx-us.lbr @@ -0,0 +1,812 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Dual In Line Package</b> + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Dual In Line Package</b> + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Leadless Chip Carrier</b><p> Ceramic Package + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Small Outline package</b> 150 mil + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + +<b>Wide Small Outline package</b> 300 mil + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +>NAME +GND +VCC + + + + +Quad 2-input <b>NAND</b> gate + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Dual 4-input <b>NAND</b> gate + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Dual 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1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" +PadDrills=" 0.5 0.6 0.7 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.8" +ViaDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" +ViaDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6" +HoleDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6" +TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778" +PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27" +PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" +MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0" +DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13" +DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0" +DimensionExtLengths=" 1.27 2.54 1 2 3 0" +DimensionExtOffsets=" 1.27 2.54 1 2 3 0" +SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635" +WireBend=0 +WireBendSet=31 +WireCap=1 +MiterStyle=0 +PadShape=0 +ViaShape=0 +PolygonPour=0 +PolygonRank=0 +PolygonThermals=1 +PolygonOrphans=0 +TextRatio=8 +DimensionUnit=1 +DimensionPrecision=2 +DimensionShowUnit=0 +PinDirection=3 +PinFunction=0 +PinLength=2 +PinVisible=3 +SwapLevel=0 +ArcDirection=0 +AddLevel=2 +PadsSameType=0 +Layer=91 +Views=" 1: -51.7895 -103.761 267.738 101.65" +Sheet=1 + +[Desktop] +Screen="1920 1080" +Window="Win_1" +Window="Win_2" +Window="Win_3" diff --git a/eagle/Liron - original/liron.brd b/eagle/Liron - original/liron.brd new file mode 100644 index 0000000..aeab40e --- /dev/null +++ b/eagle/Liron - original/liron.brd @@ -0,0 +1,1139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>TTL Devices, 74xx Series with US Symbols</b><p> +Based on the following sources: +<ul> +<li>Texas Instruments <i>TTL Data Book</i>&nbsp;&nbsp;&nbsp;Volume 1, 1996. +<li>TTL Data Book, Volume 2 , 1993 +<li>National Seminconductor Databook 1990, ALS/LS Logic +<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0 +<li>http://icmaster.com/ViewCompare.asp +</ul> +<author>Created by librarian@cadsoft.de</author> + + +<b>Dual In Line Package</b> + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Dual In Line Package</b> + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +Generated from <b>liron.sch</b><p> +by exp-lbrs.ulp + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +<b>.050 DIP EDGE CARD CONNECTOR</b> STAGGERED DIP SOLDER<p> +.050 [1.27mm] CONTACT CENTERS .610" INSULATEOR HEIGHT<br> +Source: .050 DIP EDGE CARD.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>SUB-D</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +10 +11 +19 + + + + + + + + + + + +>NAME +>VALUE + + + + +<b>Generic Memories</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>Dual In Line Package</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +<b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie für +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab. +<b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/eagle/Liron - original/liron.lbr b/eagle/Liron - original/liron.lbr new file mode 100644 index 0000000..85e90d4 --- /dev/null +++ b/eagle/Liron - original/liron.lbr @@ -0,0 +1,1485 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Generated from <b>liron.sch</b><p> +by exp-lbrs.ulp + + +<b>Dual In Line Package</b> + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Dual In Line Package</b> + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Leadless Chip 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/eagle/Liron - original/pinhead.lbr b/eagle/Liron - original/pinhead.lbr new file mode 100644 index 0000000..f329014 --- /dev/null +++ b/eagle/Liron - original/pinhead.lbr @@ -0,0 +1,900 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>UNSH HEADER</b> 2.0mm VERTICAL TMT<p> +Source: https://portal.fciconnect.com/res/en/pdffiles/doc_search/57102.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lattice/._Real_._Math_.vhd b/lattice/._Real_._Math_.vhd new file mode 100644 index 0000000..ad185b2 --- /dev/null +++ b/lattice/._Real_._Math_.vhd @@ -0,0 +1,2574 @@ + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package defines a standard for designers to use in +-- describing VHDL models that make use of common REAL constants +-- and common REAL elementary mathematical functions. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076- +-- 1993. +-- +-- Notes: +-- No declarations or definitions shall be included in, or +-- excluded from, this package. +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to provide a guideline for implementations to +-- verify their implementation of MATH_REAL. Tool developers may +-- choose to implement the package body in the most efficient +-- manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package MATH_REAL is + constant CopyRightNotice: STRING + := "Copyright 1996 IEEE. All rights reserved."; + + -- + -- Constant Definitions + -- + constant MATH_E : REAL := 2.71828_18284_59045_23536; + -- Value of e + constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; + -- Value of 1/e + constant MATH_PI : REAL := 3.14159_26535_89793_23846; + -- Value of pi + constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; + -- Value of 2*pi + constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; + -- Value of 1/pi + constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; + -- Value of pi/2 + constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; + -- Value of pi/3 + constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; + -- Value of pi/4 + constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; + -- Value 3*pi/2 + constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; + -- Natural log of 2 + constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; + -- Natural log of 10 + constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; + -- Log base 2 of e + constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; + -- Log base 10 of e + constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; + -- square root of 2 + constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; + -- square root of 1/2 + constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; + -- square root of pi + constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; + -- Conversion factor from degree to radian + constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; + -- Conversion factor from radian to degree + + -- + -- Function Declarations + -- + function SIGN (X: in REAL ) return REAL; + -- Purpose: + -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIGN(X)) <= 1.0 + -- Notes: + -- None + + function CEIL (X : in REAL ) return REAL; + -- Purpose: + -- Returns smallest INTEGER value (as REAL) not less than X + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CEIL(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function FLOOR (X : in REAL ) return REAL; + -- Purpose: + -- Returns largest INTEGER value (as REAL) not greater than X + -- Special values: + -- FLOOR(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- FLOOR(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function ROUND (X : in REAL ) return REAL; + -- Purpose: + -- Rounds X to the nearest integer value (as real). If X is + -- halfway between two integers, rounding is away from 0.0 + -- Special values: + -- ROUND(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ROUND(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function TRUNC (X : in REAL ) return REAL; + -- Purpose: + -- Truncates X towards 0.0 and returns truncated value + -- Special values: + -- TRUNC(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- TRUNC(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function "MOD" (X, Y: in REAL ) return REAL; + -- Purpose: + -- Returns floating point modulus of X/Y, with the same sign as + -- Y, and absolute value less than the absolute value of Y, and + -- for some INTEGER value N the result satisfies the relation + -- X = Y*N + MOD(X,Y) + -- Special values: + -- None + -- Domain: + -- X in REAL; Y in REAL and Y /= 0.0 + -- Error conditions: + -- Error if Y = 0.0 + -- Range: + -- ABS(MOD(X,Y)) < ABS(Y) + -- Notes: + -- None + + function REALMAX (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically larger of X and Y + -- Special values: + -- REALMAX(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMAX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function REALMIN (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically smaller of X and Y + -- Special values: + -- REALMIN(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMIN(X,Y) is mathematically unbounded + -- Notes: + -- None + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); + -- Purpose: + -- Returns, in X, a pseudo-random number with uniform + -- distribution in the open interval (0.0, 1.0). + -- Special values: + -- None + -- Domain: + -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 + -- Error conditions: + -- Error if SEED1 or SEED2 outside of valid domain + -- Range: + -- 0.0 < X < 1.0 + -- Notes: + -- a) The semantics for this function are described by the + -- algorithm published by Pierre L'Ecuyer in "Communications + -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. + -- The algorithm is based on the combination of two + -- multiplicative linear congruential generators for 32-bit + -- platforms. + -- + -- b) Before the first call to UNIFORM, the seed values + -- (SEED1, SEED2) have to be initialized to values in the range + -- [1, 2147483562] and [1, 2147483398] respectively. The + -- seed values are modified after each call to UNIFORM. + -- + -- c) This random number generator is portable for 32-bit + -- computers, and it has a period of ~2.30584*(10**18) for each + -- set of seed values. + -- + -- d) For information on spectral tests for the algorithm, refer + -- to the L'Ecuyer article. + + function SQRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns square root of X + -- Special values: + -- SQRT(0.0) = 0.0 + -- SQRT(1.0) = 1.0 + -- Domain: + -- X >= 0.0 + -- Error conditions: + -- Error if X < 0.0 + -- Range: + -- SQRT(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of SQRT is + -- approximately given by: + -- SQRT(X) <= SQRT(REAL'HIGH) + + function CBRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns cube root of X + -- Special values: + -- CBRT(0.0) = 0.0 + -- CBRT(1.0) = 1.0 + -- CBRT(-1.0) = -1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CBRT(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of CBRT is approximately given by: + -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) + + function "**" (X : in INTEGER; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0 + -- 0**Y = 0.0; Y > 0.0 + -- X**1.0 = REAL(X); X >= 0 + -- 1**Y = 1.0 + -- Domain: + -- X > 0 + -- X = 0 for Y > 0.0 + -- X < 0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0 and Y /= 0.0 + -- Error if X = 0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function "**" (X : in REAL; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0.0 + -- 0.0**Y = 0.0; Y > 0.0 + -- X**1.0 = X; X >= 0.0 + -- 1.0**Y = 1.0 + -- Domain: + -- X > 0.0 + -- X = 0.0 for Y > 0.0 + -- X < 0.0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0.0 and Y /= 0.0 + -- Error if X = 0.0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function EXP (X : in REAL ) return REAL; + -- Purpose: + -- Returns e**X; where e = MATH_E + -- Special values: + -- EXP(0.0) = 1.0 + -- EXP(1.0) = MATH_E + -- EXP(-1.0) = MATH_1_OVER_E + -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) + -- Domain: + -- X in REAL such that EXP(X) <= REAL'HIGH + -- Error conditions: + -- Error if X > LOG(REAL'HIGH) + -- Range: + -- EXP(X) >= 0.0 + -- Notes: + -- a) The usable domain of EXP is approximately given by: + -- X <= LOG(REAL'HIGH) + + function LOG (X : in REAL ) return REAL; + -- Purpose: + -- Returns natural logarithm of X + -- Special values: + -- LOG(1.0) = 0.0 + -- LOG(MATH_E) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG is approximately given by: + -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) + + function LOG2 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 2 of X + -- Special values: + -- LOG2(1.0) = 0.0 + -- LOG2(2.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG2(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG2 is approximately given by: + -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) + + function LOG10 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 10 of X + -- Special values: + -- LOG10(1.0) = 0.0 + -- LOG10(10.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG10(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG10 is approximately given by: + -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) + + function LOG (X: in REAL; BASE: in REAL) return REAL; + -- Purpose: + -- Returns logarithm base BASE of X + -- Special values: + -- LOG(1.0, BASE) = 0.0 + -- LOG(BASE, BASE) = 1.0 + -- Domain: + -- X > 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(X, BASE) is mathematically unbounded + -- Notes: + -- a) When BASE > 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) + -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) + + function SIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns sine of X; X in radians + -- Special values: + -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function COS ( X : in REAL ) return REAL; + -- Purpose: + -- Returns cosine of X; X in radians + -- Special values: + -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER + -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(COS(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function TAN (X : in REAL ) return REAL; + -- Purpose: + -- Returns tangent of X; X in radians + -- Special values: + -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL and + -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER + -- Error conditions: + -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an + -- INTEGER + -- Range: + -- TAN(X) is mathematically unbounded + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function ARCSIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse sine of X + -- Special values: + -- ARCSIN(0.0) = 0.0 + -- ARCSIN(1.0) = MATH_PI_OVER_2 + -- ARCSIN(-1.0) = -MATH_PI_OVER_2 + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCCOS (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse cosine of X + -- Special values: + -- ARCCOS(1.0) = 0.0 + -- ARCCOS(0.0) = MATH_PI_OVER_2 + -- ARCCOS(-1.0) = MATH_PI + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- 0.0 <= ARCCOS(X) <= MATH_PI + -- Notes: + -- None + + function ARCTAN (Y : in REAL) return REAL; + -- Purpose: + -- Returns the value of the angle in radians of the point + -- (1.0, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0) = 0.0 + -- Domain: + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCTAN (Y : in REAL; X : in REAL) return REAL; + -- Purpose: + -- Returns the principal value of the angle in radians of + -- the point (X, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0, X) = 0.0 if X > 0.0 + -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 + -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 + -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 + -- Domain: + -- Y in REAL + -- X in REAL, X /= 0.0 when Y = 0.0 + -- Error conditions: + -- Error if X = 0.0 and Y = 0.0 + -- Range: + -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI + -- Notes: + -- None + + function SINH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic sine of X + -- Special values: + -- SINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- SINH(X) is mathematically unbounded + -- Notes: + -- a) The usable domain of SINH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + + function COSH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic cosine of X + -- Special values: + -- COSH(0.0) = 1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- COSH(X) >= 1.0 + -- Notes: + -- a) The usable domain of COSH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + function TANH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic tangent of X + -- Special values: + -- TANH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(TANH(X)) <= 1.0 + -- Notes: + -- None + + function ARCSINH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic sine of X + -- Special values: + -- ARCSINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ARCSINH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCSINH is approximately given by: + -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) + + function ARCCOSH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic cosine of X + -- Special values: + -- ARCCOSH(1.0) = 0.0 + -- Domain: + -- X >= 1.0 + -- Error conditions: + -- Error if X < 1.0 + -- Range: + -- ARCCOSH(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of ARCCOSH is + -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) + + function ARCTANH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic tangent of X + -- Special values: + -- ARCTANH(0.0) = 0.0 + -- Domain: + -- ABS(X) < 1.0 + -- Error conditions: + -- Error if ABS(X) >= 1.0 + -- Range: + -- ARCTANH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCTANH is approximately given by: + -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) + +end MATH_REAL; + + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. + +-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. + +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package body is a nonnormative implementation of the +-- functionality defined in the MATH_REAL package declaration. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076 +-- -1993. +-- +-- Notes: +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to clarify such semantics and provide a +-- guideline for implementations to verify their implementation +-- of MATH_REAL. Tool developers may choose to implement +-- the package body in the most efficient manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package body MATH_REAL is + + -- + -- Local Constants for Use in the Package Body Only + -- + constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 + constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 + constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi + constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic + constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries + constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria + constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic + + -- + -- Local Type Declarations for Cordic Operations + -- + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; + subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); + subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); + subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); + subtype QUADRANT is INTEGER range 0 to 3; + type CORDIC_MODE_TYPE is (ROTATION, VECTORING); + + -- + -- Auxiliary Functions for Cordic Algorithms + -- + function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; + NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is + -- Description: + -- Returns power of two for a vector of values + -- Notes: + -- None + -- + variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); + variable TEMP : REAL := INITIAL_VALUE; + variable FLAG : BOOLEAN := TRUE; + begin + for I in 0 to NUMBER_OF_VALUES loop + V(I) := TEMP; + for P in D'RANGE loop + if I = D(P) then + FLAG := FALSE; + exit; + end if; + end loop; + if FLAG then + TEMP := TEMP/2.0; + end if; + FLAG := TRUE; + end loop; + return V; + end POWER_OF_2_SERIES; + + + constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( + NATURAL_VECTOR'(100, 90),1.0, + MAX_ITER); + + constant EPSILON : REAL_VECTOR_N := ( + 7.8539816339744827e-01, + 4.6364760900080606e-01, + 2.4497866312686413e-01, + 1.2435499454676144e-01, + 6.2418809995957351e-02, + 3.1239833430268277e-02, + 1.5623728620476830e-02, + 7.8123410601011116e-03, + 3.9062301319669717e-03, + 1.9531225164788189e-03, + 9.7656218955931937e-04, + 4.8828121119489829e-04, + 2.4414062014936175e-04, + 1.2207031189367021e-04, + 6.1035156174208768e-05, + 3.0517578115526093e-05, + 1.5258789061315760e-05, + 7.6293945311019699e-06, + 3.8146972656064960e-06, + 1.9073486328101870e-06, + 9.5367431640596080e-07, + 4.7683715820308876e-07, + 2.3841857910155801e-07, + 1.1920928955078067e-07, + 5.9604644775390553e-08, + 2.9802322387695303e-08, + 1.4901161193847654e-08, + 7.4505805969238281e-09 + ); + + function CORDIC ( X0 : in REAL; + Y0 : in REAL; + Z0 : in REAL; + N : in NATURAL; -- Precision factor + CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) + -- or vectoring (Y -> 0) + ) return REAL_ARR_3 is + -- Description: + -- Compute cordic values + -- Notes: + -- None + variable X : REAL := X0; + variable Y : REAL := Y0; + variable Z : REAL := Z0; + variable X_TEMP : REAL; + begin + if CORDIC_MODE = ROTATION then + for K in 0 to N loop + X_TEMP := X; + if ( Z >= 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + else + for K in 0 to N loop + X_TEMP := X; + if ( Y < 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + end if; + return REAL_ARR_3'(X, Y, Z); + end CORDIC; + + -- + -- Bodies for Global Mathematical Functions Start Here + -- + function SIGN (X: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + if ( X > 0.0 ) then + return 1.0; + elsif ( X < 0.0 ) then + return -1.0; + else + return 0.0; + end if; + end SIGN; + + function CEIL (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is X <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS(X) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD >= X then + return RD; + else + return RD + 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD <= X then + return RD + 1.0; + else + return RD; + end if; + end if; + end CEIL; + + function FLOOR (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is ABS(X) <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS( X ) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD <= X then + return RD; + else + return RD - 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD >= X then + return RD - 1.0; + else + return RD; + end if; + end if; + end FLOOR; + + function ROUND (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X + 0.5) if X > 0 + -- c) Returns CEIL(X - 0.5) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X + 0.5); + elsif X < 0.0 then + return CEIL( X - 0.5); + else + return 0.0; + end if; + end ROUND; + + function TRUNC (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X) if X > 0 + -- c) Returns CEIL(X) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X); + elsif X < 0.0 then + return CEIL( X); + else + return 0.0; + end if; + end TRUNC; + + + + + function "MOD" (X, Y: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable XNEGATIVE : BOOLEAN := X < 0.0; + variable YNEGATIVE : BOOLEAN := Y < 0.0; + variable VALUE : REAL; + begin + -- Check validity of input arguments + if (Y = 0.0) then + assert FALSE + report "MOD(X, 0.0) is undefined" + severity ERROR; + return 0.0; + end if; + + -- Compute value + if ( XNEGATIVE ) then + if ( YNEGATIVE ) then + VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + end if; + else + if ( YNEGATIVE ) then + VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + end if; + end if; + + return VALUE; + end "MOD"; + + + function REALMAX (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMAX(X,Y) = X when X = Y + -- + begin + if X >= Y then + return X; + else + return Y; + end if; + end REALMAX; + + function REALMIN (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMIN(X,Y) = X when X = Y + -- + begin + if X <= Y then + return X; + else + return Y; + end if; + end REALMIN; + + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + -- + variable Z, K: INTEGER; + variable TSEED1 : INTEGER := INTEGER'(SEED1); + variable TSEED2 : INTEGER := INTEGER'(SEED2); + begin + -- Check validity of arguments + if SEED1 > 2147483562 then + assert FALSE + report "SEED1 > 2147483562 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + if SEED2 > 2147483398 then + assert FALSE + report "SEED2 > 2147483398 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + -- Compute new seed values and pseudo-random number + K := TSEED1/53668; + TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; + + if TSEED1 < 0 then + TSEED1 := TSEED1 + 2147483563; + end if; + + K := TSEED2/52774; + TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; + + if TSEED2 < 0 then + TSEED2 := TSEED2 + 2147483399; + end if; + + Z := TSEED1 - TSEED2; + if Z < 1 then + Z := Z + 2147483562; + end if; + + -- Get output values + SEED1 := POSITIVE'(TSEED1); + SEED2 := POSITIVE'(TSEED2); + X := REAL(Z)*4.656613e-10; + end UNIFORM; + + + + function SQRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = 0.5*[F(n) + x/F(n)] + -- b) Returns 0.0 on error + -- + + constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor + + variable INIVAL: REAL; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + -- Check validity of argument + if ( X < 0.0 ) then + assert FALSE + report "X < 0.0 in SQRT(X)" + severity ERROR; + return 0.0; + end if; + + -- Get the square root for special cases + if X = 0.0 then + return 0.0; + else + if ( X = 1.0 ) then + return 1.0; + end if; + end if; + + -- Get the square root for general cases + INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise + OLDVAL := INIVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + + -- Check for relative and absolute error and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT) ) loop + OLDVAL := NEWVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + COUNT := COUNT + 1; + end loop; + return NEWVAL; + end SQRT; + + function CBRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; + -- + constant EPS : REAL := BASE_EPS*BASE_EPS; + + variable INIVAL: REAL; + variable XLOCAL : REAL := X; + variable NEGATIVE : BOOLEAN := X < 0.0; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + + -- Compute root for special cases + if X = 0.0 then + return 0.0; + elsif ( X = 1.0 ) then + return 1.0; + else + if X = -1.0 then + return -1.0; + end if; + end if; + + -- Compute root for general cases + if NEGATIVE then + XLOCAL := -X; + end if; + + INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but + -- imprecise + OLDVAL := INIVAL; + NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR + (ABS(NEWVAL - OLDVAL) > EPS ) ) AND + ( COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + COUNT := COUNT + 1; + end loop; + + if NEGATIVE then + NEWVAL := -NEWVAL; + end if; + + return NEWVAL; + end CBRT; + + function "**" (X : in INTEGER; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (REAL(X)); + end if; + + -- Get value for general case + return EXP (Y * LOG (REAL(X))); + end "**"; + + function "**" (X : in REAL; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0.0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0.0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0.0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1.0 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0.0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (X); + end if; + + -- Get value for general case + return EXP (Y * LOG (X)); + end "**"; + + function EXP (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) This function computes the exponential using the following + -- series: + -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 + -- and reduces argument X to take advantage of exp(x+y) = + -- exp(x)*exp(y) + -- + -- b) This implementation limits X to be less than LOG(REAL'HIGH) + -- to avoid overflow. Returns REAL'HIGH when X reaches that + -- limit + -- + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria + + variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument + variable XLOCAL : REAL := ABS(X); -- Use positive value + variable OLDVAL: REAL ; + variable COUNT: INTEGER ; + variable NEWVAL: REAL ; + variable LAST_TERM: REAL ; + variable FACTOR : REAL := 1.0; + + begin + -- Compute value for special cases + if X = 0.0 then + return 1.0; + end if; + + if XLOCAL = 1.0 then + if RECIPROCAL then + return MATH_1_OVER_E; + else + return MATH_E; + end if; + end if; + + if XLOCAL = 2.0 then + if RECIPROCAL then + return 1.0/MATH_E_P2; + else + return MATH_E_P2; + end if; + end if; + + if XLOCAL = 10.0 then + if RECIPROCAL then + return 1.0/MATH_E_P10; + else + return MATH_E_P10; + end if; + end if; + + if XLOCAL > LOG(REAL'HIGH) then + if RECIPROCAL then + return 0.0; + else + assert FALSE + report "X > LOG(REAL'HIGH) in EXP(X)" + severity NOTE; + return REAL'HIGH; + end if; + end if; + + -- Reduce argument to ABS(X) < 1.0 + while XLOCAL > 10.0 loop + XLOCAL := XLOCAL - 10.0; + FACTOR := FACTOR*MATH_E_P10; + end loop; + + while XLOCAL > 1.0 loop + XLOCAL := XLOCAL - 1.0; + FACTOR := FACTOR*MATH_E; + end loop; + + -- Compute value for case 0 < XLOCAL < 1 + OLDVAL := 1.0; + LAST_TERM := XLOCAL; + NEWVAL:= OLDVAL + LAST_TERM; + COUNT := 2; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); + NEWVAL := OLDVAL + LAST_TERM; + COUNT := COUNT + 1; + end loop; + + -- Compute final value using exp(x+y) = exp(x)*exp(y) + NEWVAL := NEWVAL*FACTOR; + + if RECIPROCAL then + NEWVAL := 1.0/NEWVAL; + end if; + + return NEWVAL; + end EXP; + + + -- + -- Auxiliary Functions to Compute LOG + -- + function ILOGB(X: in REAL) return INTEGER IS + -- Description: + -- Returns n such that -1 <= ABS(X)/2^n < 2 + -- Notes: + -- None + + variable N: INTEGER := 0; + variable Y: REAL := ABS(X); + + begin + if(Y = 1.0 or Y = 0.0) then + return 0; + end if; + + if( Y > 1.0) then + while Y >= 2.0 loop + Y := Y/2.0; + N := N+1; + end loop; + return N; + end if; + + -- O < Y < 1 + while Y < 1.0 loop + Y := Y*2.0; + N := N -1; + end loop; + return N; + end ILOGB; + + function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS + -- Description: + -- Returns X*2^n + -- Notes: + -- None + begin + return X*(2.0 ** N); + end LDEXP; + + function LOG (X : in REAL ) return REAL IS + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- + -- Notes: + -- a) Returns REAL'LOW on error + -- + -- Copyright (c) 1992 Regents of the University of California. + -- All rights reserved. + -- + -- Redistribution and use in source and binary forms, with or without + -- modification, are permitted provided that the following conditions + -- are met: + -- 1. Redistributions of source code must retain the above copyright + -- notice, this list of conditions and the following disclaimer. + -- 2. Redistributions in binary form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- 3. All advertising materials mentioning features or use of this + -- software must display the following acknowledgement: + -- This product includes software developed by the University of + -- California, Berkeley and its contributors. + -- 4. Neither the name of the University nor the names of its + -- contributors may be used to endorse or promote products derived + -- from this software without specific prior written permission. + -- + -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR + -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + -- DAMAGE. + -- + -- NOTE: This VHDL version was generated using the C version of the + -- original function by the IEEE VHDL Mathematical Package + -- Working Group (CS/JT) + + constant N: INTEGER := 128; + + -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. + -- Used for generation of extend precision logarithms. + -- The constant 35184372088832 is 2^45, so the divide is exact. + -- It ensures correct reading of logF_head, even for inaccurate + -- decimal-to-binary conversion routines. (Everybody gets the + -- right answer for INTEGERs less than 2^53.) + -- Values for LOG(F) were generated using error < 10^-57 absolute + -- with the bc -l package. + + type REAL_VECTOR is array (NATURAL range <>) of REAL; + + constant A1:REAL := 0.08333333333333178827; + constant A2:REAL := 0.01250000000377174923; + constant A3:REAL := 0.002232139987919447809; + constant A4:REAL := 0.0004348877777076145742; + + constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( + 0.0, + 0.007782140442060381246, + 0.015504186535963526694, + 0.023167059281547608406, + 0.030771658666765233647, + 0.038318864302141264488, + 0.045809536031242714670, + 0.053244514518837604555, + 0.060624621816486978786, + 0.067950661908525944454, + 0.075223421237524235039, + 0.082443669210988446138, + 0.089612158689760690322, + 0.096729626458454731618, + 0.103796793681567578460, + 0.110814366340264314203, + 0.117783035656430001836, + 0.124703478501032805070, + 0.131576357788617315236, + 0.138402322859292326029, + 0.145182009844575077295, + 0.151916042025732167530, + 0.158605030176659056451, + 0.165249572895390883786, + 0.171850256926518341060, + 0.178407657472689606947, + 0.184922338493834104156, + 0.191394852999565046047, + 0.197825743329758552135, + 0.204215541428766300668, + 0.210564769107350002741, + 0.216873938300523150246, + 0.223143551314024080056, + 0.229374101064877322642, + 0.235566071312860003672, + 0.241719936886966024758, + 0.247836163904594286577, + 0.253915209980732470285, + 0.259957524436686071567, + 0.265963548496984003577, + 0.271933715484010463114, + 0.277868451003087102435, + 0.283768173130738432519, + 0.289633292582948342896, + 0.295464212893421063199, + 0.301261330578199704177, + 0.307025035294827830512, + 0.312755710004239517729, + 0.318453731118097493890, + 0.324119468654316733591, + 0.329753286372579168528, + 0.335355541920762334484, + 0.340926586970454081892, + 0.346466767346100823488, + 0.351976423156884266063, + 0.357455888922231679316, + 0.362905493689140712376, + 0.368325561158599157352, + 0.373716409793814818840, + 0.379078352934811846353, + 0.384411698910298582632, + 0.389716751140440464951, + 0.394993808240542421117, + 0.400243164127459749579, + 0.405465108107819105498, + 0.410659924985338875558, + 0.415827895143593195825, + 0.420969294644237379543, + 0.426084395310681429691, + 0.431173464818130014464, + 0.436236766774527495726, + 0.441274560805140936281, + 0.446287102628048160113, + 0.451274644139630254358, + 0.456237433481874177232, + 0.461175715122408291790, + 0.466089729924533457960, + 0.470979715219073113985, + 0.475845904869856894947, + 0.480688529345570714212, + 0.485507815781602403149, + 0.490303988045525329653, + 0.495077266798034543171, + 0.499827869556611403822, + 0.504556010751912253908, + 0.509261901790523552335, + 0.513945751101346104405, + 0.518607764208354637958, + 0.523248143765158602036, + 0.527867089620485785417, + 0.532464798869114019908, + 0.537041465897345915436, + 0.541597282432121573947, + 0.546132437597407260909, + 0.550647117952394182793, + 0.555141507540611200965, + 0.559615787935399566777, + 0.564070138285387656651, + 0.568504735352689749561, + 0.572919753562018740922, + 0.577315365035246941260, + 0.581691739635061821900, + 0.586049045003164792433, + 0.590387446602107957005, + 0.594707107746216934174, + 0.599008189645246602594, + 0.603290851438941899687, + 0.607555250224322662688, + 0.611801541106615331955, + 0.616029877215623855590, + 0.620240409751204424537, + 0.624433288012369303032, + 0.628608659422752680256, + 0.632766669570628437213, + 0.636907462236194987781, + 0.641031179420679109171, + 0.645137961373620782978, + 0.649227946625615004450, + 0.653301272011958644725, + 0.657358072709030238911, + 0.661398482245203922502, + 0.665422632544505177065, + 0.669430653942981734871, + 0.673422675212350441142, + 0.677398823590920073911, + 0.681359224807238206267, + 0.685304003098281100392, + 0.689233281238557538017, + 0.693147180560117703862); + + constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( + 0.0, + -0.00000000000000543229938420049, + 0.00000000000000172745674997061, + -0.00000000000001323017818229233, + -0.00000000000001154527628289872, + -0.00000000000000466529469958300, + 0.00000000000005148849572685810, + -0.00000000000002532168943117445, + -0.00000000000005213620639136504, + -0.00000000000001819506003016881, + 0.00000000000006329065958724544, + 0.00000000000008614512936087814, + -0.00000000000007355770219435028, + 0.00000000000009638067658552277, + 0.00000000000007598636597194141, + 0.00000000000002579999128306990, + -0.00000000000004654729747598444, + -0.00000000000007556920687451336, + 0.00000000000010195735223708472, + -0.00000000000017319034406422306, + -0.00000000000007718001336828098, + 0.00000000000010980754099855238, + -0.00000000000002047235780046195, + -0.00000000000008372091099235912, + 0.00000000000014088127937111135, + 0.00000000000012869017157588257, + 0.00000000000017788850778198106, + 0.00000000000006440856150696891, + 0.00000000000016132822667240822, + -0.00000000000007540916511956188, + -0.00000000000000036507188831790, + 0.00000000000009120937249914984, + 0.00000000000018567570959796010, + -0.00000000000003149265065191483, + -0.00000000000009309459495196889, + 0.00000000000017914338601329117, + -0.00000000000001302979717330866, + 0.00000000000023097385217586939, + 0.00000000000023999540484211737, + 0.00000000000015393776174455408, + -0.00000000000036870428315837678, + 0.00000000000036920375082080089, + -0.00000000000009383417223663699, + 0.00000000000009433398189512690, + 0.00000000000041481318704258568, + -0.00000000000003792316480209314, + 0.00000000000008403156304792424, + -0.00000000000034262934348285429, + 0.00000000000043712191957429145, + -0.00000000000010475750058776541, + -0.00000000000011118671389559323, + 0.00000000000037549577257259853, + 0.00000000000013912841212197565, + 0.00000000000010775743037572640, + 0.00000000000029391859187648000, + -0.00000000000042790509060060774, + 0.00000000000022774076114039555, + 0.00000000000010849569622967912, + -0.00000000000023073801945705758, + 0.00000000000015761203773969435, + 0.00000000000003345710269544082, + -0.00000000000041525158063436123, + 0.00000000000032655698896907146, + -0.00000000000044704265010452446, + 0.00000000000034527647952039772, + -0.00000000000007048962392109746, + 0.00000000000011776978751369214, + -0.00000000000010774341461609578, + 0.00000000000021863343293215910, + 0.00000000000024132639491333131, + 0.00000000000039057462209830700, + -0.00000000000026570679203560751, + 0.00000000000037135141919592021, + -0.00000000000017166921336082431, + -0.00000000000028658285157914353, + -0.00000000000023812542263446809, + 0.00000000000006576659768580062, + -0.00000000000028210143846181267, + 0.00000000000010701931762114254, + 0.00000000000018119346366441110, + 0.00000000000009840465278232627, + -0.00000000000033149150282752542, + -0.00000000000018302857356041668, + -0.00000000000016207400156744949, + 0.00000000000048303314949553201, + -0.00000000000071560553172382115, + 0.00000000000088821239518571855, + -0.00000000000030900580513238244, + -0.00000000000061076551972851496, + 0.00000000000035659969663347830, + 0.00000000000035782396591276383, + -0.00000000000046226087001544578, + 0.00000000000062279762917225156, + 0.00000000000072838947272065741, + 0.00000000000026809646615211673, + -0.00000000000010960825046059278, + 0.00000000000002311949383800537, + -0.00000000000058469058005299247, + -0.00000000000002103748251144494, + -0.00000000000023323182945587408, + -0.00000000000042333694288141916, + -0.00000000000043933937969737844, + 0.00000000000041341647073835565, + 0.00000000000006841763641591466, + 0.00000000000047585534004430641, + 0.00000000000083679678674757695, + -0.00000000000085763734646658640, + 0.00000000000021913281229340092, + -0.00000000000062242842536431148, + -0.00000000000010983594325438430, + 0.00000000000065310431377633651, + -0.00000000000047580199021710769, + -0.00000000000037854251265457040, + 0.00000000000040939233218678664, + 0.00000000000087424383914858291, + 0.00000000000025218188456842882, + -0.00000000000003608131360422557, + -0.00000000000050518555924280902, + 0.00000000000078699403323355317, + -0.00000000000067020876961949060, + 0.00000000000016108575753932458, + 0.00000000000058527188436251509, + -0.00000000000035246757297904791, + -0.00000000000018372084495629058, + 0.00000000000088606689813494916, + 0.00000000000066486268071468700, + 0.00000000000063831615170646519, + 0.00000000000025144230728376072, + -0.00000000000017239444525614834); + + variable M, J:INTEGER; + variable F1, F2, G, Q, U, U2, V: REAL; + variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs + variable ONE: REAL := 1.0; --Made variable so no constant folding occurs + + -- double logb(), ldexp(); + + variable U1:REAL; + + begin + + -- Check validity of argument + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = MATH_E ) then + return 1.0; + end if; + + -- Argument reduction: 1 <= g < 2; x/2^m = g; + -- y = F*(1 + f/F) for |f| <= 2^-8 + + M := ILOGB(X); + G := LDEXP(X, -M); + J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding + F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] + F2 := G - F1; + + -- Approximate expansion for log(1+f2/F1) ~= u + q + G := 1.0/(2.0*F1+F2); + U := 2.0*F2*G; + V := U*U; + Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); + + -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, + -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. + -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. + -- + if ( J /= 0 or M /= 0) then + U1 := U + 513.0; + U1 := U1 - 513.0; + + -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero + -- u1 = u to 24 bits. + -- + else + U1 := U; + --TRUNC(U1); --In c this is u1 = (double) (float) (u1) + end if; + + U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; + -- u1 + u2 = 2f/(2F+f) to extra precision. + + -- log(x) = log(2^m*F1*(1+f2/F1)) = + -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); + -- (exact) + (tiny) + + U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact + U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny + U2 := U2 + LOGF_TAIL(N)*REAL(M); + return (U1 + U2); + end LOG; + + + function LOG2 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG2(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 2.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG2_OF_E*LOG(X) ); + end LOG2; + + + function LOG10 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG10(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 10.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG10_OF_E*LOG(X) ); + end LOG10; + + + function LOG (X: in REAL; BASE: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = BASE ) then + return 1.0; + end if; + + -- Compute value for general case + return ( LOG(X)/LOG(BASE)); + end LOG; + + + function SIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) SIN(-X) = -SIN(X) + -- b) SIN(X) = X if ABS(X) < EPS + -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS + -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) + -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS + -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in SIN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then + return 0.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 then + if NEGATIVE then + return -1.0; + else + return 1.0; + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + if NEGATIVE then + return 1.0; + else + return -1.0; + end if; + end if; + + if XLOCAL < EPS then + if NEGATIVE then + return -XLOCAL; + else + return XLOCAL; + end if; + else + if XLOCAL < BASE_EPS then + TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_2_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + -- Compute value for general cases + if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then + VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); + end if; + + N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); + case QUADRANT( N mod 4) is + when 0 => + VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); + when 1 => + VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, + ROTATION)(0); + when 2 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); + when 3 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, + ROTATION)(0); + end case; + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end SIN; + + + function COS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) COS(-X) = COS(X) + -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) + -- c) COS(MATH_PI + X) = -COS(X) + -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS + -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in COS(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then + return 1.0; + end if; + + if XLOCAL = MATH_PI then + return -1.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then + return 0.0; + end if; + + TEMP := ABS(XLOCAL); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS(XLOCAL -MATH_2_PI); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS (XLOCAL - MATH_PI); + if TEMP < EPS then + return (-1.0 + 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + -- Compute value for general cases + return SIN(MATH_PI_OVER_2 - XLOCAL); + end COS; + + function TAN (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) TAN(0.0) = 0.0 + -- b) TAN(-X) = -TAN(X) + -- c) Returns REAL'LOW on error if X < 0.0 + -- d) Returns REAL'HIGH on error if X > 0.0 + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X) ; + variable VALUE: REAL; + variable TEMP : REAL; + + begin + -- Make 0.0 <= XLOCAL <= MATH_2_PI + if XLOCAL > MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in TAN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Check validity of argument + if XLOCAL = MATH_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'LOW); + else + return(REAL'HIGH); + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'HIGH); + else + return(REAL'LOW); + end if; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_PI then + return 0.0; + end if; + + -- Compute value for general cases + VALUE := SIN(XLOCAL)/COS(XLOCAL); + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TAN; + + function ARCSIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCSIN(-X) = -ARCSIN(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of arguments + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCSIN(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + elsif XLOCAL = 1.0 then + if NEGATIVE then + return -MATH_PI_OVER_2; + else + return MATH_PI_OVER_2; + end if; + end if; + + -- Compute value for general cases + if XLOCAL < 0.9 then + VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCSIN; + + function ARCCOS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of argument + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCCOS(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + elsif X = 0.0 then + return MATH_PI_OVER_2; + elsif X = -1.0 then + return MATH_PI; + end if; + + -- Compute value for general cases + if XLOCAL > 0.9 then + VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); + end if; + + + if NEGATIVE then + VALUE := MATH_PI - VALUE; + end if; + + return VALUE; + end ARCCOS; + + + function ARCTAN (Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCTAN(-Y) = -ARCTAN(Y) + -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 + -- c) ARCTAN(Y) = Y for |Y| < EPS + + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; + + variable NEGATIVE : BOOLEAN := Y < 0.0; + variable RECIPROCAL : BOOLEAN; + variable YLOCAL : REAL := ABS(Y); + variable VALUE : REAL; + + begin + -- Make argument |Y| <=1.0 + if YLOCAL > 1.0 then + YLOCAL := 1.0/YLOCAL; + RECIPROCAL := TRUE; + else + RECIPROCAL := FALSE; + end if; + + -- Compute value for special cases + if YLOCAL = 0.0 then + if RECIPROCAL then + if NEGATIVE then + return (-MATH_PI_OVER_2); + else + return (MATH_PI_OVER_2); + end if; + else + return 0.0; + end if; + end if; + + if YLOCAL < EPS then + if NEGATIVE then + if RECIPROCAL then + return (-MATH_PI_OVER_2 + YLOCAL); + else + return -YLOCAL; + end if; + else + if RECIPROCAL then + return (MATH_PI_OVER_2 - YLOCAL); + else + return YLOCAL; + end if; + end if; + end if; + + -- Compute value for general cases + VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); + + if RECIPROCAL then + VALUE := MATH_PI_OVER_2 - VALUE; + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function ARCTAN (Y : in REAL; X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable YLOCAL : REAL; + variable VALUE : REAL; + begin + + -- Check validity of arguments + if (Y = 0.0 and X = 0.0 ) then + assert FALSE report + "ARCTAN(0.0, 0.0) is undetermined" + severity ERROR; + return 0.0; + end if; + + -- Compute value for special cases + if Y = 0.0 then + if X > 0.0 then + return 0.0; + else + return MATH_PI; + end if; + end if; + + if X = 0.0 then + if Y > 0.0 then + return MATH_PI_OVER_2; + else + return -MATH_PI_OVER_2; + end if; + end if; + + + -- Compute value for general cases + YLOCAL := ABS(Y/X); + + VALUE := ARCTAN(YLOCAL); + + if X < 0.0 then + VALUE := MATH_PI - VALUE; + end if; + + if Y < 0.0 then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function SINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/2.0 + -- b) SINH(-X) = SINH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)*0.5; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end SINH; + + function COSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) + EXP(-X))/2.0 + -- b) COSH(-X) = COSH(X) + + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 1.0; + end if; + + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP + 1.0/TEMP)*0.5; + + return VALUE; + end COSH; + + function TANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) + -- b) TANH(-X) = -TANH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TANH; + + function ARCSINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X + 1.0)) + + begin + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X + 1.0)) ); + end ARCSINH; + + + + function ARCCOSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 + -- b) Returns X on error + + begin + -- Check validity of arguments + if X < 1.0 then + assert FALSE + report "X < 1.0 in ARCCOSH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X - 1.0))); + end ARCCOSH; + + function ARCTANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 + -- b) Returns X on error + begin + -- Check validity of arguments + if ABS(X) >= 1.0 then + assert FALSE + report "ABS(X) >= 1.0 in ARCTANH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); + end ARCTANH; + +end MATH_REAL; diff --git a/lattice/.floorplanner.ini b/lattice/.floorplanner.ini new file mode 100644 index 0000000..f5d7422 --- /dev/null +++ b/lattice/.floorplanner.ini @@ -0,0 +1,14 @@ +[General] +showNCD=true +showPgroups=true +showCongestion=false +showConnsSelect=false +showConnsBetween=true +showConnsOutside=true +showLPF=true +showREGIONs=true +showUGROUPs=true +showPARITIONs=true +showLogicalConnections=false +dontShowBBoxOverlapWarning=false +sceneInViewRect=@Variant(\0\0\0\x14@\x99\0\0\0\0\0\0@\xd0\x63\0\0\0\0\0@\xd4\xc3\0\0\0\0\0@\xc2\x8e\0\0\0\0\0) diff --git a/lattice/.run_manager.ini b/lattice/.run_manager.ini new file mode 100644 index 0000000..60fc10a --- /dev/null +++ b/lattice/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[fpgatop%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/lattice/.setting.ini b/lattice/.setting.ini new file mode 100644 index 0000000..a18d9b7 --- /dev/null +++ b/lattice/.setting.ini @@ -0,0 +1,4 @@ +[General] +PAR.auto_tasks=PARTrace +AutoAssign=false +Export.auto_tasks=Jedecgen diff --git a/lattice/.spread_sheet.ini b/lattice/.spread_sheet.ini new file mode 100644 index 0000000..6c511f4 --- /dev/null +++ b/lattice/.spread_sheet.ini @@ -0,0 +1,3 @@ +[General] +COLUMN_POS_INFO_NAME_-1_0=Prioritize +COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/lattice/.spreadsheet_view.ini b/lattice/.spreadsheet_view.ini new file mode 100644 index 0000000..420f148 --- /dev/null +++ b/lattice/.spreadsheet_view.ini @@ -0,0 +1,76 @@ +[General] +pin_sort_type=0 +pin_sort_ascending=true +sig_sort_type=0 +sig_sort_ascending=true +active_Sheet=Port Assignments + +[Port%20Assignments] +Name="183,0" +Group%20By="84,1" +Pin="50,2" +BANK="62,3" +IO_TYPE="80,4" +PULLMODE="92,5" +DRIVE="67,9" +SLEWRATE="92,6" +OPENDRAIN="97,10" +Outload%20%28pF%29="103,11" +MaxSkew="87,14" +Clock%20Load%20Only="121,13" +sort_columns="BANK,Ascending" +BANK_VCC="90,7" +VREF="60,8" +CLAMP="71,12" +DIFFRESISTOR="114,15" +DIFFDRIVE="92,16" +HYSTERESIS="101,17" +SwitchingID="100,18" +Ground%20plane%20PCB%20noise%20%28mV%29="196,19" +Power%20plane%20PCB%20noise%20%28mV%29="190,20" +SSO%20Allowance%28%25%29="138,21" + +[Pin%20Assignments] +Pin="90,0" +Pad%20Name="89,1" +Dual%20Function="158,2" +Polarity="77,3" +BANK="0,4" +IO_TYPE="80,5" +Signal%20Name="102,6" +Signal%20Type="98,7" +sort_columns="Pin,Ascending" +BANK_VCC="90,8" + +[Clock%20Resource] +Clock%20Type="100,ELLIPSIS" +Clock%20Name="100,ELLIPSIS" +Selection="100,ELLIPSIS" + +[Global%20Preferences] +Preference%20Name="230,ELLIPSIS" +Preference%20Value="236,ELLIPSIS" + +[Cell%20Mapping] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Din\Dout="100,ELLIPSIS" +PIO%20Register="100,ELLIPSIS" + +[Route%20Priority] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Prioritize="100,ELLIPSIS" + +[Timing%20Preferences] +Preference%20Name="129,ELLIPSIS" +Preference%20Value="104,ELLIPSIS" +Preference%20Unit="98,ELLIPSIS" + +[Group] +Group%20Type\Name="134,ELLIPSIS" +Value="38,ELLIPSIS" + +[Misc%20Preferences] +Preference%20Name="162,ELLIPSIS" +Preference%20Value="104,ELLIPSIS" diff --git a/lattice/Untitled.tpf b/lattice/Untitled.tpf new file mode 100644 index 0000000..be8782f --- /dev/null +++ b/lattice/Untitled.tpf @@ -0,0 +1,4 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +AUTOMOTIVE ; +FREQUENCY NET "fclk_c" 318.066000 MHz ; diff --git a/lattice/addrDecoder.v b/lattice/addrDecoder.v new file mode 100644 index 0000000..ba7fd02 --- /dev/null +++ b/lattice/addrDecoder.v @@ -0,0 +1,37 @@ +`timescale 1 ns / 1 ps +module addrDecoder( + input [11:0] addr, + //input _devsel, // 16 bytes (for IWM) + input fclk, + input _iostrobe, // shared 2K space + input _iosel, // card-specific 256 bytes + input _reset, + output _romoe, // 0 if the card's ROM should drive its output right now + output reg romExpansionActive // 1 if the Yellowstone card's ROM is the currently selected slot ROM + ); + + wire histrobe = ~_iostrobe & (addr == 12'hFFF); + + /*reg [1:0] histrobeHistory; + reg [1:0] ioselHistory; + + always @(posedge fclk) begin + histrobeHistory <= { histrobeHistory[0], histrobe }; + ioselHistory <= { ioselHistory[0], _iosel }; + end*/ + + //wire clearActive = histrobe || ~_reset; + //always @(posedge fclk or posedge clearActive) begin + always @(posedge fclk) begin + //if (clearActive) + //if (histrobeHistory == 2'b11) + if (histrobe) + romExpansionActive <= 0; + //else if (ioselHistory == 2'b00) + else if (~_iosel) + romExpansionActive <= 1; + end + + assign _romoe = ~(~_iosel || (romExpansionActive && ~_iostrobe)); + +endmodule diff --git a/lattice/codeROM.edn b/lattice/codeROM.edn new file mode 100644 index 0000000..8d8fe7d --- /dev/null +++ b/lattice/codeROM.edn @@ -0,0 +1,918 @@ +(edif codeROM + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2018 1 30 17 35 12) + (program "SCUBA" (version "Diamond (64-bit) 3.9.0.99.2")))) + (comment "C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n codeROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type bram -wp 00 -rp 1100 -addr_width 12 -data_width 8 -num_rows 4096 -outdata REGISTERED -cascade 11 -resetmode SYNC -sync_reset -memfile c:/users/chamberlin/documents/liron/rom-full-4k.mem -memformat hex ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction 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codeROM_0_0_2_1)) + (portRef ADA11 (instanceRef codeROM_0_0_3_0)))) + (net raddr9 + (joined + (portRef (member Address 2)) + (portRef ADA10 (instanceRef codeROM_0_0_0_3)) + (portRef ADA10 (instanceRef codeROM_0_0_1_2)) + (portRef ADA10 (instanceRef codeROM_0_0_2_1)) + (portRef ADA10 (instanceRef codeROM_0_0_3_0)))) + (net raddr8 + (joined + (portRef (member Address 3)) + (portRef ADA9 (instanceRef codeROM_0_0_0_3)) + (portRef ADA9 (instanceRef codeROM_0_0_1_2)) + (portRef ADA9 (instanceRef codeROM_0_0_2_1)) + (portRef ADA9 (instanceRef codeROM_0_0_3_0)))) + (net raddr7 + (joined + (portRef (member Address 4)) + (portRef ADA8 (instanceRef codeROM_0_0_0_3)) + (portRef ADA8 (instanceRef codeROM_0_0_1_2)) + (portRef ADA8 (instanceRef codeROM_0_0_2_1)) + (portRef ADA8 (instanceRef codeROM_0_0_3_0)))) + (net raddr6 + (joined + (portRef (member Address 5)) + (portRef ADA7 (instanceRef codeROM_0_0_0_3)) + (portRef ADA7 (instanceRef codeROM_0_0_1_2)) + (portRef ADA7 (instanceRef codeROM_0_0_2_1)) + (portRef ADA7 (instanceRef codeROM_0_0_3_0)))) + (net raddr5 + (joined + (portRef (member Address 6)) + (portRef ADA6 (instanceRef codeROM_0_0_0_3)) + (portRef ADA6 (instanceRef codeROM_0_0_1_2)) + (portRef ADA6 (instanceRef codeROM_0_0_2_1)) + (portRef ADA6 (instanceRef codeROM_0_0_3_0)))) + (net raddr4 + (joined + (portRef (member Address 7)) + (portRef ADA5 (instanceRef codeROM_0_0_0_3)) + (portRef ADA5 (instanceRef codeROM_0_0_1_2)) + (portRef ADA5 (instanceRef codeROM_0_0_2_1)) + (portRef ADA5 (instanceRef codeROM_0_0_3_0)))) + (net raddr3 + (joined + (portRef (member Address 8)) + (portRef ADA4 (instanceRef codeROM_0_0_0_3)) + (portRef ADA4 (instanceRef codeROM_0_0_1_2)) + (portRef ADA4 (instanceRef codeROM_0_0_2_1)) + (portRef ADA4 (instanceRef codeROM_0_0_3_0)))) + (net raddr2 + (joined + (portRef (member Address 9)) + (portRef ADA3 (instanceRef codeROM_0_0_0_3)) + (portRef ADA3 (instanceRef codeROM_0_0_1_2)) + (portRef ADA3 (instanceRef codeROM_0_0_2_1)) + (portRef ADA3 (instanceRef codeROM_0_0_3_0)))) + (net raddr1 + (joined + (portRef (member Address 10)) + (portRef ADA2 (instanceRef codeROM_0_0_0_3)) + (portRef ADA2 (instanceRef codeROM_0_0_1_2)) + (portRef ADA2 (instanceRef codeROM_0_0_2_1)) + (portRef ADA2 (instanceRef codeROM_0_0_3_0)))) + (net raddr0 + (joined + (portRef (member Address 11)) + (portRef ADA1 (instanceRef codeROM_0_0_0_3)) + (portRef ADA1 (instanceRef codeROM_0_0_1_2)) + (portRef ADA1 (instanceRef codeROM_0_0_2_1)) + (portRef ADA1 (instanceRef codeROM_0_0_3_0)))))))) + (design codeROM + (cellRef codeROM + (libraryRef ORCLIB))) +) diff --git a/lattice/codeROM.ipx b/lattice/codeROM.ipx new file mode 100644 index 0000000..4652254 --- /dev/null +++ b/lattice/codeROM.ipx @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/lattice/codeROM.lpc b/lattice/codeROM.lpc new file mode 100644 index 0000000..4fc510a --- /dev/null +++ b/lattice/codeROM.lpc @@ -0,0 +1,51 @@ +[Device] +Family=machxo2 +PartType=LCMXO2-1200HC +PartName=LCMXO2-1200HC-4TG100C +SpeedGrade=4 +Package=TQFP100 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=ROM +CoreRevision=5.4 +ModuleName=codeROM +SourceFormat=Verilog HDL +ParameterFileVersion=1.0 +Date=01/30/2018 +Time=17:35:12 + +[Parameters] +Verilog=1 +VHDL=0 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Address=4096 +Data=8 +enByte=0 +ByteSize=9 +OutputEn=1 +ClockEn=0 +Optimization=Area +Reset=Sync +Reset1=Sync +Init=0 +MemFile=c:/users/chamberlin/documents/liron/rom-full-4k.mem +MemFormat=hex +EnECC=0 +Pipeline=0 +Write=Normal +init_data=0 + +[FilesGenerated] +c:/users/chamberlin/documents/liron/rom-full-4k.mem=mem + +[Command] +cmd_line= -w -n codeROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-1200HC -addr_width 12 -data_width 8 -num_words 4096 -outdata REGISTERED -cascade 11 -resetmode SYNC -sync_reset -memfile "c:/users/chamberlin/documents/liron/rom-full-4k.mem" -memformat hex diff --git a/lattice/codeROM.naf b/lattice/codeROM.naf new file mode 100644 index 0000000..87c1322 --- /dev/null +++ b/lattice/codeROM.naf @@ -0,0 +1,23 @@ +Address[11] i +Address[10] i +Address[9] i +Address[8] i +Address[7] i +Address[6] i +Address[5] i +Address[4] i +Address[3] i +Address[2] i +Address[1] i +Address[0] i +OutClock i +OutClockEn i +Reset i +Q[7] o +Q[6] o +Q[5] o +Q[4] o +Q[3] o +Q[2] o +Q[1] o +Q[0] o diff --git a/lattice/codeROM.sort b/lattice/codeROM.sort new file mode 100644 index 0000000..1ef0274 --- /dev/null +++ b/lattice/codeROM.sort @@ -0,0 +1 @@ +codeROM.v diff --git a/lattice/codeROM.srp b/lattice/codeROM.srp new file mode 100644 index 0000000..5d150a1 --- /dev/null +++ b/lattice/codeROM.srp @@ -0,0 +1,29 @@ +SCUBA, Version Diamond (64-bit) 3.9.0.99.2 +Tue Jan 30 17:35:12 2018 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n codeROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-1200HC -addr_width 12 -data_width 8 -num_words 4096 -outdata REGISTERED -cascade 11 -resetmode SYNC -sync_reset -memfile c:/users/chamberlin/documents/liron/rom-full-4k.mem -memformat hex + Circuit name : codeROM + Module type : EBR_ROM + Module Version : 5.4 + Ports : + Inputs : Address[11:0], OutClock, OutClockEn, Reset + Outputs : Q[7:0] + I/O buffer : not inserted + Memory file : c:/users/chamberlin/documents/liron/rom-full-4k.mem + EDIF output : codeROM.edn + Verilog output : codeROM.v + Verilog template : codeROM_tmpl.v + Verilog testbench: tb_codeROM_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : codeROM.srp + Element Usage : + DP8KC : 4 + Estimated Resource Usage: + EBR : 4 diff --git a/lattice/codeROM.sym b/lattice/codeROM.sym new file mode 100644 index 0000000..7e79edf Binary files /dev/null and b/lattice/codeROM.sym differ diff --git a/lattice/codeROM.v b/lattice/codeROM.v new file mode 100644 index 0000000..5d92aa7 --- /dev/null +++ b/lattice/codeROM.v @@ -0,0 +1,295 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.9.0.99.2 */ +/* Module Version: 5.4 */ +/* C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n codeROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type bram -wp 00 -rp 1100 -addr_width 12 -data_width 8 -num_rows 4096 -outdata REGISTERED -cascade 11 -resetmode SYNC -sync_reset -memfile c:/users/chamberlin/documents/liron/rom-full-4k.mem -memformat hex */ +/* Tue Jan 30 17:35:12 2018 */ + + +`timescale 1 ns / 1 ps +module codeROM (Address, OutClock, OutClockEn, Reset, Q)/* synthesis NGD_DRC_MASK=1 */; + input wire [11:0] Address; + input wire OutClock; + input wire OutClockEn; + input wire Reset; + output wire [7:0] Q; + + wire scuba_vhi; + wire scuba_vlo; + + defparam codeROM_0_0_0_3.INIT_DATA = "STATIC" ; + defparam codeROM_0_0_0_3.ASYNC_RESET_RELEASE = "SYNC" ; + defparam codeROM_0_0_0_3.INITVAL_1F = "0x1E07417209022F10021108E3F1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ; + defparam codeROM_0_0_0_3.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00020F8186D01C04D" ; + defparam codeROM_0_0_0_3.INITVAL_1D = "0x15E1D120E31A04907C101C4E907A0100A220348D1501A10040108480DCA3060680522C024AA0301B" ; + defparam codeROM_0_0_0_3.INITVAL_1C = "0x0409311AAA038091CA2100C48108441187602A9309231012450840A080240AA6A19A150229D13219" ; + defparam codeROM_0_0_0_3.INITVAL_1B = "0x0B4241A461086D51BEC10008408C44000040484209A4109AE8024401440402C3400A611A8640022C" ; + defparam codeROM_0_0_0_3.INITVAL_1A = "0x1363C0121809242080101920B06C5614E8210C2118CC008C40090500061D14A51030A219A1D15C99" ; + defparam codeROM_0_0_0_3.INITVAL_19 = "0x1121113A76160120325902A5C198800864108242194C1024C00884118E011848212E2500A41108C8" ; + defparam codeROM_0_0_0_3.INITVAL_18 = "0x0265D148D0012101220706429092441089108A840A233002E2130091B0A21AA05062DC0B04204078" ; + defparam codeROM_0_0_0_3.INITVAL_17 = "0x0101809644088041123019C81006A0090BA1DC23080D20864E00A041D09D04A88030410C88D02A91" ; + defparam codeROM_0_0_0_3.INITVAL_16 = "0x00A800341502014022C008A111341208A09036221085F0108B0ECD11B0D104A4606A5510C1D12C44" ; + defparam codeROM_0_0_0_3.INITVAL_15 = "0x03C0403A5C15E241244902040000890881302005080C410022012C50C203032850A2010581918A61" ; + defparam codeROM_0_0_0_3.INITVAL_14 = "0x0A06210241094010800000000000000000000000000000000000000014A8084410481B0064D16048" ; + defparam codeROM_0_0_0_3.INITVAL_13 = "0x1101C11610002451601102E0002420002180D8050D80406856088C10804409ADC00C030C0C00C05C" ; + defparam codeROM_0_0_0_3.INITVAL_12 = "0x048590684112AD5122110A0A919ECF00204004601624010250082400A09808AC00484419C1A1B214" ; + defparam codeROM_0_0_0_3.INITVAL_11 = "0x0E86A0C851122A512245080CE082A11224408CB608A1D03499028650AC4019C4114A9402E0008251" ; + defparam codeROM_0_0_0_3.INITVAL_10 = "0x0A82706670008410E0251881400E500226110835108060C017004441BA410A800184600A67419228" ; + defparam codeROM_0_0_0_3.INITVAL_0F = "0x160300301000E0902A28102000400C000560601D02E011E6380229B0E01008C6D18041032B70026E" ; + defparam codeROM_0_0_0_3.INITVAL_0E = "0x100460DAC00821916E01008661B807140111367002AD516CA5180701864309E7B05C021C20803C22" ; + defparam codeROM_0_0_0_3.INITVAL_0D = "0x160300301000E0902A28102000400C000560601D02E01166380229B0E01008C6D18041032B70026E" ; + defparam codeROM_0_0_0_3.INITVAL_0C = "0x100460DAC00821916E01008661B807140111367002AD516CA5180601864309E6B054021420803C22" ; + defparam codeROM_0_0_0_3.INITVAL_0B = "0x160300301000E0902A28102000400C000560601D02E010E6380229B0E01008C6D18041032B70026E" ; + defparam codeROM_0_0_0_3.INITVAL_0A = "0x100460DAC00821916E01008661B807140111367002AD516CA5180501864309E5B04C020C20803C22" ; + defparam codeROM_0_0_0_3.INITVAL_09 = "0x160300301000E0902A28102000400C000560601D02E01066380229B0E01008C6D18041032B70026E" ; + defparam codeROM_0_0_0_3.INITVAL_08 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180401864309E4B044020420803C22" ; + defparam codeROM_0_0_0_3.INITVAL_07 = "0x160300301000E0902A28102000400C000560601D02E011E6380229B0E01008C6D18041032B70026E" ; + defparam codeROM_0_0_0_3.INITVAL_06 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180701864309E7B05C021C20803C22" ; + defparam codeROM_0_0_0_3.INITVAL_05 = "0x160300301000E0902A28102000400C000560601D02E01166380229B0E01008C6D18041032B70026E" ; + defparam codeROM_0_0_0_3.INITVAL_04 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180601864309E6B054021420803C22" ; + defparam codeROM_0_0_0_3.INITVAL_03 = "0x160300301000E0902A28102000400C000560601D02E010E6380229B0E01008C6D18041032B70026E" ; + defparam codeROM_0_0_0_3.INITVAL_02 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180501864309E5B04C020C20803C22" ; + defparam codeROM_0_0_0_3.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ; + defparam codeROM_0_0_0_3.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECE0FA0506A181206C0CE66" ; + defparam codeROM_0_0_0_3.CSDECODE_B = "0b111" ; + defparam codeROM_0_0_0_3.CSDECODE_A = "0b000" ; + defparam codeROM_0_0_0_3.WRITEMODE_B = "NORMAL" ; + defparam codeROM_0_0_0_3.WRITEMODE_A = "NORMAL" ; + defparam codeROM_0_0_0_3.GSR = "ENABLED" ; + defparam codeROM_0_0_0_3.RESETMODE = "SYNC" ; + defparam codeROM_0_0_0_3.REGMODE_B = "NOREG" ; + defparam codeROM_0_0_0_3.REGMODE_A = "OUTREG" ; + defparam codeROM_0_0_0_3.DATA_WIDTH_B = 2 ; + defparam codeROM_0_0_0_3.DATA_WIDTH_A = 2 ; + DP8KC codeROM_0_0_0_3 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo), + .DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo), + .DIA1(scuba_vlo), .DIA0(scuba_vlo), .ADA12(Address[11]), .ADA11(Address[10]), + .ADA10(Address[9]), .ADA9(Address[8]), .ADA8(Address[7]), .ADA7(Address[6]), + .ADA6(Address[5]), .ADA5(Address[4]), .ADA4(Address[3]), .ADA3(Address[2]), + .ADA2(Address[1]), .ADA1(Address[0]), .ADA0(scuba_vlo), .CEA(OutClockEn), + .OCEA(OutClockEn), .CLKA(OutClock), .WEA(scuba_vlo), .CSA2(scuba_vlo), + .CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(Reset), .DIB8(scuba_vlo), + .DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), + .DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo), + .ADB12(scuba_vlo), .ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo), + .ADB8(scuba_vlo), .ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo), + .ADB4(scuba_vlo), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vlo), + .ADB0(scuba_vlo), .CEB(scuba_vhi), .OCEB(scuba_vhi), .CLKB(scuba_vlo), + .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo), + .RSTB(scuba_vlo), .DOA8(), .DOA7(), .DOA6(), .DOA5(), .DOA4(), .DOA3(), + .DOA2(), .DOA1(Q[1]), .DOA0(Q[0]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), + .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0()) + /* synthesis MEM_LPC_FILE="codeROM.lpc" */ + /* synthesis MEM_INIT_FILE="rom-full-4k.mem" */; + + defparam codeROM_0_0_1_2.INIT_DATA = "STATIC" ; + defparam codeROM_0_0_1_2.ASYNC_RESET_RELEASE = "SYNC" ; + defparam codeROM_0_0_1_2.INITVAL_1F = "0x1E00C19C310A6C11801A010BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ; + defparam codeROM_0_0_1_2.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE08002F01A4241E251" ; + defparam codeROM_0_0_1_2.INITVAL_1D = "0x1F8120A8F2048700F8011E0C107C0D05E130E00E180A800CA4028B00A8AC0361803C3011CAA1308F" ; + defparam codeROM_0_0_1_2.INITVAL_1C = "0x050D2082AA128821B21B0DCA40DC6E08CB914C180CA9A1324D106790903416CA61922504A2105221" ; + defparam codeROM_0_0_1_2.INITVAL_1B = "0x0CA960306A09000000080546A0D46A1188600CA601C4A1144C040461C46A0E8390125B0ACD503698" ; + defparam codeROM_0_0_1_2.INITVAL_1A = "0x03E2C09615082A00E2A918C49048B70AA50012031EA090A8A9052020243302A550A8921922112295" ; + defparam codeROM_0_0_1_2.INITVAL_19 = "0x0029213CCC082B90A45D05AA802CE610690140A210A861FECA120A40DC24092910902C196C210889" ; + defparam codeROM_0_0_1_2.INITVAL_18 = "0x0D6B303018104481280F1840412A521241400A690B4FC0341A04042054AA03E09034E40CCA605062" ; + defparam codeROM_0_0_1_2.INITVAL_17 = "0x15426150A61406A15CC01320D16C430D0A60120A088E31C6E919E2C0A0561286010C031244504A55" ; + defparam codeROM_0_0_1_2.INITVAL_16 = "0x16C6814C490565602889024350A80102424094D30945B1C04A0CCFD0C06D14E491347506CF915A56" ; + defparam codeROM_0_0_1_2.INITVAL_15 = "0x04A4004A501BE01000900089018CE6194030406914886182B919A6F0B68117A6F0B69B130AD0DE5B" ; + defparam codeROM_0_0_1_2.INITVAL_14 = "0x1E0A2106C2094011000000000000000000000000000000000000000014AA082C70183B002C3160CA" ; + defparam codeROM_0_0_1_2.INITVAL_13 = "0x010AC11628002C31601107C0F040F30C8200303C0D03C028950AC4D19044114E807A10164831E038" ; + defparam codeROM_0_0_1_2.INITVAL_12 = "0x078F9008A9024550AA12178AA11E3C01E0E006D2160A2106E011EA2150A809E831D06F012860283C" ; + defparam codeROM_0_0_1_2.INITVAL_11 = "0x10C180A0F203061086C80D4F509061086C80C2B501E2D10CD4078B4088AA06A480DA4907C0F124D3" ; + defparam codeROM_0_0_1_2.INITVAL_10 = "0x1882818473092231C0F9188DA0146805A92094260940A0843E01E881FC401D6A2086C0164E80922C" ; + defparam codeROM_0_0_1_2.INITVAL_0F = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95" ; + defparam codeROM_0_0_1_2.INITVAL_0E = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000" ; + defparam codeROM_0_0_1_2.INITVAL_0D = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95" ; + defparam codeROM_0_0_1_2.INITVAL_0C = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000" ; + defparam codeROM_0_0_1_2.INITVAL_0B = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95" ; + defparam codeROM_0_0_1_2.INITVAL_0A = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000" ; + defparam codeROM_0_0_1_2.INITVAL_09 = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95" ; + defparam codeROM_0_0_1_2.INITVAL_08 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000" ; + defparam codeROM_0_0_1_2.INITVAL_07 = "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95" ; + defparam codeROM_0_0_1_2.INITVAL_06 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000" ; + defparam codeROM_0_0_1_2.INITVAL_05 = "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95" ; + defparam codeROM_0_0_1_2.INITVAL_04 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000" ; + defparam codeROM_0_0_1_2.INITVAL_03 = "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95" ; + defparam codeROM_0_0_1_2.INITVAL_02 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000" ; + defparam codeROM_0_0_1_2.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ; + defparam codeROM_0_0_1_2.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEC314034116201AA84082C9" ; + defparam codeROM_0_0_1_2.CSDECODE_B = "0b111" ; + defparam codeROM_0_0_1_2.CSDECODE_A = "0b000" ; + defparam codeROM_0_0_1_2.WRITEMODE_B = "NORMAL" ; + defparam codeROM_0_0_1_2.WRITEMODE_A = "NORMAL" ; + defparam codeROM_0_0_1_2.GSR = "ENABLED" ; + defparam codeROM_0_0_1_2.RESETMODE = "SYNC" ; + defparam codeROM_0_0_1_2.REGMODE_B = "NOREG" ; + defparam codeROM_0_0_1_2.REGMODE_A = "OUTREG" ; + defparam codeROM_0_0_1_2.DATA_WIDTH_B = 2 ; + defparam codeROM_0_0_1_2.DATA_WIDTH_A = 2 ; + DP8KC codeROM_0_0_1_2 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo), + .DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo), + .DIA1(scuba_vlo), .DIA0(scuba_vlo), .ADA12(Address[11]), .ADA11(Address[10]), + .ADA10(Address[9]), .ADA9(Address[8]), .ADA8(Address[7]), .ADA7(Address[6]), + .ADA6(Address[5]), .ADA5(Address[4]), .ADA4(Address[3]), .ADA3(Address[2]), + .ADA2(Address[1]), .ADA1(Address[0]), .ADA0(scuba_vlo), .CEA(OutClockEn), + .OCEA(OutClockEn), .CLKA(OutClock), .WEA(scuba_vlo), .CSA2(scuba_vlo), + .CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(Reset), .DIB8(scuba_vlo), + .DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), + .DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo), + .ADB12(scuba_vlo), .ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo), + .ADB8(scuba_vlo), .ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo), + .ADB4(scuba_vlo), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vlo), + .ADB0(scuba_vlo), .CEB(scuba_vhi), .OCEB(scuba_vhi), .CLKB(scuba_vlo), + .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo), + .RSTB(scuba_vlo), .DOA8(), .DOA7(), .DOA6(), .DOA5(), .DOA4(), .DOA3(), + .DOA2(), .DOA1(Q[3]), .DOA0(Q[2]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), + .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0()) + /* synthesis MEM_LPC_FILE="codeROM.lpc" */ + /* synthesis MEM_INIT_FILE="rom-full-4k.mem" */; + + defparam codeROM_0_0_2_1.INIT_DATA = "STATIC" ; + defparam codeROM_0_0_2_1.ASYNC_RESET_RELEASE = "SYNC" ; + defparam codeROM_0_0_2_1.INITVAL_1F = "0x1E812150AE1FC8A178BF1D0BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ; + defparam codeROM_0_0_2_1.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00082020304200010" ; + defparam codeROM_0_0_2_1.INITVAL_1D = "0x0008008400084000808900214110830DC8C0FC180C282026D8140BA10CF009C21058B6004000C608" ; + defparam codeROM_0_0_2_1.INITVAL_1C = "0x0809C140000DA010388D06C9206A35146701B4080408D0CCB2050C40208010098048240482004820" ; + defparam codeROM_0_0_2_1.INITVAL_1B = "0x04008040A8140000002C1CC3C07C3E1AC860465807038070A3004531BC35110680B08D0464909E65" ; + defparam codeROM_0_0_2_1.INITVAL_1A = "0x0408E1669101084108F61A41212080010841104800C5903091192C90964B04824046380482008460" ; + defparam codeROM_0_0_2_1.INITVAL_19 = "0x0240209C2C128F60844004029046DA12A9512C8C06410000201088107E4104C0415440010A202454" ; + defparam codeROM_0_0_2_1.INITVAL_18 = "0x0568B04A2D0027208E21008881221C138070483D01E0009E0A00600054A20448819AC1106D3080DB" ; + defparam codeROM_0_0_2_1.INITVAL_17 = "0x000230D0930CE3E02206040321808413A080402815A600A0530060E0C2420B0BD012300BE2404C46" ; + defparam codeROM_0_0_2_1.INITVAL_16 = "0x092BD030740409200AD10A8C9130C90AE450A4DC1106103230010700420209654112081007003A19" ; + defparam codeROM_0_0_2_1.INITVAL_15 = "0x04C320486705E000020000022126581C68809434134530C8D60203801C081843011A4D0C4E00700E" ; + defparam codeROM_0_0_2_1.INITVAL_14 = "0x050B4050A202088100000000000000000000000000000000000000005001140C301831140C3034D0" ; + defparam codeROM_0_0_2_1.INITVAL_13 = "0x15A0E0408E0C0C30140000E43042A400A0301A0C01A0C12099032B212000002ED018B4018D01B03D" ; + defparam codeROM_0_0_2_1.INITVAL_12 = "0x01830120960944608C02064A80D8FC1060D1E0CF03084040741061810C80102D01C08C0600808E04" ; + defparam codeROM_0_0_2_1.INITVAL_11 = "0x03021038100C0840E04114046020840E04110401182020100700808000A010C101007600E4308020" ; + defparam codeROM_0_0_2_1.INITVAL_10 = "0x090A1008A4002C00E8161CE2110086004180C2980C281168070821C03C20180F4060F8060CA0408A" ; + defparam codeROM_0_0_2_1.INITVAL_0F = "0x0603B0C2A9076CE0726D00A2304A0D0701A1E8E01264E040C0000510E8E0002411A68000A3709C66" ; + defparam codeROM_0_0_2_1.INITVAL_0E = "0x0200108AD31000500E4E000141BA39108000A4741C826110041A68C02088106881844F048F30042A" ; + defparam codeROM_0_0_2_1.INITVAL_0D = "0x0603B0C2A9056CA0526D00A2304A0D0501A1E8A01264A040C0000510E8A0002411A48000A3709466" ; + defparam codeROM_0_0_2_1.INITVAL_0C = "0x0200108AD21000500E4A000141BA29108000A47414826110041A48C02088106881844F048F30042A" ; + defparam codeROM_0_0_2_1.INITVAL_0B = "0x0603B0C2A9036C60326D00A2304A0D0301A1E86012646040C0000510E860002411A28000A3708C66" ; + defparam codeROM_0_0_2_1.INITVAL_0A = "0x0200108AD11000500E46000141BA19108000A4740C826110041A28C02088106881844F048F30042A" ; + defparam codeROM_0_0_2_1.INITVAL_09 = "0x0603B0C2A9016C20126D00A2304A0D0101A1E82012642040C0000510E820002411A08000A3708466" ; + defparam codeROM_0_0_2_1.INITVAL_08 = "0x0200108AD01000500E42000141BA09108000A47404826110041A08C02088106881844F048F30042A" ; + defparam codeROM_0_0_2_1.INITVAL_07 = "0x0603B0C2A9076CE0726D00A2304A0D0701A1E8E01264E040C0000510E8E0002411A68000A3709C66" ; + defparam codeROM_0_0_2_1.INITVAL_06 = "0x0200108AD31000500E4E000141BA39108000A4741C826110041A68C02088106881844F048F30042A" ; + defparam codeROM_0_0_2_1.INITVAL_05 = "0x0603B0C2A9056CA0526D00A2304A0D0501A1E8A01264A040C0000510E8A0002411A48000A3709466" ; + defparam codeROM_0_0_2_1.INITVAL_04 = "0x0200108AD21000500E4A000141BA29108000A47414826110041A48C02088106881844F048F30042A" ; + defparam codeROM_0_0_2_1.INITVAL_03 = "0x0603B0C2A9036C60326D00A2304A0D0301A1E86012646040C0000510E860002411A28000A3708C66" ; + defparam codeROM_0_0_2_1.INITVAL_02 = "0x0200108AD11000500E46000141BA19108000A4740C826110041A28C02088106881844F048F30042A" ; + defparam codeROM_0_0_2_1.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ; + defparam codeROM_0_0_2_1.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECE158AA150BA15EBE176B8" ; + defparam codeROM_0_0_2_1.CSDECODE_B = "0b111" ; + defparam codeROM_0_0_2_1.CSDECODE_A = "0b000" ; + defparam codeROM_0_0_2_1.WRITEMODE_B = "NORMAL" ; + defparam codeROM_0_0_2_1.WRITEMODE_A = "NORMAL" ; + defparam codeROM_0_0_2_1.GSR = "ENABLED" ; + defparam codeROM_0_0_2_1.RESETMODE = "SYNC" ; + defparam codeROM_0_0_2_1.REGMODE_B = "NOREG" ; + defparam codeROM_0_0_2_1.REGMODE_A = "OUTREG" ; + defparam codeROM_0_0_2_1.DATA_WIDTH_B = 2 ; + defparam codeROM_0_0_2_1.DATA_WIDTH_A = 2 ; + DP8KC codeROM_0_0_2_1 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo), + .DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo), + .DIA1(scuba_vlo), .DIA0(scuba_vlo), .ADA12(Address[11]), .ADA11(Address[10]), + .ADA10(Address[9]), .ADA9(Address[8]), .ADA8(Address[7]), .ADA7(Address[6]), + .ADA6(Address[5]), .ADA5(Address[4]), .ADA4(Address[3]), .ADA3(Address[2]), + .ADA2(Address[1]), .ADA1(Address[0]), .ADA0(scuba_vlo), .CEA(OutClockEn), + .OCEA(OutClockEn), .CLKA(OutClock), .WEA(scuba_vlo), .CSA2(scuba_vlo), + .CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(Reset), .DIB8(scuba_vlo), + .DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), + .DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo), + .ADB12(scuba_vlo), .ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo), + .ADB8(scuba_vlo), .ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo), + .ADB4(scuba_vlo), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vlo), + .ADB0(scuba_vlo), .CEB(scuba_vhi), .OCEB(scuba_vhi), .CLKB(scuba_vlo), + .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo), + .RSTB(scuba_vlo), .DOA8(), .DOA7(), .DOA6(), .DOA5(), .DOA4(), .DOA3(), + .DOA2(), .DOA1(Q[5]), .DOA0(Q[4]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), + .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0()) + /* synthesis MEM_LPC_FILE="codeROM.lpc" */ + /* synthesis MEM_INIT_FILE="rom-full-4k.mem" */; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam codeROM_0_0_3_0.INIT_DATA = "STATIC" ; + defparam codeROM_0_0_3_0.ASYNC_RESET_RELEASE = "SYNC" ; + defparam codeROM_0_0_3_0.INITVAL_1F = "0x1E0FE17EAF1FEFB1FEAA156BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ; + defparam codeROM_0_0_3_0.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00086FE1F6FE1E6FF" ; + defparam codeROM_0_0_3_0.INITVAL_1D = "0x1FEBF1FCF31FCFF1FEBB1E6FF176C71FE0F1C4330463206698110B0044E419E2305C3800C000C608" ; + defparam codeROM_0_0_3_0.INITVAL_1C = "0x1E08B18C000D8861908E0349903439122B41D46512C4E0CCF61A617058181309F00CA604C6604C26" ; + defparam codeROM_0_0_3_0.INITVAL_1B = "0x04C590CAA718C00110101A419034381C6D90429A06633066220E40111C39130C8182860C69800C63" ; + defparam codeROM_0_0_3_0.INITVAL_1A = "0x0DA381DC191128D100660642D034991328C110CF0AE2512885152881983E0CC660CCD300CA60CC66" ; + defparam codeROM_0_0_3_0.INITVAL_19 = "0x06C620C8F9100660CC6604C2E0E698158AC1588F06C331CE48130B6076E604CBD110EF096C2066F7" ; + defparam codeROM_0_0_3_0.INITVAL_18 = "0x0523E0CE6F10C620CC2E090D81329B1366604C1911CF400C6E02431000000DE0818AD31669B06A89" ; + defparam codeROM_0_0_3_0.INITVAL_17 = "0x03211130431201A17A490CE27032C909ED004C2913E0E0DCAE0F4E90E4610324C128011302602C65" ; + defparam codeROM_0_0_3_0.INITVAL_16 = "0x0324C12866052990CAF90A8D91B8CD0AEE50BE8D1126C0DE0D12EE60643507C2410298136E61F294" ; + defparam codeROM_0_0_3_0.INITVAL_15 = "0x04E3314C630DA0000000000411E6DB01E0816838132C11F8F604C1911CC00CC3910C8E0C4A60328E" ; + defparam codeROM_0_0_3_0.INITVAL_14 = "0x1E4BB10ECA05C08110881108810482104821002A1002A10000054AA1300113CBA1D6AC03CBA182FF" ; + defparam codeROM_0_0_3_0.INITVAL_13 = "0x13EBC0583C0DCBA182651D63A142791EC92098E9118E813059128361929608C4C1D0BF1E4CE116AC" ; + defparam codeROM_0_0_3_0.INITVAL_12 = "0x1D6AC036460C4660CC6218AFF086FF0F4E819C881808E05CBD074F317885174CE142B506ED00CCEA" ; + defparam codeROM_0_0_3_0.INITVAL_11 = "0x03641136A80DA060DCA112ED707A060DCA116819174861A0661D4191209712E3D00C661D63A0D06E" ; + defparam codeROM_0_0_3_0.INITVAL_10 = "0x130BC09AB91C2BE176861C66F042BC10CF319E1B19E21164EB170DB15C2E16A3E01C8B15CB80583C" ; + defparam codeROM_0_0_3_0.INITVAL_0F = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67" ; + defparam codeROM_0_0_3_0.INITVAL_0E = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422" ; + defparam codeROM_0_0_3_0.INITVAL_0D = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67" ; + defparam codeROM_0_0_3_0.INITVAL_0C = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422" ; + defparam codeROM_0_0_3_0.INITVAL_0B = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67" ; + defparam codeROM_0_0_3_0.INITVAL_0A = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422" ; + defparam codeROM_0_0_3_0.INITVAL_09 = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67" ; + defparam codeROM_0_0_3_0.INITVAL_08 = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422" ; + defparam codeROM_0_0_3_0.INITVAL_07 = "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467" ; + defparam codeROM_0_0_3_0.INITVAL_06 = "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422" ; + defparam codeROM_0_0_3_0.INITVAL_05 = "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467" ; + defparam codeROM_0_0_3_0.INITVAL_04 = "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422" ; + defparam codeROM_0_0_3_0.INITVAL_03 = "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467" ; + defparam codeROM_0_0_3_0.INITVAL_02 = "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422" ; + defparam codeROM_0_0_3_0.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ; + defparam codeROM_0_0_3_0.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECF1FEBF1FEBE1FEFE1FEFF" ; + defparam codeROM_0_0_3_0.CSDECODE_B = "0b111" ; + defparam codeROM_0_0_3_0.CSDECODE_A = "0b000" ; + defparam codeROM_0_0_3_0.WRITEMODE_B = "NORMAL" ; + defparam codeROM_0_0_3_0.WRITEMODE_A = "NORMAL" ; + defparam codeROM_0_0_3_0.GSR = "ENABLED" ; + defparam codeROM_0_0_3_0.RESETMODE = "SYNC" ; + defparam codeROM_0_0_3_0.REGMODE_B = "NOREG" ; + defparam codeROM_0_0_3_0.REGMODE_A = "OUTREG" ; + defparam codeROM_0_0_3_0.DATA_WIDTH_B = 2 ; + defparam codeROM_0_0_3_0.DATA_WIDTH_A = 2 ; + DP8KC codeROM_0_0_3_0 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo), + .DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo), + .DIA1(scuba_vlo), .DIA0(scuba_vlo), .ADA12(Address[11]), .ADA11(Address[10]), + .ADA10(Address[9]), .ADA9(Address[8]), .ADA8(Address[7]), .ADA7(Address[6]), + .ADA6(Address[5]), .ADA5(Address[4]), .ADA4(Address[3]), .ADA3(Address[2]), + .ADA2(Address[1]), .ADA1(Address[0]), .ADA0(scuba_vlo), .CEA(OutClockEn), + .OCEA(OutClockEn), .CLKA(OutClock), .WEA(scuba_vlo), .CSA2(scuba_vlo), + .CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(Reset), .DIB8(scuba_vlo), + .DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), + .DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo), + .ADB12(scuba_vlo), .ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo), + .ADB8(scuba_vlo), .ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo), + .ADB4(scuba_vlo), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vlo), + .ADB0(scuba_vlo), .CEB(scuba_vhi), .OCEB(scuba_vhi), .CLKB(scuba_vlo), + .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo), + .RSTB(scuba_vlo), .DOA8(), .DOA7(), .DOA6(), .DOA5(), .DOA4(), .DOA3(), + .DOA2(), .DOA1(Q[7]), .DOA0(Q[6]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), + .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0()) + /* synthesis MEM_LPC_FILE="codeROM.lpc" */ + /* synthesis MEM_INIT_FILE="rom-full-4k.mem" */; + + + + // exemplar begin + // exemplar attribute codeROM_0_0_0_3 MEM_LPC_FILE codeROM.lpc + // exemplar attribute codeROM_0_0_0_3 MEM_INIT_FILE rom-full-4k.mem + // exemplar attribute codeROM_0_0_1_2 MEM_LPC_FILE codeROM.lpc + // exemplar attribute codeROM_0_0_1_2 MEM_INIT_FILE rom-full-4k.mem + // exemplar attribute codeROM_0_0_2_1 MEM_LPC_FILE codeROM.lpc + // exemplar attribute codeROM_0_0_2_1 MEM_INIT_FILE rom-full-4k.mem + // exemplar attribute codeROM_0_0_3_0 MEM_LPC_FILE codeROM.lpc + // exemplar attribute codeROM_0_0_3_0 MEM_INIT_FILE rom-full-4k.mem + // exemplar end + +endmodule diff --git a/lattice/codeROM_tmpl.v b/lattice/codeROM_tmpl.v new file mode 100644 index 0000000..f469e39 --- /dev/null +++ b/lattice/codeROM_tmpl.v @@ -0,0 +1,6 @@ +/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.0.99.2 */ +/* Module Version: 5.4 */ +/* Tue Jan 30 17:35:12 2018 */ + +/* parameterized module instance */ +codeROM __ (.Address( ), .OutClock( ), .OutClockEn( ), .Reset( ), .Q( )); diff --git a/lattice/fpgatop/.build_status b/lattice/fpgatop/.build_status new file mode 100644 index 0000000..be14e85 --- /dev/null +++ b/lattice/fpgatop/.build_status @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lattice/fpgatop/.vdbs/dbStat.txt b/lattice/fpgatop/.vdbs/dbStat.txt new file mode 100644 index 0000000..e8652b9 --- /dev/null +++ b/lattice/fpgatop/.vdbs/dbStat.txt @@ -0,0 +1 @@ +top_rtl.vdb diff --git a/lattice/fpgatop/.vdbs/liron_fpgatop_map.vdb b/lattice/fpgatop/.vdbs/liron_fpgatop_map.vdb new file mode 100644 index 0000000..bb30432 Binary files /dev/null and b/lattice/fpgatop/.vdbs/liron_fpgatop_map.vdb differ diff --git a/lattice/fpgatop/.vdbs/top_rtl.vdb b/lattice/fpgatop/.vdbs/top_rtl.vdb new file mode 100644 index 0000000..da0d219 Binary files /dev/null and b/lattice/fpgatop/.vdbs/top_rtl.vdb differ diff --git a/lattice/fpgatop/.vdbs/top_tech.vdb b/lattice/fpgatop/.vdbs/top_tech.vdb new file mode 100644 index 0000000..8aed5b5 Binary files /dev/null and b/lattice/fpgatop/.vdbs/top_tech.vdb differ diff --git a/lattice/fpgatop/Untitled.tpf.prf b/lattice/fpgatop/Untitled.tpf.prf new file mode 100644 index 0000000..9df1d70 --- /dev/null +++ b/lattice/fpgatop/Untitled.tpf.prf @@ -0,0 +1,5 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +AUTOMOTIVE ; +FREQUENCY NET "fclk_c" 318.066000 MHz ; +COMMERCIAL ; \ No newline at end of file diff --git a/lattice/fpgatop/Untitled.tpf.prf_cdmp b/lattice/fpgatop/Untitled.tpf.prf_cdmp new file mode 100644 index 0000000..1e87179 --- /dev/null +++ b/lattice/fpgatop/Untitled.tpf.prf_cdmp @@ -0,0 +1,34 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF PORT "data[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "wrdata" IO_TYPE=LVCMOS25 ; +IOBUF PORT "phase[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "phase[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "phase[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "phase[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_wrreq" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_enbl1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_enbl2" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_romoe" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_enbuf" IO_TYPE=LVCMOS25 ; +IOBUF PORT "addr[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "addr[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "addr[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "addr[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_xFFx" IO_TYPE=LVCMOS25 ; +IOBUF PORT "fclk" IO_TYPE=LVCMOS25 ; +IOBUF PORT "q3" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_iostrobe" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_iosel" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_devsel" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_reset" IO_TYPE=LVCMOS25 ; +IOBUF PORT "sense" IO_TYPE=LVCMOS25 ; +IOBUF PORT "rddata" IO_TYPE=LVCMOS25 ; +FREQUENCY NET "fclk_c" 318.066016 MHz ; diff --git a/lattice/fpgatop/Untitled.tpf.prf_cdmp0 b/lattice/fpgatop/Untitled.tpf.prf_cdmp0 new file mode 100644 index 0000000..be8782f --- /dev/null +++ b/lattice/fpgatop/Untitled.tpf.prf_cdmp0 @@ -0,0 +1,4 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +AUTOMOTIVE ; +FREQUENCY NET "fclk_c" 318.066000 MHz ; diff --git a/lattice/fpgatop/Untitled.tpf.prf_cdmp2 b/lattice/fpgatop/Untitled.tpf.prf_cdmp2 new file mode 100644 index 0000000..1e87179 --- /dev/null +++ b/lattice/fpgatop/Untitled.tpf.prf_cdmp2 @@ -0,0 +1,34 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF PORT "data[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "data[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "wrdata" IO_TYPE=LVCMOS25 ; +IOBUF PORT "phase[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "phase[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "phase[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "phase[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_wrreq" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_enbl1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_enbl2" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_romoe" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_enbuf" IO_TYPE=LVCMOS25 ; +IOBUF PORT "addr[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "addr[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "addr[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "addr[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_xFFx" IO_TYPE=LVCMOS25 ; +IOBUF PORT "fclk" IO_TYPE=LVCMOS25 ; +IOBUF PORT "q3" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_iostrobe" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_iosel" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_devsel" IO_TYPE=LVCMOS25 ; +IOBUF PORT "_reset" IO_TYPE=LVCMOS25 ; +IOBUF PORT "sense" IO_TYPE=LVCMOS25 ; +IOBUF PORT "rddata" IO_TYPE=LVCMOS25 ; +FREQUENCY NET "fclk_c" 318.066016 MHz ; diff --git a/lattice/fpgatop/Untitled.tpf_hold.html b/lattice/fpgatop/Untitled.tpf_hold.html new file mode 100644 index 0000000..b67ef52 --- /dev/null +++ b/lattice/fpgatop/Untitled.tpf_hold.html @@ -0,0 +1,535 @@ + + + + + + + +


+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.9.0.99.2
+Wed Jul 26 13:46:07 2017
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     top
+Device,speed:    LAMXO256C,M
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "fclk_c" 318.066000 MHz ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 0.281ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_154__i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_154__i0  (to fclk_c +)
+
+   Delay:               0.264ns  (47.7% logic, 52.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.264ns physical path delay myIwm/SLICE_33 to myIwm/SLICE_33 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.281ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_33 to myIwm/SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R7C5B.CLK to       R7C5B.Q0 myIwm/SLICE_33 (from fclk_c)
+ROUTE         4     0.138       R7C5B.Q0 to R7C5B.M0       myIwm/bitCounter_0 (to fclk_c)
+                  --------
+                    0.264   (47.7% logic, 52.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C5B.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C5B.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.281ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/rddataSync_i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/rddataSync_i1  (to fclk_c +)
+
+   Delay:               0.264ns  (47.7% logic, 52.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.264ns physical path delay myIwm/SLICE_38 to myIwm/SLICE_38 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.281ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_38 to myIwm/SLICE_38:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C3D.CLK to       R5C3D.Q0 myIwm/SLICE_38 (from fclk_c)
+ROUTE         7     0.138       R5C3D.Q0 to R5C3D.M1       myIwm/rddataSync_0 (to fclk_c)
+                  --------
+                    0.264   (47.7% logic, 52.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_38:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R5C3D.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_38:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R5C3D.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_154__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_154__i2  (to fclk_c +)
+
+   Delay:               0.331ns  (60.4% logic, 39.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.331ns physical path delay myIwm/SLICE_3 to myIwm/SLICE_3 meets
+     -0.008ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.008ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_3 to myIwm/SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R7C5A.CLK to       R7C5A.Q1 myIwm/SLICE_3 (from fclk_c)
+ROUTE         2     0.131       R7C5A.Q1 to R7C5A.A1       myIwm/bitCounter_2
+CTOF_DEL    ---     0.074       R7C5A.A1 to       R7C5A.F1 myIwm/SLICE_3
+ROUTE         1     0.000       R7C5A.F1 to R7C5A.DI1      myIwm/n18 (to fclk_c)
+                  --------
+                    0.331   (60.4% logic, 39.6% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C5A.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C5A.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_154__i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_154__i1  (to fclk_c +)
+
+   Delay:               0.331ns  (60.4% logic, 39.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.331ns physical path delay myIwm/SLICE_3 to myIwm/SLICE_3 meets
+     -0.008ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.008ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_3 to myIwm/SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R7C5A.CLK to       R7C5A.Q0 myIwm/SLICE_3 (from fclk_c)
+ROUTE         3     0.131       R7C5A.Q0 to R7C5A.A0       myIwm/bitCounter_1
+CTOF_DEL    ---     0.074       R7C5A.A0 to       R7C5A.F0 myIwm/SLICE_3
+ROUTE         1     0.000       R7C5A.F0 to R7C5A.DI0      myIwm/n19 (to fclk_c)
+                  --------
+                    0.331   (60.4% logic, 39.6% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C5A.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C5A.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.340ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_154__i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_154__i2  (to fclk_c +)
+
+   Delay:               0.332ns  (60.2% logic, 39.8% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay myIwm/SLICE_3 to myIwm/SLICE_3 meets
+     -0.008ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.008ns) by 0.340ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_3 to myIwm/SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R7C5A.CLK to       R7C5A.Q0 myIwm/SLICE_3 (from fclk_c)
+ROUTE         3     0.132       R7C5A.Q0 to R7C5A.D1       myIwm/bitCounter_1
+CTOF_DEL    ---     0.074       R7C5A.D1 to       R7C5A.F1 myIwm/SLICE_3
+ROUTE         1     0.000       R7C5A.F1 to R7C5A.DI1      myIwm/n18 (to fclk_c)
+                  --------
+                    0.332   (60.2% logic, 39.8% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C5A.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C5A.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.342ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i3  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitTimer__i4  (to fclk_c +)
+
+   Delay:               0.334ns  (59.9% logic, 40.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.334ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_6 meets
+     -0.008ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.008ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_5 to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R7C4A.CLK to       R7C4A.Q1 myIwm/SLICE_5 (from fclk_c)
+ROUTE         9     0.134       R7C4A.Q1 to R7C4D.D0       myIwm/bitTimer_3
+CTOF_DEL    ---     0.074       R7C4D.D0 to       R7C4D.F0 myIwm/SLICE_6
+ROUTE         1     0.000       R7C4D.F0 to R7C4D.DI0      myIwm/n183 (to fclk_c)
+                  --------
+                    0.334   (59.9% logic, 40.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C4A.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C4D.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.342ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i3  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i3  (to fclk_c +)
+
+   Delay:               0.334ns  (59.9% logic, 40.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.334ns physical path delay myIwm/SLICE_13 to myIwm/SLICE_13 meets
+     -0.008ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.008ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_13 to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C2D.CLK to       R5C2D.Q0 myIwm/SLICE_13 (from fclk_c)
+ROUTE         4     0.134       R5C2D.Q0 to R5C2D.A0       myIwm/clearBufferTimer_3
+CTOF_DEL    ---     0.074       R5C2D.A0 to       R5C2D.F0 myIwm/SLICE_13
+ROUTE         1     0.000       R5C2D.F0 to R5C2D.DI0      myIwm/n105 (to fclk_c)
+                  --------
+                    0.334   (59.9% logic, 40.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R5C2D.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R5C2D.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.342ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i2  (to fclk_c +)
+
+   Delay:               0.334ns  (59.9% logic, 40.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.334ns physical path delay myIwm/SLICE_12 to myIwm/SLICE_12 meets
+     -0.008ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.008ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_12 to myIwm/SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C2A.CLK to       R5C2A.Q1 myIwm/SLICE_12 (from fclk_c)
+ROUTE         5     0.134       R5C2A.Q1 to R5C2A.A1       myIwm/clearBufferTimer_2
+CTOF_DEL    ---     0.074       R5C2A.A1 to       R5C2A.F1 myIwm/SLICE_12
+ROUTE         1     0.000       R5C2A.F1 to R5C2A.DI1      myIwm/n106 (to fclk_c)
+                  --------
+                    0.334   (59.9% logic, 40.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R5C2A.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R5C2A.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.342ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i5  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitTimer__i5  (to fclk_c +)
+
+   Delay:               0.334ns  (59.9% logic, 40.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.334ns physical path delay myIwm/SLICE_6 to myIwm/SLICE_6 meets
+     -0.008ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.008ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_6 to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R7C4D.CLK to       R7C4D.Q1 myIwm/SLICE_6 (from fclk_c)
+ROUTE         5     0.134       R7C4D.Q1 to R7C4D.D1       myIwm/bitTimer_5
+CTOF_DEL    ---     0.074       R7C4D.D1 to       R7C4D.F1 myIwm/SLICE_6
+ROUTE         1     0.000       R7C4D.F1 to R7C4D.DI1      myIwm/n184 (to fclk_c)
+                  --------
+                    0.334   (59.9% logic, 40.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C4D.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R7C4D.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.342ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitTimer__i1  (to fclk_c +)
+
+   Delay:               0.334ns  (59.9% logic, 40.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.334ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_4 meets
+     -0.008ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.008ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_4 to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R6C4D.CLK to       R6C4D.Q1 myIwm/SLICE_4 (from fclk_c)
+ROUTE         8     0.134       R6C4D.Q1 to R6C4D.A1       myIwm/bitTimer_1
+CTOF_DEL    ---     0.074       R6C4D.A1 to       R6C4D.F1 myIwm/SLICE_4
+ROUTE         1     0.000       R6C4D.F1 to R6C4D.DI1      myIwm/n180 (to fclk_c)
+                  --------
+                    0.334   (59.9% logic, 40.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R6C4D.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     0.333       36.PADDI to R6C4D.CLK      fclk_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "fclk_c" 318.066000 MHz ; |     0.000 ns|     0.281 ns|   1  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 3 clocks:
+
+Clock Domain: fclk_c   Source: fclk.PAD   Loads: 24
+   Covered under: FREQUENCY NET "fclk_c" 318.066000 MHz ;
+
+   Data transfers from:
+   Clock Domain: _devsel_c   Source: _devsel.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: _devsel_c   Source: _devsel.PAD   Loads: 11
+   No transfer within this clock domain is found
+
+Clock Domain: _iosel_c   Source: _iosel.PAD   Loads: 2
+   No transfer within this clock domain is found
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 841 paths, 1 nets, and 319 connections (64.84% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 10 (setup), 0 (hold)
+Score: 59154 (setup), 0 (hold)
+Cumulative negative slack: 59154 (59154+0)
diff --git a/lattice/fpgatop/Untitled.tpf_setup.html b/lattice/fpgatop/Untitled.tpf_setup.html
new file mode 100644
index 0000000..de942e3
--- /dev/null
+++ b/lattice/fpgatop/Untitled.tpf_setup.html
@@ -0,0 +1,662 @@
+
+
+
+
+
+
+
+

+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.9.0.99.2
+Wed Jul 26 13:46:07 2017
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     top
+Device,speed:    LAMXO256C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "fclk_c" 318.066000 MHz ;
+            10 items scored, 10 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Error: The following path exceeds requirements by 6.415ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i7  (to fclk_c +)
+
+   Delay:               9.378ns  (32.3% logic, 67.7% route), 7 logic levels.
+
+ Constraint Details:
+
+      9.378ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_26 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 2.963ns) by 6.415ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_5 to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 myIwm/SLICE_5 (from fclk_c)
+ROUTE         7     1.209       R7C4A.Q0 to R6C3D.D0       myIwm/bitTimer_2
+CTOF_DEL    ---     0.371       R6C3D.D0 to       R6C3D.F0 myIwm/SLICE_51
+ROUTE         2     0.901       R6C3D.F0 to R6C4C.C0       myIwm/n6
+CTOF_DEL    ---     0.371       R6C4C.C0 to       R6C4C.F0 myIwm/SLICE_36
+ROUTE         5     1.138       R6C4C.F0 to R5C4D.B1       myIwm/n133
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 myIwm/SLICE_35
+ROUTE         1     0.497       R5C4D.F1 to R5C4D.C0       myIwm/n1516
+CTOF_DEL    ---     0.371       R5C4D.C0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.657       R5C4D.F0 to R5C4C.D1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4C.D1 to       R5C4C.F1 myIwm/SLICE_27
+ROUTE         7     1.946       R5C4C.F1 to R4C5C.B1       myIwm/n395
+CTOOFX_DEL  ---     0.615       R4C5C.B1 to     R4C5C.OFX0 myIwm/SLICE_26
+ROUTE         1     0.000     R4C5C.OFX0 to R4C5C.DI0      myIwm/shifter_7_N_85_7 (to fclk_c)
+                  --------
+                    9.378   (32.3% logic, 67.7% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R7C4A.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C5C.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Error: The following path exceeds requirements by 6.286ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i7  (to fclk_c +)
+
+   Delay:               9.249ns  (32.8% logic, 67.2% route), 7 logic levels.
+
+ Constraint Details:
+
+      9.249ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_26 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 2.963ns) by 6.286ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_4 to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C4D.CLK to       R6C4D.Q1 myIwm/SLICE_4 (from fclk_c)
+ROUTE         8     1.080       R6C4D.Q1 to R6C3D.A0       myIwm/bitTimer_1
+CTOF_DEL    ---     0.371       R6C3D.A0 to       R6C3D.F0 myIwm/SLICE_51
+ROUTE         2     0.901       R6C3D.F0 to R6C4C.C0       myIwm/n6
+CTOF_DEL    ---     0.371       R6C4C.C0 to       R6C4C.F0 myIwm/SLICE_36
+ROUTE         5     1.138       R6C4C.F0 to R5C4D.B1       myIwm/n133
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 myIwm/SLICE_35
+ROUTE         1     0.497       R5C4D.F1 to R5C4D.C0       myIwm/n1516
+CTOF_DEL    ---     0.371       R5C4D.C0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.657       R5C4D.F0 to R5C4C.D1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4C.D1 to       R5C4C.F1 myIwm/SLICE_27
+ROUTE         7     1.946       R5C4C.F1 to R4C5C.B1       myIwm/n395
+CTOOFX_DEL  ---     0.615       R4C5C.B1 to     R4C5C.OFX0 myIwm/SLICE_26
+ROUTE         1     0.000     R4C5C.OFX0 to R4C5C.DI0      myIwm/shifter_7_N_85_7 (to fclk_c)
+                  --------
+                    9.249   (32.8% logic, 67.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R6C4D.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C5C.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Error: The following path exceeds requirements by 5.997ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i5  (to fclk_c +)
+
+   Delay:               8.960ns  (33.8% logic, 66.2% route), 7 logic levels.
+
+ Constraint Details:
+
+      8.960ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_24 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 2.963ns) by 5.997ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_5 to myIwm/SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 myIwm/SLICE_5 (from fclk_c)
+ROUTE         7     1.209       R7C4A.Q0 to R6C3D.D0       myIwm/bitTimer_2
+CTOF_DEL    ---     0.371       R6C3D.D0 to       R6C3D.F0 myIwm/SLICE_51
+ROUTE         2     0.901       R6C3D.F0 to R6C4C.C0       myIwm/n6
+CTOF_DEL    ---     0.371       R6C4C.C0 to       R6C4C.F0 myIwm/SLICE_36
+ROUTE         5     1.138       R6C4C.F0 to R5C4D.B1       myIwm/n133
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 myIwm/SLICE_35
+ROUTE         1     0.497       R5C4D.F1 to R5C4D.C0       myIwm/n1516
+CTOF_DEL    ---     0.371       R5C4D.C0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.657       R5C4D.F0 to R5C4C.D1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4C.D1 to       R5C4C.F1 myIwm/SLICE_27
+ROUTE         7     1.528       R5C4C.F1 to R4C5B.A1       myIwm/n395
+CTOOFX_DEL  ---     0.615       R4C5B.A1 to     R4C5B.OFX0 myIwm/SLICE_24
+ROUTE         1     0.000     R4C5B.OFX0 to R4C5B.DI0      myIwm/shifter_7_N_85_5 (to fclk_c)
+                  --------
+                    8.960   (33.8% logic, 66.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R7C4A.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C5B.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Error: The following path exceeds requirements by 5.997ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i6  (to fclk_c +)
+
+   Delay:               8.960ns  (33.8% logic, 66.2% route), 7 logic levels.
+
+ Constraint Details:
+
+      8.960ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_25 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 2.963ns) by 5.997ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_5 to myIwm/SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 myIwm/SLICE_5 (from fclk_c)
+ROUTE         7     1.209       R7C4A.Q0 to R6C3D.D0       myIwm/bitTimer_2
+CTOF_DEL    ---     0.371       R6C3D.D0 to       R6C3D.F0 myIwm/SLICE_51
+ROUTE         2     0.901       R6C3D.F0 to R6C4C.C0       myIwm/n6
+CTOF_DEL    ---     0.371       R6C4C.C0 to       R6C4C.F0 myIwm/SLICE_36
+ROUTE         5     1.138       R6C4C.F0 to R5C4D.B1       myIwm/n133
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 myIwm/SLICE_35
+ROUTE         1     0.497       R5C4D.F1 to R5C4D.C0       myIwm/n1516
+CTOF_DEL    ---     0.371       R5C4D.C0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.657       R5C4D.F0 to R5C4C.D1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4C.D1 to       R5C4C.F1 myIwm/SLICE_27
+ROUTE         7     1.528       R5C4C.F1 to R4C5D.A1       myIwm/n395
+CTOOFX_DEL  ---     0.615       R4C5D.A1 to     R4C5D.OFX0 myIwm/SLICE_25
+ROUTE         1     0.000     R4C5D.OFX0 to R4C5D.DI0      myIwm/shifter_7_N_85_6 (to fclk_c)
+                  --------
+                    8.960   (33.8% logic, 66.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R7C4A.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C5D.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Error: The following path exceeds requirements by 5.868ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i5  (to fclk_c +)
+
+   Delay:               8.831ns  (34.3% logic, 65.7% route), 7 logic levels.
+
+ Constraint Details:
+
+      8.831ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_24 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 2.963ns) by 5.868ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_4 to myIwm/SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C4D.CLK to       R6C4D.Q1 myIwm/SLICE_4 (from fclk_c)
+ROUTE         8     1.080       R6C4D.Q1 to R6C3D.A0       myIwm/bitTimer_1
+CTOF_DEL    ---     0.371       R6C3D.A0 to       R6C3D.F0 myIwm/SLICE_51
+ROUTE         2     0.901       R6C3D.F0 to R6C4C.C0       myIwm/n6
+CTOF_DEL    ---     0.371       R6C4C.C0 to       R6C4C.F0 myIwm/SLICE_36
+ROUTE         5     1.138       R6C4C.F0 to R5C4D.B1       myIwm/n133
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 myIwm/SLICE_35
+ROUTE         1     0.497       R5C4D.F1 to R5C4D.C0       myIwm/n1516
+CTOF_DEL    ---     0.371       R5C4D.C0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.657       R5C4D.F0 to R5C4C.D1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4C.D1 to       R5C4C.F1 myIwm/SLICE_27
+ROUTE         7     1.528       R5C4C.F1 to R4C5B.A1       myIwm/n395
+CTOOFX_DEL  ---     0.615       R4C5B.A1 to     R4C5B.OFX0 myIwm/SLICE_24
+ROUTE         1     0.000     R4C5B.OFX0 to R4C5B.DI0      myIwm/shifter_7_N_85_5 (to fclk_c)
+                  --------
+                    8.831   (34.3% logic, 65.7% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R6C4D.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C5B.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Error: The following path exceeds requirements by 5.868ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i6  (to fclk_c +)
+
+   Delay:               8.831ns  (34.3% logic, 65.7% route), 7 logic levels.
+
+ Constraint Details:
+
+      8.831ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_25 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 2.963ns) by 5.868ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_4 to myIwm/SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C4D.CLK to       R6C4D.Q1 myIwm/SLICE_4 (from fclk_c)
+ROUTE         8     1.080       R6C4D.Q1 to R6C3D.A0       myIwm/bitTimer_1
+CTOF_DEL    ---     0.371       R6C3D.A0 to       R6C3D.F0 myIwm/SLICE_51
+ROUTE         2     0.901       R6C3D.F0 to R6C4C.C0       myIwm/n6
+CTOF_DEL    ---     0.371       R6C4C.C0 to       R6C4C.F0 myIwm/SLICE_36
+ROUTE         5     1.138       R6C4C.F0 to R5C4D.B1       myIwm/n133
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 myIwm/SLICE_35
+ROUTE         1     0.497       R5C4D.F1 to R5C4D.C0       myIwm/n1516
+CTOF_DEL    ---     0.371       R5C4D.C0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.657       R5C4D.F0 to R5C4C.D1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4C.D1 to       R5C4C.F1 myIwm/SLICE_27
+ROUTE         7     1.528       R5C4C.F1 to R4C5D.A1       myIwm/n395
+CTOOFX_DEL  ---     0.615       R4C5D.A1 to     R4C5D.OFX0 myIwm/SLICE_25
+ROUTE         1     0.000     R4C5D.OFX0 to R4C5D.DI0      myIwm/shifter_7_N_85_6 (to fclk_c)
+                  --------
+                    8.831   (34.3% logic, 65.7% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R6C4D.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C5D.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Error: The following path exceeds requirements by 5.861ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i7  (to fclk_c +)
+
+   Delay:               8.824ns  (34.3% logic, 65.7% route), 7 logic levels.
+
+ Constraint Details:
+
+      8.824ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_26 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 2.963ns) by 5.861ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_5 to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 myIwm/SLICE_5 (from fclk_c)
+ROUTE         7     1.209       R7C4A.Q0 to R6C3D.D1       myIwm/bitTimer_2
+CTOF_DEL    ---     0.371       R6C3D.D1 to       R6C3D.F1 myIwm/SLICE_51
+ROUTE         1     0.636       R6C3D.F1 to R6C4A.A0       myIwm/n4
+CTOF_DEL    ---     0.371       R6C4A.A0 to       R6C4A.F0 myIwm/SLICE_37
+ROUTE         3     0.652       R6C4A.F0 to R6C4A.A1       myIwm/n123
+CTOF_DEL    ---     0.371       R6C4A.A1 to       R6C4A.F1 myIwm/SLICE_37
+ROUTE         1     0.694       R6C4A.F1 to R5C4D.D0       myIwm/n59
+CTOF_DEL    ---     0.371       R5C4D.D0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.657       R5C4D.F0 to R5C4C.D1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4C.D1 to       R5C4C.F1 myIwm/SLICE_27
+ROUTE         7     1.946       R5C4C.F1 to R4C5C.B1       myIwm/n395
+CTOOFX_DEL  ---     0.615       R4C5C.B1 to     R4C5C.OFX0 myIwm/SLICE_26
+ROUTE         1     0.000     R4C5C.OFX0 to R4C5C.DI0      myIwm/shifter_7_N_85_7 (to fclk_c)
+                  --------
+                    8.824   (34.3% logic, 65.7% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R7C4A.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C5C.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Error: The following path exceeds requirements by 5.732ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i7  (to fclk_c +)
+
+   Delay:               8.695ns  (34.8% logic, 65.2% route), 7 logic levels.
+
+ Constraint Details:
+
+      8.695ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_26 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 2.963ns) by 5.732ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_4 to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C4D.CLK to       R6C4D.Q1 myIwm/SLICE_4 (from fclk_c)
+ROUTE         8     1.080       R6C4D.Q1 to R6C3D.A1       myIwm/bitTimer_1
+CTOF_DEL    ---     0.371       R6C3D.A1 to       R6C3D.F1 myIwm/SLICE_51
+ROUTE         1     0.636       R6C3D.F1 to R6C4A.A0       myIwm/n4
+CTOF_DEL    ---     0.371       R6C4A.A0 to       R6C4A.F0 myIwm/SLICE_37
+ROUTE         3     0.652       R6C4A.F0 to R6C4A.A1       myIwm/n123
+CTOF_DEL    ---     0.371       R6C4A.A1 to       R6C4A.F1 myIwm/SLICE_37
+ROUTE         1     0.694       R6C4A.F1 to R5C4D.D0       myIwm/n59
+CTOF_DEL    ---     0.371       R5C4D.D0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.657       R5C4D.F0 to R5C4C.D1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4C.D1 to       R5C4C.F1 myIwm/SLICE_27
+ROUTE         7     1.946       R5C4C.F1 to R4C5C.B1       myIwm/n395
+CTOOFX_DEL  ---     0.615       R4C5C.B1 to     R4C5C.OFX0 myIwm/SLICE_26
+ROUTE         1     0.000     R4C5C.OFX0 to R4C5C.DI0      myIwm/shifter_7_N_85_7 (to fclk_c)
+                  --------
+                    8.695   (34.8% logic, 65.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R6C4D.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C5C.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Error: The following path exceeds requirements by 5.579ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i2  (to fclk_c +)
+
+   Delay:               8.542ns  (35.5% logic, 64.5% route), 7 logic levels.
+
+ Constraint Details:
+
+      8.542ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_21 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 2.963ns) by 5.579ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_5 to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 myIwm/SLICE_5 (from fclk_c)
+ROUTE         7     1.209       R7C4A.Q0 to R6C3D.D0       myIwm/bitTimer_2
+CTOF_DEL    ---     0.371       R6C3D.D0 to       R6C3D.F0 myIwm/SLICE_51
+ROUTE         2     0.901       R6C3D.F0 to R6C4C.C0       myIwm/n6
+CTOF_DEL    ---     0.371       R6C4C.C0 to       R6C4C.F0 myIwm/SLICE_36
+ROUTE         5     1.138       R6C4C.F0 to R5C4D.B1       myIwm/n133
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 myIwm/SLICE_35
+ROUTE         1     0.497       R5C4D.F1 to R5C4D.C0       myIwm/n1516
+CTOF_DEL    ---     0.371       R5C4D.C0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.657       R5C4D.F0 to R5C4C.D1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4C.D1 to       R5C4C.F1 myIwm/SLICE_27
+ROUTE         7     1.110       R5C4C.F1 to R4C4D.B1       myIwm/n395
+CTOOFX_DEL  ---     0.615       R4C4D.B1 to     R4C4D.OFX0 myIwm/SLICE_21
+ROUTE         1     0.000     R4C4D.OFX0 to R4C4D.DI0      myIwm/shifter_7_N_85_2 (to fclk_c)
+                  --------
+                    8.542   (35.5% logic, 64.5% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R7C4A.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C4D.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Error: The following path exceeds requirements by 5.551ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i7  (to fclk_c +)
+
+   Delay:               8.451ns  (28.6% logic, 71.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.451ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_26 exceeds
+      3.144ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 2.900ns) by 5.551ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_5 to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C4A.CLK to       R7C4A.Q0 myIwm/SLICE_5 (from fclk_c)
+ROUTE         7     1.209       R7C4A.Q0 to R6C3D.D0       myIwm/bitTimer_2
+CTOF_DEL    ---     0.371       R6C3D.D0 to       R6C3D.F0 myIwm/SLICE_51
+ROUTE         2     0.901       R6C3D.F0 to R6C4C.C0       myIwm/n6
+CTOF_DEL    ---     0.371       R6C4C.C0 to       R6C4C.F0 myIwm/SLICE_36
+ROUTE         5     1.138       R6C4C.F0 to R5C4D.B1       myIwm/n133
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 myIwm/SLICE_35
+ROUTE         1     0.497       R5C4D.F1 to R5C4D.C0       myIwm/n1516
+CTOF_DEL    ---     0.371       R5C4D.C0 to       R5C4D.F0 myIwm/SLICE_35
+ROUTE         3     0.727       R5C4D.F0 to R5C4B.B1       myIwm/n65
+CTOF_DEL    ---     0.371       R5C4B.B1 to       R5C4B.F1 myIwm/SLICE_45
+ROUTE         8     1.564       R5C4B.F1 to R4C5C.CE       myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.451   (28.6% logic, 71.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R7C4A.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        24     1.353       36.PADDI to R4C5C.CLK      fclk_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 104.613MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "fclk_c" 318.066000 MHz ; |  318.066 MHz|  104.613 MHz|   7 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+1 preference(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+myIwm/n65                               |       3|      10|    100.00%
+                                        |        |        |
+myIwm/n395                              |       7|       9|     90.00%
+                                        |        |        |
+myIwm/n133                              |       5|       8|     80.00%
+                                        |        |        |
+myIwm/n6                                |       2|       8|     80.00%
+                                        |        |        |
+myIwm/n1516                             |       1|       8|     80.00%
+                                        |        |        |
+myIwm/bitTimer_2                        |       7|       6|     60.00%
+                                        |        |        |
+myIwm/shifter_7_N_85_7                  |       1|       4|     40.00%
+                                        |        |        |
+myIwm/bitTimer_1                        |       8|       4|     40.00%
+                                        |        |        |
+myIwm/shifter_7_N_85_6                  |       1|       2|     20.00%
+                                        |        |        |
+myIwm/shifter_7_N_85_5                  |       1|       2|     20.00%
+                                        |        |        |
+myIwm/n123                              |       3|       2|     20.00%
+                                        |        |        |
+myIwm/n4                                |       1|       2|     20.00%
+                                        |        |        |
+myIwm/n59                               |       1|       2|     20.00%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 3 clocks:
+
+Clock Domain: fclk_c   Source: fclk.PAD   Loads: 24
+   Covered under: FREQUENCY NET "fclk_c" 318.066000 MHz ;
+
+   Data transfers from:
+   Clock Domain: _devsel_c   Source: _devsel.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: _devsel_c   Source: _devsel.PAD   Loads: 11
+   No transfer within this clock domain is found
+
+Clock Domain: _iosel_c   Source: _iosel.PAD   Loads: 2
+   No transfer within this clock domain is found
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 10  Score: 59154
+Cumulative negative slack: 59154
+
+Constraints cover 841 paths, 1 nets, and 319 connections (64.84% coverage)
+
diff --git a/lattice/fpgatop/codeROM_lse.twr b/lattice/fpgatop/codeROM_lse.twr
new file mode 100644
index 0000000..5a966b5
--- /dev/null
+++ b/lattice/fpgatop/codeROM_lse.twr
@@ -0,0 +1,50 @@
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Thu Jul 27 11:14:19 2017
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     codeROM
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 1000.000000 -name clk0 [get_nets OutClock_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk0 [get_nets OutClock_c]              |            -|            -|     0  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+
+Timing summary:
+---------------
+
+Timing errors: 0  Score: 0
+
+Constraints cover  0 paths, 0 nets, and 2 connections (5.6% coverage)
+
+
+Peak memory: 48201728 bytes, TRCE: 1507328 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
diff --git a/lattice/fpgatop/codeROM_prim.v b/lattice/fpgatop/codeROM_prim.v
new file mode 100644
index 0000000..d9f77c4
--- /dev/null
+++ b/lattice/fpgatop/codeROM_prim.v
@@ -0,0 +1,184 @@
+// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.9.0.99.2
+// Netlist written on Thu Jul 27 11:14:19 2017
+//
+// Verilog Description of module codeROM
+//
+
+module codeROM (Address, OutClock, OutClockEn, Reset, Q) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/coderom.v(8[8:15])
+    input [10:0]Address;   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    input OutClock;   // c:/users/chamberlin/documents/liron/lattice/coderom.v(10[16:24])
+    input OutClockEn;   // c:/users/chamberlin/documents/liron/lattice/coderom.v(11[16:26])
+    input Reset;   // c:/users/chamberlin/documents/liron/lattice/coderom.v(12[16:21])
+    output [7:0]Q;   // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
+    
+    wire OutClock_c /* synthesis is_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/coderom.v(10[16:24])
+    
+    wire Address_c_10, Address_c_9, Address_c_8, Address_c_7, Address_c_6, 
+        Address_c_5, Address_c_4, Address_c_3, Address_c_2, Address_c_1, 
+        Address_c_0, OutClockEn_c, Reset_c, Q_c_7, Q_c_6, Q_c_5, 
+        Q_c_4, Q_c_3, Q_c_2, Q_c_1, Q_c_0, scuba_vlo, VCC_net;
+    
+    OB Q_pad_4 (.I(Q_c_4), .O(Q[4]));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+    DP8KC codeROM_0_0_1_0 (.DIA0(scuba_vlo), .DIA1(scuba_vlo), .DIA2(scuba_vlo), 
+          .DIA3(scuba_vlo), .DIA4(scuba_vlo), .DIA5(scuba_vlo), .DIA6(scuba_vlo), 
+          .DIA7(scuba_vlo), .DIA8(scuba_vlo), .ADA0(scuba_vlo), .ADA1(scuba_vlo), 
+          .ADA2(Address_c_0), .ADA3(Address_c_1), .ADA4(Address_c_2), 
+          .ADA5(Address_c_3), .ADA6(Address_c_4), .ADA7(Address_c_5), 
+          .ADA8(Address_c_6), .ADA9(Address_c_7), .ADA10(Address_c_8), 
+          .ADA11(Address_c_9), .ADA12(Address_c_10), .CEA(OutClockEn_c), 
+          .OCEA(OutClockEn_c), .CLKA(OutClock_c), .WEA(scuba_vlo), .CSA0(scuba_vlo), 
+          .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(Reset_c), .DIB0(scuba_vlo), 
+          .DIB1(scuba_vlo), .DIB2(scuba_vlo), .DIB3(scuba_vlo), .DIB4(scuba_vlo), 
+          .DIB5(scuba_vlo), .DIB6(scuba_vlo), .DIB7(scuba_vlo), .DIB8(scuba_vlo), 
+          .ADB0(scuba_vlo), .ADB1(scuba_vlo), .ADB2(scuba_vlo), .ADB3(scuba_vlo), 
+          .ADB4(scuba_vlo), .ADB5(scuba_vlo), .ADB6(scuba_vlo), .ADB7(scuba_vlo), 
+          .ADB8(scuba_vlo), .ADB9(scuba_vlo), .ADB10(scuba_vlo), .ADB11(scuba_vlo), 
+          .ADB12(scuba_vlo), .CEB(VCC_net), .OCEB(VCC_net), .CLKB(scuba_vlo), 
+          .WEB(scuba_vlo), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo), 
+          .RSTB(scuba_vlo), .DOA0(Q_c_4), .DOA1(Q_c_5), .DOA2(Q_c_6), 
+          .DOA3(Q_c_7)) /* synthesis MEM_LPC_FILE="codeROM.lpc", MEM_INIT_FILE="rom-upper-2k.mem", syn_instantiated=1 */ ;
+    defparam codeROM_0_0_1_0.DATA_WIDTH_A = 4;
+    defparam codeROM_0_0_1_0.DATA_WIDTH_B = 4;
+    defparam codeROM_0_0_1_0.REGMODE_A = "OUTREG";
+    defparam codeROM_0_0_1_0.REGMODE_B = "NOREG";
+    defparam codeROM_0_0_1_0.CSDECODE_A = "0b000";
+    defparam codeROM_0_0_1_0.CSDECODE_B = "0b111";
+    defparam codeROM_0_0_1_0.WRITEMODE_A = "NORMAL";
+    defparam codeROM_0_0_1_0.WRITEMODE_B = "NORMAL";
+    defparam codeROM_0_0_1_0.GSR = "ENABLED";
+    defparam codeROM_0_0_1_0.RESETMODE = "SYNC";
+    defparam codeROM_0_0_1_0.ASYNC_RESET_RELEASE = "SYNC";
+    defparam codeROM_0_0_1_0.INIT_DATA = "STATIC";
+    defparam codeROM_0_0_1_0.INITVAL_00 = "0x1A4CD0500515E181909F1388118ABC112FA014C81784407ED8006C8166AC116C8178A2014C0058E2";
+    defparam codeROM_0_0_1_0.INITVAL_01 = "0x128A015CC1080D415C9419005178C813E9C1025A1F41F094CD05004158D21004A19A2C1A4CD04AAC";
+    defparam codeROM_0_0_1_0.INITVAL_02 = "0x178891004A188200905B19098008A41080014C4C1485E01AC4040480B65A1909F0388B0B080094C8";
+    defparam codeROM_0_0_1_0.INITVAL_03 = "0x00AAC0840510ABC112800B4C4040580B6C81300514C4C1A85E01AC4040580B6C8130051584200885";
+    defparam codeROM_0_0_1_0.INITVAL_04 = "0x18220140D8014C813ED40588B19A2C158D214044158891E2C8174041587401E4C188200B05B19098";
+    defparam codeROM_0_0_1_0.INITVAL_05 = "0x190BC116C004A8C0C25A0B02A0B05A0B05A0900A186461DCEC0A43C1FEFC0D88B190B11E6C8160B3";
+    defparam codeROM_0_0_1_0.INITVAL_06 = "0x100F1190B014A800CAA510A6105E4A1C28410848080490E4F1190B015EDC198381E2C8162AC116F1";
+    defparam codeROM_0_0_1_0.INITVAL_07 = "0x14CFD118F2014C0058F20B4C81788B18026090441909F0388B114050DC94198591080B080F1190B4";
+    defparam codeROM_0_0_1_0.INITVAL_08 = "0x10000010881000000000010881108810CA00000514CC81788B190BC116C104CC81788B182261FACC";
+    defparam codeROM_0_0_1_0.INITVAL_09 = "0x19C2815E9C1046C1C48A012C8040A014080100801008010080100081000810008100081000001088";
+    defparam codeROM_0_0_1_0.INITVAL_0A = "0x14AA61A2071BCD01FA5A0124800EA4100FA180200F04A01E8414079120F90B40A1744800EA4100FA";
+    defparam codeROM_0_0_1_0.INITVAL_0B = "0x0145E01E0E114580B41F094F700000000010000000000084061DA0F1AAAC064CF040A01386201E90";
+    defparam codeROM_0_0_1_0.INITVAL_0C = "0x140A40B4C1092ED006C41086C1B64801C0901846038EB0325014025108A01488C1B64819AB510A61";
+    defparam codeROM_0_0_1_0.INITVAL_0D = "0x028A50C6F110A600B6580148414A86090551FA850AA501E8A51CAE01E0E50AA5F1B0550AACE162F4";
+    defparam codeROM_0_0_1_0.INITVAL_0E = "0x14CFD024C80B2C8132CB0988B190B60BC090B00602AA40C6F1108610060412AB30145800C5A0B056";
+    defparam codeROM_0_0_1_0.INITVAL_0F = "0x0088400C0712CA00C20F12C1300EBA11AC5080960944C0164E068841C0940C2FD1882001448014A4";
+    defparam codeROM_0_0_1_0.INITVAL_10 = "0x100FB198400207B090EA0080B018040042204402094CE040A01E0751E80D1580F16A8F03844162A7";
+    defparam codeROM_0_0_1_0.INITVAL_11 = "0x014A7058EB0945D094FD100490B60A0B05B014C9080901C8A014A8510ABC14ABC0905B0145800EB5";
+    defparam codeROM_0_0_1_0.INITVAL_12 = "0x01E4A01A0C1904C08480148901584901EBF1B0490145A118D4144A21B0CC080AC1C40A01A0E1BA5C";
+    defparam codeROM_0_0_1_0.INITVAL_13 = "0x01A4A0900A0B07219CB4142100F65A0B04A0B04801448014E909C0F16AA2152D1152D1152D2140FC";
+    defparam codeROM_0_0_1_0.INITVAL_14 = "0x0885E0326510A6014245170A5160A11A0E3038EB09458094580944B18E2C00458114480B04A0B448";
+    defparam codeROM_0_0_1_0.INITVAL_15 = "0x094C4058B21D6CB04A85100A4140D4140100F65A07A0A012C604A8814884108A4140D0140A01A0EC";
+    defparam codeROM_0_0_1_0.INITVAL_16 = "0x01E2C01E2C01E2C0540B0980A02207162FA01E95148A01A4A01A224140790940F128A10207B0B41D";
+    defparam codeROM_0_0_1_0.INITVAL_17 = "0x01448088A4094441546C1C448000001008000C301EC1A00EB400EBA01EB21F21E1C8960140712AA8";
+    defparam codeROM_0_0_1_0.INITVAL_18 = "0x10C480C0F90B45A1DE4A18C2C0685C012C0048801488014AEC004581145801458094480145801448";
+    defparam codeROM_0_0_1_0.INITVAL_19 = "0x1B800142BC1C448000000B4F110049182B0140F900E9A14A8600E9901E9514C0713E401F2AA09064";
+    defparam codeROM_0_0_1_0.INITVAL_1A = "0x0340D0580A01A0F16AA01448015E220501A1F6401A0FE0140D014F805E920004A000000B40F000A0";
+    defparam codeROM_0_0_1_0.INITVAL_1B = "0x198CC158CC1B8CA1980C1B8CA198CC1B8CC158AD1980D19ADC158AC1C04F1BCFE040FC1B63A01A2C";
+    defparam codeROM_0_0_1_0.INITVAL_1C = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF000000A00D198CA19AAC1B8CA1980C19ACC";
+    defparam codeROM_0_0_1_0.INITVAL_1D = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    defparam codeROM_0_0_1_0.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    defparam codeROM_0_0_1_0.INITVAL_1F = "0x1FE1019ACA15CEC154FE1FEFE1D8AE1DEFC156BB174AC15EFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    OB Q_pad_5 (.I(Q_c_5), .O(Q[5]));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
+    OB Q_pad_6 (.I(Q_c_6), .O(Q[6]));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
+    DP8KC codeROM_0_0_0_1 (.DIA0(scuba_vlo), .DIA1(scuba_vlo), .DIA2(scuba_vlo), 
+          .DIA3(scuba_vlo), .DIA4(scuba_vlo), .DIA5(scuba_vlo), .DIA6(scuba_vlo), 
+          .DIA7(scuba_vlo), .DIA8(scuba_vlo), .ADA0(scuba_vlo), .ADA1(scuba_vlo), 
+          .ADA2(Address_c_0), .ADA3(Address_c_1), .ADA4(Address_c_2), 
+          .ADA5(Address_c_3), .ADA6(Address_c_4), .ADA7(Address_c_5), 
+          .ADA8(Address_c_6), .ADA9(Address_c_7), .ADA10(Address_c_8), 
+          .ADA11(Address_c_9), .ADA12(Address_c_10), .CEA(OutClockEn_c), 
+          .OCEA(OutClockEn_c), .CLKA(OutClock_c), .WEA(scuba_vlo), .CSA0(scuba_vlo), 
+          .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(Reset_c), .DIB0(scuba_vlo), 
+          .DIB1(scuba_vlo), .DIB2(scuba_vlo), .DIB3(scuba_vlo), .DIB4(scuba_vlo), 
+          .DIB5(scuba_vlo), .DIB6(scuba_vlo), .DIB7(scuba_vlo), .DIB8(scuba_vlo), 
+          .ADB0(scuba_vlo), .ADB1(scuba_vlo), .ADB2(scuba_vlo), .ADB3(scuba_vlo), 
+          .ADB4(scuba_vlo), .ADB5(scuba_vlo), .ADB6(scuba_vlo), .ADB7(scuba_vlo), 
+          .ADB8(scuba_vlo), .ADB9(scuba_vlo), .ADB10(scuba_vlo), .ADB11(scuba_vlo), 
+          .ADB12(scuba_vlo), .CEB(VCC_net), .OCEB(VCC_net), .CLKB(scuba_vlo), 
+          .WEB(scuba_vlo), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo), 
+          .RSTB(scuba_vlo), .DOA0(Q_c_0), .DOA1(Q_c_1), .DOA2(Q_c_2), 
+          .DOA3(Q_c_3)) /* synthesis MEM_LPC_FILE="codeROM.lpc", MEM_INIT_FILE="rom-upper-2k.mem", syn_instantiated=1 */ ;
+    defparam codeROM_0_0_0_1.DATA_WIDTH_A = 4;
+    defparam codeROM_0_0_0_1.DATA_WIDTH_B = 4;
+    defparam codeROM_0_0_0_1.REGMODE_A = "OUTREG";
+    defparam codeROM_0_0_0_1.REGMODE_B = "NOREG";
+    defparam codeROM_0_0_0_1.CSDECODE_A = "0b000";
+    defparam codeROM_0_0_0_1.CSDECODE_B = "0b111";
+    defparam codeROM_0_0_0_1.WRITEMODE_A = "NORMAL";
+    defparam codeROM_0_0_0_1.WRITEMODE_B = "NORMAL";
+    defparam codeROM_0_0_0_1.GSR = "ENABLED";
+    defparam codeROM_0_0_0_1.RESETMODE = "SYNC";
+    defparam codeROM_0_0_0_1.ASYNC_RESET_RELEASE = "SYNC";
+    defparam codeROM_0_0_0_1.INIT_DATA = "STATIC";
+    defparam codeROM_0_0_0_1.INITVAL_00 = "0x0C0980009A0A40801ADB000CE120901FAF90A0011B29C110080E00E1A40013A0B1B6900E0A5014E0";
+    defparam codeROM_0_0_0_1.INITVAL_01 = "0x1A250014931860B0BE0C080940300D1B60019C951E05018A980009B0B280012C512C090C09801659";
+    defparam codeROM_0_0_0_1.INITVAL_02 = "0x020DD012F51026A1CA6101AD013C510A25213088078760A0810D4D50C29401ADB000CC128091AA0D";
+    defparam codeROM_0_0_0_1.INITVAL_03 = "0x1265802CA20AC101BA0904A810D4150C20D1A0910B0881F8760A0810D4050C20D1A0900B01615E56";
+    defparam codeROM_0_0_0_1.INITVAL_04 = "0x15E01130081400D1B200120CD1300813280152A00A0DD1600C194900B0DC060B61026A06A6101AD0";
+    defparam codeROM_0_0_0_1.INITVAL_05 = "0x01CD01BAA5006501308504A190EA550CA4500A0913AC0154A9160FF078F3000CD000D80000E1AC08";
+    defparam codeROM_0_0_0_1.INITVAL_06 = "0x0B4B0018D000E5012A560A8580E0C51A0800A050120B91F2B0018D60080313C081600C1BC0003AB0";
+    defparam codeROM_0_0_0_1.INITVAL_07 = "0x040A0112F0140AF01280000051A01D15E0000A0501ADB000CC0120219C0C090410122002CB0018D1";
+    defparam codeROM_0_0_0_1.INITVAL_08 = "0x000000000000000000000000000000000AA154A80A0061A04D004D001AAF000071A03D15E001A0A8";
+    defparam codeROM_0_0_0_1.INITVAL_09 = "0x1BA001340A1400D1A0090A0AA0000512000000000000000000000000000000000000000000000000";
+    defparam codeROM_0_0_0_1.INITVAL_0A = "0x13040160581C00411C86180E50F0DD0AC8D1000711AE50D0DD0AA8D1088D10CB0112E50F0DD0AC8D";
+    defparam codeROM_0_0_0_1.INITVAL_0B = "0x0127608010012750AA301CCFF0041404202128210024012800180481D0691A0980020F0120009095";
+    defparam codeROM_0_0_0_1.INITVAL_0C = "0x0C0980AABF190200C0AB0B65A1FAC50F2200F2C51145D0A09610E990BA550585A19AB5152D60A858";
+    defparam codeROM_0_0_0_1.INITVAL_0D = "0x118590D0801126A082950128C08A5800A41160840281901A450CA62002060281901061082AB18C0E";
+    defparam codeROM_0_0_0_1.INITVAL_0E = "0x0A0401F20E1B00F1B0B6180DD010D00EC200CA7910C510D020102680200D12C180C075012550CA45";
+    defparam codeROM_0_0_0_1.INITVAL_0F = "0x110A801268130A3130581301009098150E918600168B6040C51184B0C40C0B0A01566A064B60048B";
+    defparam codeROM_0_0_0_1.INITVAL_10 = "0x0AA8919EC30088906C8A0522008029072A81548A06ADD0009500E891F2700B2681304A014800B628";
+    defparam codeROM_0_0_0_1.INITVAL_11 = "0x0928F13A3D04C9006A80100290828014A41000DF1860A00461128650A8181481804A41020550D094";
+    defparam codeROM_0_0_0_1.INITVAL_12 = "0x160661604919ACE1E08812810130410F0DB010410E086148060C293014D11809D1A00914050160A4";
+    defparam codeROM_0_0_0_1.INITVAL_13 = "0x0402510A0914AF91A6D20C60411A8608A290AAE5012D5132B0068781D0481200F12801130011300A";
+    defparam codeROM_0_0_0_1.INITVAL_14 = "0x1F856060840A85213084030A4022080080B01A3D04C550AA4508A6014C0A1E0B50123514C3614A65";
+    defparam codeROM_0_0_0_1.INITVAL_15 = "0x04AEF016F0080AD00A640A025130020B804112841E069080A70165213A5E0CC570C802040960040D";
+    defparam codeROM_0_0_0_1.INITVAL_16 = "0x020F90A089120B90E4E0012020A0481D40A0909809A5201E94000950AC8D0EA581AC540088D10CB0";
+    defparam codeROM_0_0_0_1.INITVAL_17 = "0x0B26610C5806A820B4890A083062110623306081010880D0980B09A0B098100C010058004581304A";
+    defparam codeROM_0_0_0_1.INITVAL_18 = "0x0B06510E89108A50A0D51200E098A60A08001C5013A591346A1E0B5012550124505235052A501225";
+    defparam codeROM_0_0_0_1.INITVAL_19 = "0x014801CA0B0C035154AA10A70100291EC9500C8D090DA130600D0D80B0D80C07813E961125904A83";
+    defparam codeROM_0_0_0_1.INITVAL_1A = "0x1C420112A2040481304004850138200AC72154C300E8C02CA000CE901C30102CA154AA10AA0102EF";
+    defparam codeROM_0_0_0_1.INITVAL_1B = "0x1DCF300A390CA401FC0B072400B82109EF2002041FC021E42501EF9000C5010DD00C0E09A22040F9";
+    defparam codeROM_0_0_0_1.INITVAL_1C = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF00080002041FE201E80B072401FC040A835";
+    defparam codeROM_0_0_0_1.INITVAL_1D = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    defparam codeROM_0_0_0_1.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    defparam codeROM_0_0_0_1.INITVAL_1F = "0x1FE00026D01C6E90182508A0D1E6051800100A890209311EFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    OB Q_pad_7 (.I(Q_c_7), .O(Q[7]));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
+    OB Q_pad_3 (.I(Q_c_3), .O(Q[3]));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
+    OB Q_pad_2 (.I(Q_c_2), .O(Q[2]));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
+    OB Q_pad_1 (.I(Q_c_1), .O(Q[1]));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
+    OB Q_pad_0 (.I(Q_c_0), .O(Q[0]));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
+    IB Address_pad_10 (.I(Address[10]), .O(Address_c_10));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_9 (.I(Address[9]), .O(Address_c_9));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_8 (.I(Address[8]), .O(Address_c_8));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_7 (.I(Address[7]), .O(Address_c_7));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_6 (.I(Address[6]), .O(Address_c_6));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_5 (.I(Address[5]), .O(Address_c_5));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_4 (.I(Address[4]), .O(Address_c_4));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_3 (.I(Address[3]), .O(Address_c_3));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_2 (.I(Address[2]), .O(Address_c_2));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_1 (.I(Address[1]), .O(Address_c_1));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB Address_pad_0 (.I(Address[0]), .O(Address_c_0));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
+    IB OutClock_pad (.I(OutClock), .O(OutClock_c));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(10[16:24])
+    IB OutClockEn_pad (.I(OutClockEn), .O(OutClockEn_c));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(11[16:26])
+    IB Reset_pad (.I(Reset), .O(Reset_c));   // c:/users/chamberlin/documents/liron/lattice/coderom.v(12[16:21])
+    GSR GSR_INST (.GSR(VCC_net));
+    TSALL TSALL_INST (.TSALL(scuba_vlo));
+    PUR PUR_INST (.PUR(VCC_net));
+    defparam PUR_INST.RST_PULSE = 1;
+    VHI i7 (.Z(VCC_net));
+    
+endmodule
+//
+// Verilog Description of module TSALL
+// module not written out since it is a black-box. 
+//
+
+//
+// Verilog Description of module PUR
+// module not written out since it is a black-box. 
+//
+
diff --git a/lattice/fpgatop/fpgatop.xcf b/lattice/fpgatop/fpgatop.xcf
new file mode 100644
index 0000000..1e23393
--- /dev/null
+++ b/lattice/fpgatop/fpgatop.xcf
@@ -0,0 +1,51 @@
+
+
+
+	
+	
+		JTAG
+		
+			
+			1
+			Lattice
+			MachXO2
+			LCMXO2-1200HC
+			0x012ba043
+			All
+			LCMXO2-1200HC
+			
+				8
+				11111111
+				1
+				0
+			
+			C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/liron_fpgatop.jed
+			02/22/18 10:56:48
+			0x3262
+			FLASH Erase,Program,Verify
+			
+		
+	
+	
+		SEQUENTIAL
+		ENTIRED CHAIN
+		No Override
+		TLR
+		TLR
+		
+		1
+	
+	
+		USB
+		EzUSB-0
+		\\?\usb#vid_1134&amp;pid_8001#5&amp;5cf71e0&amp;0&amp;4#
+	
+
diff --git a/lattice/fpgatop/hdla_gen_hierarchy.html b/lattice/fpgatop/hdla_gen_hierarchy.html
new file mode 100644
index 0000000..09c8ad6
--- /dev/null
+++ b/lattice/fpgatop/hdla_gen_hierarchy.html
@@ -0,0 +1,21 @@
+         	                                   	                                                	                                                 	                                                  	
Setting log file to 'C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/lattice/top.v
+(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v
+(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/lattice/iwm.v
+(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v
+INFO - C:/Users/chamberlin/Documents/Liron/lattice/top.v(2,8-2,11) (VERI-1018) compiling module top
+INFO - C:/Users/chamberlin/Documents/Liron/lattice/top.v(2,1-112,10) (VERI-9000) elaborating module 'top'
+INFO - C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v(2,1-37,10) (VERI-9000) elaborating module 'addrDecoder_uniq_1'
+INFO - C:/Users/chamberlin/Documents/Liron/lattice/iwm.v(2,1-296,10) (VERI-9000) elaborating module 'iwm_uniq_1'
+INFO - C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v(8,1-295,10) (VERI-9000) elaborating module 'codeROM_uniq_1'
+INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1'
+INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2'
+INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_3'
+INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_4'
+INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
+INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
+Done: design load finished with (0) errors, and (0) warnings
+
+

\ No newline at end of file
diff --git a/lattice/fpgatop/liron_fpgatop.alt b/lattice/fpgatop/liron_fpgatop.alt
new file mode 100644
index 0000000..724771f
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.alt
@@ -0,0 +1,60 @@
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Thu Feb 22 10:56:48 2018 *
+NOTE DESIGN NAME: top *
+NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS data[7] : 52 : inout *
+NOTE PINS data[6] : 51 : inout *
+NOTE PINS data[5] : 47 : inout *
+NOTE PINS data[4] : 39 : inout *
+NOTE PINS data[3] : 38 : inout *
+NOTE PINS data[2] : 37 : inout *
+NOTE PINS data[1] : 36 : inout *
+NOTE PINS data[0] : 35 : inout *
+NOTE PINS wrdata : 83 : out *
+NOTE PINS phase[3] : 87 : out *
+NOTE PINS phase[2] : 86 : out *
+NOTE PINS phase[1] : 85 : out *
+NOTE PINS phase[0] : 84 : out *
+NOTE PINS _wrreq : 88 : out *
+NOTE PINS _enbl1 : 82 : out *
+NOTE PINS _enbl2 : 99 : out *
+NOTE PINS select : 78 : out *
+NOTE PINS _en35 : 98 : out *
+NOTE PINS spi_clk : 31 : out *
+NOTE PINS spi_mosi : 49 : out *
+NOTE PINS spi_cs : 27 : out *
+NOTE PINS _en245 : 30 : out *
+NOTE PINS debugInfo[7] : 25 : out *
+NOTE PINS debugInfo[6] : 24 : out *
+NOTE PINS debugInfo[5] : 17 : out *
+NOTE PINS debugInfo[4] : 16 : out *
+NOTE PINS debugInfo[3] : 15 : out *
+NOTE PINS debugInfo[2] : 14 : out *
+NOTE PINS debugInfo[1] : 13 : out *
+NOTE PINS debugInfo[0] : 12 : out *
+NOTE PINS addr[11] : 69 : in *
+NOTE PINS addr[10] : 68 : in *
+NOTE PINS addr[9] : 67 : in *
+NOTE PINS addr[8] : 66 : in *
+NOTE PINS addr[7] : 65 : in *
+NOTE PINS addr[6] : 64 : in *
+NOTE PINS addr[5] : 62 : in *
+NOTE PINS addr[4] : 60 : in *
+NOTE PINS addr[3] : 59 : in *
+NOTE PINS addr[2] : 58 : in *
+NOTE PINS addr[1] : 57 : in *
+NOTE PINS addr[0] : 54 : in *
+NOTE PINS fclk : 63 : in *
+NOTE PINS q3 : 70 : in *
+NOTE PINS rw : 71 : in *
+NOTE PINS _iostrobe : 74 : in *
+NOTE PINS _iosel : 53 : in *
+NOTE PINS _devsel : 34 : in *
+NOTE PINS _reset : 75 : in *
+NOTE PINS sense : 97 : in *
+NOTE PINS rddata : 96 : in *
+NOTE PINS spi_miso : 32 : in *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: on *
diff --git a/lattice/fpgatop/liron_fpgatop.arearep b/lattice/fpgatop/liron_fpgatop.arearep
new file mode 100644
index 0000000..2dd8610
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.arearep
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+Report for cell top.TECH
+Register bits:  43 of 1520 (2.829%)
+I/O cells:      52
+                                  Cell usage:
+                               cell     count   Res Usage(%)
+                                 BB         8          100.0
+                              DP8KC         4          100.0
+                            FD1P3AX        29          100.0
+                            FD1P3IX        10          100.0
+                            FD1P3JX         1          100.0
+                            FD1S3AX         2          100.0
+                            FD1S3AY         1          100.0
+                                GSR         1          100.0
+                                 IB        22          100.0
+                                INV         1          100.0
+                               LUT4       115          100.0
+                                 OB        19          100.0
+                                OBZ         3          100.0
+                              PFUMX         1          100.0
+SUB MODULES
+                        addrDecoder         1
+                            codeROM         1
+                                iwm         1
+                              TOTAL       220
+----------------------------------------------------------------------
+Report for cell iwm.v1
+Instance Path : myIwm
+                                  Cell usage:
+                               cell     count   Res Usage(%)
+                            FD1P3AX        29          100.0
+                            FD1P3IX         9           90.0
+                            FD1P3JX         1          100.0
+                            FD1S3AX         2          100.0
+                            FD1S3AY         1          100.0
+                               LUT4       103           89.6
+                              PFUMX         1          100.0
+                              TOTAL       146
+----------------------------------------------------------------------
+Report for cell codeROM.v1
+Instance Path : myROM
+                                  Cell usage:
+                               cell     count   Res Usage(%)
+                              DP8KC         4          100.0
+                              TOTAL         4
+----------------------------------------------------------------------
+Report for cell addrDecoder.v1
+Instance Path : myAddrDecoder
+                                  Cell usage:
+                               cell     count   Res Usage(%)
+                            FD1P3IX         1           10.0
+                               LUT4         4            3.5
+                              TOTAL         5
diff --git a/lattice/fpgatop/liron_fpgatop.bgn b/lattice/fpgatop/liron_fpgatop.bgn
new file mode 100644
index 0000000..e0f40b6
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.bgn
@@ -0,0 +1,82 @@
+BITGEN: Bitstream Generator Diamond (64-bit) 3.9.0.99.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Command: bitgen -g RamCfg:Reset -path C:/Users/chamberlin/Documents/Liron/lattice -w -jedec -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf 
+
+Loading design for application Bitgen from file liron_fpgatop.ncd.
+Design name: top
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from liron_fpgatop.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.94.
+ 
+Saving bit stream in "liron_fpgatop.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        511 Pages (128*511 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
+Initialized UFM Pages:                     0 Page.
+ 
diff --git a/lattice/fpgatop/liron_fpgatop.dir/5_1.ncd b/lattice/fpgatop/liron_fpgatop.dir/5_1.ncd
new file mode 100644
index 0000000..b5f7b06
Binary files /dev/null and b/lattice/fpgatop/liron_fpgatop.dir/5_1.ncd differ
diff --git a/lattice/fpgatop/liron_fpgatop.dir/5_1.pad b/lattice/fpgatop/liron_fpgatop.dir/5_1.pad
new file mode 100644
index 0000000..c3d5eae
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.dir/5_1.pad
@@ -0,0 +1,279 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Thu Feb 22 10:56:42 2018
+
+Pinout by Port Name:
++--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name    | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
++--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| _devsel      | 34/2     | LVCMOS33_IN   | PB9A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _en245       | 30/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _en35        | 98/0     | LVCMOS33_OUT  | PT9B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _enbl1       | 82/0     | LVCMOS33_OUT  | PT15C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _enbl2       | 99/0     | LVCMOS33_OUT  | PT9A  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _iosel       | 53/1     | LVCMOS33_IN   | PR9D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _iostrobe    | 74/1     | LVCMOS33_IN   | PR2B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _reset       | 75/1     | LVCMOS33_IN   | PR2A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _wrreq       | 88/0     | LVCMOS33_OUT  | PT12A |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| addr[0]      | 54/1     | LVCMOS33_IN   | PR9C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[10]     | 68/1     | LVCMOS33_IN   | PR4B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[11]     | 69/1     | LVCMOS33_IN   | PR4A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[1]      | 57/1     | LVCMOS33_IN   | PR9B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[2]      | 58/1     | LVCMOS33_IN   | PR9A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[3]      | 59/1     | LVCMOS33_IN   | PR8D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[4]      | 60/1     | LVCMOS33_IN   | PR8C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[5]      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[6]      | 64/1     | LVCMOS33_IN   | PR5B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[7]      | 65/1     | LVCMOS33_IN   | PR5A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[8]      | 66/1     | LVCMOS33_IN   | PR4D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[9]      | 67/1     | LVCMOS33_IN   | PR4C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| data[0]      | 35/2     | LVCMOS33_BIDI | PB9B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[1]      | 36/2     | LVCMOS33_BIDI | PB11C |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[2]      | 37/2     | LVCMOS33_BIDI | PB11D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[3]      | 38/2     | LVCMOS33_BIDI | PB11A |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[4]      | 39/2     | LVCMOS33_BIDI | PB11B |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[5]      | 47/2     | LVCMOS33_BIDI | PB18D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[6]      | 51/1     | LVCMOS33_BIDI | PR10D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[7]      | 52/1     | LVCMOS33_BIDI | PR10C |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| debugInfo[0] | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[1] | 13/3     | LVCMOS33_OUT  | PL5B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[2] | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[3] | 15/3     | LVCMOS33_OUT  | PL5D  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[4] | 16/3     | LVCMOS33_OUT  | PL8A  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[5] | 17/3     | LVCMOS33_OUT  | PL8B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[6] | 24/3     | LVCMOS33_OUT  | PL10C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[7] | 25/3     | LVCMOS33_OUT  | PL10D |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| fclk         | 63/1     | LVCMOS33_IN   | PR5C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| phase[0]     | 84/0     | LVCMOS33_OUT  | PT15A |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| phase[1]     | 85/0     | LVCMOS33_OUT  | PT12D |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| phase[2]     | 86/0     | LVCMOS33_OUT  | PT12C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| phase[3]     | 87/0     | LVCMOS33_OUT  | PT12B |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| q3           | 70/1     | LVCMOS33_IN   | PR3B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| rddata       | 96/0     | LVCMOS33_IN   | PT10B |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| rw           | 71/1     | LVCMOS33_IN   | PR3A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| select       | 78/0     | LVCMOS33_OUT  | PT16C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| sense        | 97/0     | LVCMOS33_IN   | PT10A |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| spi_clk      | 31/2     | LVCMOS33_OUT  | PB6C  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| spi_cs       | 27/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| spi_miso     | 32/2     | LVCMOS33_IN   | PB6D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| spi_mosi     | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| wrdata       | 83/0     | LVCMOS33_OUT  | PT15B |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
++--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      |     unused, PULL:DOWN |            |               | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      |     unused, PULL:DOWN |            |               | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      |     unused, PULL:DOWN |            |               | PL3A  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |               | PL3B  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |               | PL3C  |               |           |           |
+| 8/3      |     unused, PULL:DOWN |            |               | PL3D  |               |           |           |
+| 9/3      |     unused, PULL:DOWN |            |               | PL4A  |               |           |           |
+| 10/3     |     unused, PULL:DOWN |            |               | PL4B  |               |           |           |
+| 12/3     | debugInfo[0]          | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | debugInfo[1]          | LOCATED    | LVCMOS33_OUT  | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | debugInfo[2]          | LOCATED    | LVCMOS33_OUT  | PL5C  |               |           |           |
+| 15/3     | debugInfo[3]          | LOCATED    | LVCMOS33_OUT  | PL5D  |               |           |           |
+| 16/3     | debugInfo[4]          | LOCATED    | LVCMOS33_OUT  | PL8A  |               |           |           |
+| 17/3     | debugInfo[5]          | LOCATED    | LVCMOS33_OUT  | PL8B  |               |           |           |
+| 18/3     |     unused, PULL:DOWN |            |               | PL8C  |               |           |           |
+| 19/3     |     unused, PULL:DOWN |            |               | PL8D  |               |           |           |
+| 20/3     |     unused, PULL:DOWN |            |               | PL9A  | PCLKT3_0      |           |           |
+| 21/3     |     unused, PULL:DOWN |            |               | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | debugInfo[6]          | LOCATED    | LVCMOS33_OUT  | PL10C |               |           |           |
+| 25/3     | debugInfo[7]          | LOCATED    | LVCMOS33_OUT  | PL10D |               |           |           |
+| 27/2     | spi_cs                | LOCATED    | LVCMOS33_OUT  | PB4C  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |               | PB4D  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |               | PB6A  |               |           |           |
+| 30/2     | _en245                | LOCATED    | LVCMOS33_OUT  | PB6B  |               |           |           |
+| 31/2     | spi_clk               | LOCATED    | LVCMOS33_OUT  | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | spi_miso              | LOCATED    | LVCMOS33_IN   | PB6D  | SO/SPISO      |           |           |
+| 34/2     | _devsel               | LOCATED    | LVCMOS33_IN   | PB9A  | PCLKT2_0      |           |           |
+| 35/2     | data[0]               | LOCATED    | LVCMOS33_BIDI | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | data[1]               | LOCATED    | LVCMOS33_BIDI | PB11C |               |           |           |
+| 37/2     | data[2]               | LOCATED    | LVCMOS33_BIDI | PB11D |               |           |           |
+| 38/2     | data[3]               | LOCATED    | LVCMOS33_BIDI | PB11A | PCLKT2_1      |           |           |
+| 39/2     | data[4]               | LOCATED    | LVCMOS33_BIDI | PB11B | PCLKC2_1      |           |           |
+| 40/2     |     unused, PULL:DOWN |            |               | PB15A |               |           |           |
+| 41/2     |     unused, PULL:DOWN |            |               | PB15B |               |           |           |
+| 42/2     |     unused, PULL:DOWN |            |               | PB18A |               |           |           |
+| 43/2     |     unused, PULL:DOWN |            |               | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB18C |               |           |           |
+| 47/2     | data[5]               | LOCATED    | LVCMOS33_BIDI | PB18D |               |           |           |
+| 48/2     | Prohibited/Reserved   | PROHIBITED |               | PB20C | SN            |           |           |
+| 49/2     | spi_mosi              | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | data[6]               | LOCATED    | LVCMOS33_BIDI | PR10D | DQ1           |           |           |
+| 52/1     | data[7]               | LOCATED    | LVCMOS33_BIDI | PR10C | DQ1           |           |           |
+| 53/1     | _iosel                | LOCATED    | LVCMOS33_IN   | PR9D  | DQ1           |           |           |
+| 54/1     | addr[0]               | LOCATED    | LVCMOS33_IN   | PR9C  | DQ1           |           |           |
+| 57/1     | addr[1]               | LOCATED    | LVCMOS33_IN   | PR9B  | DQ1           |           |           |
+| 58/1     | addr[2]               | LOCATED    | LVCMOS33_IN   | PR9A  | DQ1           |           |           |
+| 59/1     | addr[3]               | LOCATED    | LVCMOS33_IN   | PR8D  | DQ1           |           |           |
+| 60/1     | addr[4]               | LOCATED    | LVCMOS33_IN   | PR8C  | DQ1           |           |           |
+| 61/1     | Prohibited/Reserved   | PROHIBITED |               | PR8A  | DQS1          |           |           |
+| 62/1     | addr[5]               | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     | fclk                  | LOCATED    | LVCMOS33_IN   | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | addr[6]               | LOCATED    | LVCMOS33_IN   | PR5B  | DQS0N         |           |           |
+| 65/1     | addr[7]               | LOCATED    | LVCMOS33_IN   | PR5A  | DQS0          |           |           |
+| 66/1     | addr[8]               | LOCATED    | LVCMOS33_IN   | PR4D  | DQ0           |           |           |
+| 67/1     | addr[9]               | LOCATED    | LVCMOS33_IN   | PR4C  | DQ0           |           |           |
+| 68/1     | addr[10]              | LOCATED    | LVCMOS33_IN   | PR4B  | DQ0           |           |           |
+| 69/1     | addr[11]              | LOCATED    | LVCMOS33_IN   | PR4A  | DQ0           |           |           |
+| 70/1     | q3                    | LOCATED    | LVCMOS33_IN   | PR3B  | DQ0           |           |           |
+| 71/1     | rw                    | LOCATED    | LVCMOS33_IN   | PR3A  | DQ0           |           |           |
+| 74/1     | _iostrobe             | LOCATED    | LVCMOS33_IN   | PR2B  | DQ0           |           |           |
+| 75/1     | _reset                | LOCATED    | LVCMOS33_IN   | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
+| 78/0     | select                | LOCATED    | LVCMOS33_OUT  | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
+| 82/0     | _enbl1                | LOCATED    | LVCMOS33_OUT  | PT15C | JTAGENB       |           |           |
+| 83/0     | wrdata                | LOCATED    | LVCMOS33_OUT  | PT15B |               |           |           |
+| 84/0     | phase[0]              | LOCATED    | LVCMOS33_OUT  | PT15A |               |           |           |
+| 85/0     | phase[1]              | LOCATED    | LVCMOS33_OUT  | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | phase[2]              | LOCATED    | LVCMOS33_OUT  | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | phase[3]              | LOCATED    | LVCMOS33_OUT  | PT12B | PCLKC0_1      |           |           |
+| 88/0     | _wrreq                | LOCATED    | LVCMOS33_OUT  | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | rddata                | LOCATED    | LVCMOS33_IN   | PT10B |               |           |           |
+| 97/0     | sense                 | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
+| 98/0     | _en35                 | LOCATED    | LVCMOS33_OUT  | PT9B  |               |           |           |
+| 99/0     | _enbl2                | LOCATED    | LVCMOS33_OUT  | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "_devsel"  SITE  "34";
+LOCATE  COMP  "_en245"  SITE  "30";
+LOCATE  COMP  "_en35"  SITE  "98";
+LOCATE  COMP  "_enbl1"  SITE  "82";
+LOCATE  COMP  "_enbl2"  SITE  "99";
+LOCATE  COMP  "_iosel"  SITE  "53";
+LOCATE  COMP  "_iostrobe"  SITE  "74";
+LOCATE  COMP  "_reset"  SITE  "75";
+LOCATE  COMP  "_wrreq"  SITE  "88";
+LOCATE  COMP  "addr[0]"  SITE  "54";
+LOCATE  COMP  "addr[10]"  SITE  "68";
+LOCATE  COMP  "addr[11]"  SITE  "69";
+LOCATE  COMP  "addr[1]"  SITE  "57";
+LOCATE  COMP  "addr[2]"  SITE  "58";
+LOCATE  COMP  "addr[3]"  SITE  "59";
+LOCATE  COMP  "addr[4]"  SITE  "60";
+LOCATE  COMP  "addr[5]"  SITE  "62";
+LOCATE  COMP  "addr[6]"  SITE  "64";
+LOCATE  COMP  "addr[7]"  SITE  "65";
+LOCATE  COMP  "addr[8]"  SITE  "66";
+LOCATE  COMP  "addr[9]"  SITE  "67";
+LOCATE  COMP  "data[0]"  SITE  "35";
+LOCATE  COMP  "data[1]"  SITE  "36";
+LOCATE  COMP  "data[2]"  SITE  "37";
+LOCATE  COMP  "data[3]"  SITE  "38";
+LOCATE  COMP  "data[4]"  SITE  "39";
+LOCATE  COMP  "data[5]"  SITE  "47";
+LOCATE  COMP  "data[6]"  SITE  "51";
+LOCATE  COMP  "data[7]"  SITE  "52";
+LOCATE  COMP  "debugInfo[0]"  SITE  "12";
+LOCATE  COMP  "debugInfo[1]"  SITE  "13";
+LOCATE  COMP  "debugInfo[2]"  SITE  "14";
+LOCATE  COMP  "debugInfo[3]"  SITE  "15";
+LOCATE  COMP  "debugInfo[4]"  SITE  "16";
+LOCATE  COMP  "debugInfo[5]"  SITE  "17";
+LOCATE  COMP  "debugInfo[6]"  SITE  "24";
+LOCATE  COMP  "debugInfo[7]"  SITE  "25";
+LOCATE  COMP  "fclk"  SITE  "63";
+LOCATE  COMP  "phase[0]"  SITE  "84";
+LOCATE  COMP  "phase[1]"  SITE  "85";
+LOCATE  COMP  "phase[2]"  SITE  "86";
+LOCATE  COMP  "phase[3]"  SITE  "87";
+LOCATE  COMP  "q3"  SITE  "70";
+LOCATE  COMP  "rddata"  SITE  "96";
+LOCATE  COMP  "rw"  SITE  "71";
+LOCATE  COMP  "select"  SITE  "78";
+LOCATE  COMP  "sense"  SITE  "97";
+LOCATE  COMP  "spi_clk"  SITE  "31";
+LOCATE  COMP  "spi_cs"  SITE  "27";
+LOCATE  COMP  "spi_miso"  SITE  "32";
+LOCATE  COMP  "spi_mosi"  SITE  "49";
+LOCATE  COMP  "wrdata"  SITE  "83";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Feb 22 10:56:42 2018
+
diff --git a/lattice/fpgatop/liron_fpgatop.dir/5_1.par b/lattice/fpgatop/liron_fpgatop.dir/5_1.par
new file mode 100644
index 0000000..3c2b095
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.dir/5_1.par
@@ -0,0 +1,200 @@
+
+Lattice Place and Route Report for Design "liron_fpgatop_map.ncd"
+Thu Feb 22 10:56:39 2018
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF liron_fpgatop_map.ncd liron_fpgatop.dir/5_1.ncd liron_fpgatop.prf
+Preference file: liron_fpgatop.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file liron_fpgatop_map.ncd.
+Design name: top
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)   52+4(JTAG)/108     52% used
+                  52+4(JTAG)/80      70% bonded
+
+   SLICE             58/640           9% used
+
+   GSR                1/1           100% used
+   EBR                4/7            57% used
+
+
+INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
+Number of Signals: 193
+Number of Connections: 582
+
+Pin Constraint Summary:
+   52 out of 52 pins locked (100% locked).
+
+The following 1 signal is selected to use the primary clock routing resources:
+    fclk_c (driver: fclk, clk load #: 27)
+
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    _devsel_c (driver: _devsel, clk load #: 8, sr load #: 0, ce load #: 0)
+
+Signal n440_c is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 2 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 43211.
+Finished Placer Phase 1.  REAL time: 3 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  43211
+Finished Placer Phase 2.  REAL time: 3 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 2 out of 8 (25%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Quadrants All (TL, TR, BL, BR) - Global Clocks:
+  PRIMARY "fclk_c" from comp "fclk" on CLK_PIN site "63 (PR5C)", clk load = 27
+  SECONDARY "_devsel_c" from comp "_devsel" on CLK_PIN site "34 (PB9A)", clk load = 8, ce load = 0, sr load = 0
+
+  PRIMARY  : 1 out of 8 (12%)
+  SECONDARY: 1 out of 8 (12%)
+
+Edge Clocks:
+  No edge clock selected.
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   52 + 4(JTAG) out of 108 (51.9%) PIO sites used.
+   52 + 4(JTAG) out of 80 (70.0%) bonded PIO sites used.
+   Number of PIO comps: 52; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 12 / 19 ( 63%) | 3.3V       | -         |
+| 1        | 20 / 21 ( 95%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 8 / 20 ( 40%)  | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 2 secs 
+
+Dumping design to file liron_fpgatop.dir/5_1.ncd.
+
+
+-----------------------------------------------------------------
+INFO - par: ASE feature is off due to non timing-driven settings.  
+-----------------------------------------------------------------
+
+0 connections routed; 582 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 4 secs 
+
+Start NBR router at 10:56:43 02/22/18
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 10:56:43 02/22/18
+
+Start NBR section for initial routing at 10:56:43 02/22/18
+Level 4, iteration 1
+19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 10:56:43 02/22/18
+Level 4, iteration 1
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+Level 4, iteration 2
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+
+Start NBR section for re-routing at 10:56:43 02/22/18
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+
+Start NBR section for post-routing at 10:56:43 02/22/18
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 3 secs 
+Total REAL time: 4 secs 
+Completely routed.
+End of route.  582 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file liron_fpgatop.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 
+PAR_SUMMARY::Timing score> = 
+PAR_SUMMARY::Worst  slack> = 
+PAR_SUMMARY::Timing score> = 
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 3 secs 
+Total REAL time to completion: 5 secs 
+
+par done!
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/lattice/fpgatop/liron_fpgatop.dir/5_1_par.asd b/lattice/fpgatop/liron_fpgatop.dir/5_1_par.asd
new file mode 100644
index 0000000..f3cf850
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.dir/5_1_par.asd
@@ -0,0 +1,34 @@
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 1;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = fclk_c;
+GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
+GLOBAL_PRIMARY_0_LOADNUM = 27;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 1;
+; Global secondary clock #0
+GLOBAL_SECONDARY_0_SIGNALNAME = _devsel_c;
+GLOBAL_SECONDARY_0_DRIVERTYPE = CLK_PIN;
+GLOBAL_SECONDARY_0_LOADNUM = 13;
+GLOBAL_SECONDARY_0_SIGTYPE = CLK;
+; I/O Bank 0 Usage
+BANK_0_USED = 12;
+BANK_0_AVAIL = 19;
+BANK_0_VCCIO = 3.3V;
+BANK_0_VREF1 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 20;
+BANK_1_AVAIL = 21;
+BANK_1_VCCIO = 3.3V;
+BANK_1_VREF1 = NA;
+; I/O Bank 2 Usage
+BANK_2_USED = 12;
+BANK_2_AVAIL = 20;
+BANK_2_VCCIO = 3.3V;
+BANK_2_VREF1 = NA;
+; I/O Bank 3 Usage
+BANK_3_USED = 8;
+BANK_3_AVAIL = 20;
+BANK_3_VCCIO = 3.3V;
+BANK_3_VREF1 = NA;
diff --git a/lattice/fpgatop/liron_fpgatop.dir/liron_fpgatop.par b/lattice/fpgatop/liron_fpgatop.dir/liron_fpgatop.par
new file mode 100644
index 0000000..48589df
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.dir/liron_fpgatop.par
@@ -0,0 +1,26 @@
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Feb 22 10:56:39 2018
+
+C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f liron_fpgatop.p2t
+liron_fpgatop_map.ncd liron_fpgatop.dir liron_fpgatop.prf -gui -msgset
+C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
+
+
+Preference file: liron_fpgatop.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -            -            -            -            05           Complete
+
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 5 secs 
+
+par done!
diff --git a/lattice/fpgatop/liron_fpgatop.drc b/lattice/fpgatop/liron_fpgatop.drc
new file mode 100644
index 0000000..7b5bf2b
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.drc
@@ -0,0 +1,2 @@
+INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
+DRC detected 0 errors and 0 warnings.
diff --git a/lattice/fpgatop/liron_fpgatop.jed b/lattice/fpgatop/liron_fpgatop.jed
new file mode 100644
index 0000000..4e554a8
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.jed
@@ -0,0 +1,2767 @@
+*
+NOTE Diamond (64-bit) 3.9.0.99.2 JEDEC Compatible Fuse File.*
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
+NOTE All Rights Reserved.*
+NOTE DATE CREATED:	Thu Feb 22 10:56:45 2018*
+NOTE DESIGN NAME:	liron_fpgatop.ncd*
+NOTE DEVICE NAME:	LCMXO2-1200HC-4TQFP100*
+NOTE JEDEC FILE STATUS:	Final   Version 1.94*
+NOTE PIN ASSIGNMENTS*
+NOTE PINS data[7] : 52 : inout*
+NOTE PINS data[6] : 51 : inout*
+NOTE PINS data[5] : 47 : inout*
+NOTE PINS data[4] : 39 : inout*
+NOTE PINS data[3] : 38 : inout*
+NOTE PINS data[2] : 37 : inout*
+NOTE PINS data[1] : 36 : inout*
+NOTE PINS data[0] : 35 : inout*
+NOTE PINS wrdata : 83 : out*
+NOTE PINS phase[3] : 87 : out*
+NOTE PINS phase[2] : 86 : out*
+NOTE PINS phase[1] : 85 : out*
+NOTE PINS phase[0] : 84 : out*
+NOTE PINS _wrreq : 88 : out*
+NOTE PINS _enbl1 : 82 : out*
+NOTE PINS _enbl2 : 99 : out*
+NOTE PINS select : 78 : out*
+NOTE PINS _en35 : 98 : out*
+NOTE PINS spi_clk : 31 : out*
+NOTE PINS spi_mosi : 49 : out*
+NOTE PINS spi_cs : 27 : out*
+NOTE PINS _en245 : 30 : out*
+NOTE PINS debugInfo[7] : 25 : out*
+NOTE PINS debugInfo[6] : 24 : out*
+NOTE PINS debugInfo[5] : 17 : out*
+NOTE PINS debugInfo[4] : 16 : out*
+NOTE PINS debugInfo[3] : 15 : out*
+NOTE PINS debugInfo[2] : 14 : out*
+NOTE PINS debugInfo[1] : 13 : out*
+NOTE PINS debugInfo[0] : 12 : out*
+NOTE PINS addr[11] : 69 : in*
+NOTE PINS addr[10] : 68 : in*
+NOTE PINS addr[9] : 67 : in*
+NOTE PINS addr[8] : 66 : in*
+NOTE PINS addr[7] : 65 : in*
+NOTE PINS addr[6] : 64 : in*
+NOTE PINS addr[5] : 62 : in*
+NOTE PINS addr[4] : 60 : in*
+NOTE PINS addr[3] : 59 : in*
+NOTE PINS addr[2] : 58 : in*
+NOTE PINS addr[1] : 57 : in*
+NOTE PINS addr[0] : 54 : in*
+NOTE PINS fclk : 63 : in*
+NOTE PINS q3 : 70 : in*
+NOTE PINS rw : 71 : in*
+NOTE PINS _iostrobe : 74 : in*
+NOTE PINS _iosel : 53 : in*
+NOTE PINS _devsel : 34 : in*
+NOTE PINS _reset : 75 : in*
+NOTE PINS sense : 97 : in*
+NOTE PINS rddata : 96 : in*
+NOTE PINS spi_miso : 32 : in*
+QP100*
+QF343936*
+G0*
+F0*
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diff --git a/lattice/fpgatop/liron_fpgatop.lpf b/lattice/fpgatop/liron_fpgatop.lpf
new file mode 100644
index 0000000..b9d3a29
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.lpf
@@ -0,0 +1,4 @@
+#BLOCK ASYNCPATHS;
+#BLOCK RESETPATHS;
+
+#FREQUENCY 1.000000 MHz;
diff --git a/lattice/fpgatop/liron_fpgatop.lsedata b/lattice/fpgatop/liron_fpgatop.lsedata
new file mode 100644
index 0000000..5d901a3
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.lsedata
@@ -0,0 +1,5083 @@
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diff --git a/lattice/fpgatop/liron_fpgatop.mrp b/lattice/fpgatop/liron_fpgatop.mrp
new file mode 100644
index 0000000..92969fe
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.mrp
@@ -0,0 +1,468 @@
+
+             Lattice Mapping Report File for Design Module 'top'
+
+
+Design Information
+------------------
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     liron_fpgatop.ngd -o liron_fpgatop_map.ncd -pr liron_fpgatop.prf -mp
+     liron_fpgatop.mrp -lpf
+     C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/liron_fpgatop.lpf -lpf
+     C:/Users/chamberlin/Documents/Liron/lattice/liron.lpf -c 0 -gui -msgset
+     C:/Users/chamberlin/Documents/Liron/lattice/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.9.0.99.2
+Mapped on:  02/22/18  10:56:38
+
+Design Summary
+--------------
+
+   Number of registers:     43 out of  1520 (3%)
+      PFU registers:           43 out of  1280 (3%)
+      PIO registers:            0 out of   240 (0%)
+   Number of SLICEs:        58 out of   640 (9%)
+      SLICEs as Logic/ROM:     58 out of   640 (9%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:          0 out of   640 (0%)
+   Number of LUT4s:        113 out of  1280 (9%)
+      Number used as logic LUTs:        113
+      Number used as distributed RAM:     0
+      Number used as ripple logic:        0
+      Number used as shift registers:     0
+   Number of PIO sites used: 52 + 4(JTAG) out of 80 (70%)
+   Number of block RAMs:  4 out of 7 (57%)
+   Number of GSRs:  1 out of 1 (100%)
+   EFB used :       No
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   POR :            On
+   Bandgap :        On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Number of PLLs:  0 out of 1 (0%)
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  2
+     Net fclk_c: 27 loads, 27 rising, 0 falling (Driver: PIO fclk )
+     Net _devsel_c: 8 loads, 0 rising, 8 falling (Driver: PIO _devsel )
+
+                                    Page 1
+
+
+
+
+Design:  top                                           Date:  02/22/18  10:56:38
+
+Design Summary (cont)
+---------------------
+   Number of Clock Enables:  17
+     Net q7: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_1: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_2: 1 loads, 1 LSLICEs
+     Net myIwm/fclk_c_enable_14: 5 loads, 5 LSLICEs
+     Net myIwm/fclk_c_enable_4: 1 loads, 1 LSLICEs
+     Net myIwm/fclk_c_enable_16: 2 loads, 2 LSLICEs
+     Net myIwm/fclk_c_enable_20: 3 loads, 3 LSLICEs
+     Net myIwm/fclk_c_enable_26: 4 loads, 4 LSLICEs
+     Net myIwm/_devsel_N_40_enable_3: 1 loads, 1 LSLICEs
+     Net myIwm/fclk_c_enable_30: 3 loads, 3 LSLICEs
+     Net myIwm/_devsel_N_40_enable_4: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_7: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_8: 1 loads, 1 LSLICEs
+     Net myIwm/fclk_c_enable_27: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_5: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_6: 1 loads, 1 LSLICEs
+     Net n438_c: 1 loads, 1 LSLICEs
+   Number of LSRs:  4
+     Net q7: 1 loads, 1 LSLICEs
+     Net myIwm/n302: 3 loads, 3 LSLICEs
+     Net histrobe: 1 loads, 1 LSLICEs
+     Net myIwm/n648: 2 loads, 2 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net q7: 22 loads
+     Net addr_c_0: 17 loads
+     Net addr_c_1: 13 loads
+     Net addr_c_2: 13 loads
+     Net addr_c_3: 13 loads
+     Net q6: 13 loads
+     Net writeBufferEmpty: 12 loads
+     Net myIwm/n142: 11 loads
+     Net myIwm/n1871: 11 loads
+     Net myIwm/bitTimer_3: 10 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+   No errors or warnings present.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| data[7]             | BIDIR     | LVCMOS33  |            |
+
+                                    Page 2
+
+
+
+
+Design:  top                                           Date:  02/22/18  10:56:38
+
+IO (PIO) Attributes (cont)
+--------------------------
++---------------------+-----------+-----------+------------+
+| data[6]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[5]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[4]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[3]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[2]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[1]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[0]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| wrdata              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| phase[3]            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| phase[2]            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| phase[1]            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| phase[0]            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _wrreq              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _enbl1              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _enbl2              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| select              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _en35               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| spi_clk             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| spi_mosi            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| spi_cs              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _en245              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[7]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[6]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[5]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[4]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[3]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[2]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[1]        | OUTPUT    | LVCMOS33  |            |
+
+                                    Page 3
+
+
+
+
+Design:  top                                           Date:  02/22/18  10:56:38
+
+IO (PIO) Attributes (cont)
+--------------------------
++---------------------+-----------+-----------+------------+
+| debugInfo[0]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[11]            | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[10]            | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[9]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[8]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[7]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[6]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[5]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[4]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[3]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[2]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[1]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[0]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| fclk                | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| q3                  | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| rw                  | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _iostrobe           | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _iosel              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _devsel             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _reset              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| sense               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| rddata              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| spi_miso            | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+
+Removed logic
+-------------
+
+Signal _devsel_N_40 was merged into signal _devsel_c
+Signal myAddrDecoder/_iosel_N_24 was merged into signal n438_c
+Signal myIwm/n1873 was merged into signal q7
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal n1904 undriven or does not drive anything - clipped.
+
+                                    Page 4
+
+
+
+
+Design:  top                                           Date:  02/22/18  10:56:38
+
+Removed logic (cont)
+--------------------
+Block i1779 was optimized away.
+Block myAddrDecoder/_iosel_I_0_1_lut was optimized away.
+Block myIwm/i673_1_lut_rep_31 was optimized away.
+Block i2 was optimized away.
+Block m0_lut was optimized away.
+
+Memory Usage
+------------
+
+    
+         
+    INFO: Design contains EBR with GSR enabled. The GSR is only applicable for
+         output registers except FIFO. 
+    /myROM:
+    EBRs: 4
+    RAM SLICEs: 0
+    Logic SLICEs: 0
+    PFU Registers: 0
+    -Contains EBR codeROM_0_0_3_0:  TYPE= DP8KC,  Width_A= 2,  Depth_A= 4096,
+         REGMODE_A= OUTREG,  REGMODE_B= NOREG,  RESETMODE= SYNC,
+         ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A= NORMAL,  WRITEMODE_B= NORMAL,
+         GSR= ENABLED,  MEM_INIT_FILE= rom-full-4k.mem,  MEM_LPC_FILE=
+         codeROM.lpc
+    -Contains EBR codeROM_0_0_1_2:  TYPE= DP8KC,  Width_A= 2,  Depth_A= 4096,
+         REGMODE_A= OUTREG,  REGMODE_B= NOREG,  RESETMODE= SYNC,
+         ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A= NORMAL,  WRITEMODE_B= NORMAL,
+         GSR= ENABLED,  MEM_INIT_FILE= rom-full-4k.mem,  MEM_LPC_FILE=
+         codeROM.lpc
+    -Contains EBR codeROM_0_0_0_3:  TYPE= DP8KC,  Width_A= 2,  Depth_A= 4096,
+         REGMODE_A= OUTREG,  REGMODE_B= NOREG,  RESETMODE= SYNC,
+         ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A= NORMAL,  WRITEMODE_B= NORMAL,
+         GSR= ENABLED,  MEM_INIT_FILE= rom-full-4k.mem,  MEM_LPC_FILE=
+         codeROM.lpc
+    -Contains EBR codeROM_0_0_2_1:  TYPE= DP8KC,  Width_A= 2,  Depth_A= 4096,
+         REGMODE_A= OUTREG,  REGMODE_B= NOREG,  RESETMODE= SYNC,
+         ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A= NORMAL,  WRITEMODE_B= NORMAL,
+         GSR= ENABLED,  MEM_INIT_FILE= rom-full-4k.mem,  MEM_LPC_FILE=
+         codeROM.lpc
+
+     
+
+ASIC Components
+---------------
+
+Instance Name: myROM/codeROM_0_0_3_0
+         Type: DP8KC
+Instance Name: myROM/codeROM_0_0_1_2
+         Type: DP8KC
+Instance Name: myROM/codeROM_0_0_0_3
+         Type: DP8KC
+Instance Name: myROM/codeROM_0_0_2_1
+         Type: DP8KC
+
+
+
+
+
+                                    Page 5
+
+
+
+
+Design:  top                                           Date:  02/22/18  10:56:38
+
+GSR Usage
+---------
+
+GSR Component:
+   The Global Set Reset (GSR) resource has been used to implement a global reset
+        of the design. The reset signal used for GSR control is 'n440_c'.
+        
+
+     GSR Property:
+   The design components with GSR property set to ENABLED will respond to global
+        set reset while the components with GSR property set to DISABLED will
+        not.
+        
+
+     Components with disabled GSR Property
+-------------------------------------
+
+     These components have the GSR property set to DISABLED. The components will
+     not respond to the reset signal 'n440_c' via the GSR component.
+
+     Type and number of components of the type: 
+   Register = 17 
+
+     Type and instance name of component: 
+   Register : myIwm/rddataSync_i0
+   Register : myIwm/shifter_i0_i0
+   Register : myIwm/bitTimer__i0
+   Register : myIwm/rddataSync_i1
+   Register : myIwm/shifter_i0_i1
+   Register : myIwm/shifter_i0_i2
+   Register : myIwm/shifter_i0_i3
+   Register : myIwm/shifter_i0_i4
+   Register : myIwm/shifter_i0_i5
+   Register : myIwm/shifter_i0_i6
+   Register : myIwm/shifter_i0_i7
+   Register : myIwm/bitTimer__i1
+   Register : myIwm/bitTimer__i2
+   Register : myIwm/bitTimer__i3
+   Register : myIwm/bitTimer__i4
+   Register : myIwm/bitTimer__i5
+   Register : myAddrDecoder/romExpansionActive_16
+
+     Components with synchronous local reset also reset by asynchronous GSR
+----------------------------------------------------------------------
+
+     These components have the GSR property set to ENABLED and the local reset
+     is synchronous. The components will respond to the synchronous local reset
+     and to the unrelated asynchronous reset signal 'n440_c' via the GSR
+     component.
+
+     Type and number of components of the type: 
+   Register = 4 
+   DP8KC = 4
+
+     Type and instance name of component: 
+   Register : myIwm/_underrun_125
+   Register : myIwm/clearBufferTimer_i0_i3
+   Register : myIwm/clearBufferTimer_i0_i2
+
+                                    Page 6
+
+
+
+
+Design:  top                                           Date:  02/22/18  10:56:38
+
+GSR Usage (cont)
+----------------
+   Register : myIwm/clearBufferTimer_i0_i1
+   DP8KC : myROM/codeROM_0_0_3_0
+   DP8KC : myROM/codeROM_0_0_1_2
+   DP8KC : myROM/codeROM_0_0_0_3
+   DP8KC : myROM/codeROM_0_0_2_1
+
+     EBR components with enabled GSR
+-------------------------------
+
+     These EBR components have the GSR property set to ENABLED. The components
+     will respond to the asynchronous reset signal 'n440_c' via the GSR
+     component.
+
+     Type and number of components of the type: 
+   DP8KC = 4
+
+     Type and instance name of component: 
+   DP8KC : myROM/codeROM_0_0_3_0
+   DP8KC : myROM/codeROM_0_0_1_2
+   DP8KC : myROM/codeROM_0_0_0_3
+   DP8KC : myROM/codeROM_0_0_2_1
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 38 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                    Page 7
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights
+     reserved.
diff --git a/lattice/fpgatop/liron_fpgatop.ncd b/lattice/fpgatop/liron_fpgatop.ncd
new file mode 100644
index 0000000..b5f7b06
Binary files /dev/null and b/lattice/fpgatop/liron_fpgatop.ncd differ
diff --git a/lattice/fpgatop/liron_fpgatop.ngd b/lattice/fpgatop/liron_fpgatop.ngd
new file mode 100644
index 0000000..a723171
Binary files /dev/null and b/lattice/fpgatop/liron_fpgatop.ngd differ
diff --git a/lattice/fpgatop/liron_fpgatop.p2t b/lattice/fpgatop/liron_fpgatop.p2t
new file mode 100644
index 0000000..945b9db
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.p2t
@@ -0,0 +1,9 @@
+-w
+-l 5
+-i 6
+-n 1
+-t 1
+-s 1
+-c 0
+-e 0
+-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF
diff --git a/lattice/fpgatop/liron_fpgatop.p3t b/lattice/fpgatop/liron_fpgatop.p3t
new file mode 100644
index 0000000..7ea156f
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.p3t
@@ -0,0 +1,5 @@
+-rem
+-distrce
+-log "liron_fpgatop.log"
+-o "liron_fpgatop.csv"
+-pr "liron_fpgatop.prf"
diff --git a/lattice/fpgatop/liron_fpgatop.pad b/lattice/fpgatop/liron_fpgatop.pad
new file mode 100644
index 0000000..c3d5eae
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.pad
@@ -0,0 +1,279 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Thu Feb 22 10:56:42 2018
+
+Pinout by Port Name:
++--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name    | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
++--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| _devsel      | 34/2     | LVCMOS33_IN   | PB9A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _en245       | 30/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _en35        | 98/0     | LVCMOS33_OUT  | PT9B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _enbl1       | 82/0     | LVCMOS33_OUT  | PT15C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _enbl2       | 99/0     | LVCMOS33_OUT  | PT9A  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _iosel       | 53/1     | LVCMOS33_IN   | PR9D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _iostrobe    | 74/1     | LVCMOS33_IN   | PR2B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _reset       | 75/1     | LVCMOS33_IN   | PR2A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _wrreq       | 88/0     | LVCMOS33_OUT  | PT12A |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| addr[0]      | 54/1     | LVCMOS33_IN   | PR9C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[10]     | 68/1     | LVCMOS33_IN   | PR4B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[11]     | 69/1     | LVCMOS33_IN   | PR4A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[1]      | 57/1     | LVCMOS33_IN   | PR9B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[2]      | 58/1     | LVCMOS33_IN   | PR9A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[3]      | 59/1     | LVCMOS33_IN   | PR8D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[4]      | 60/1     | LVCMOS33_IN   | PR8C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[5]      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[6]      | 64/1     | LVCMOS33_IN   | PR5B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[7]      | 65/1     | LVCMOS33_IN   | PR5A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[8]      | 66/1     | LVCMOS33_IN   | PR4D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[9]      | 67/1     | LVCMOS33_IN   | PR4C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| data[0]      | 35/2     | LVCMOS33_BIDI | PB9B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[1]      | 36/2     | LVCMOS33_BIDI | PB11C |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[2]      | 37/2     | LVCMOS33_BIDI | PB11D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[3]      | 38/2     | LVCMOS33_BIDI | PB11A |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[4]      | 39/2     | LVCMOS33_BIDI | PB11B |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[5]      | 47/2     | LVCMOS33_BIDI | PB18D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[6]      | 51/1     | LVCMOS33_BIDI | PR10D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[7]      | 52/1     | LVCMOS33_BIDI | PR10C |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| debugInfo[0] | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[1] | 13/3     | LVCMOS33_OUT  | PL5B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[2] | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[3] | 15/3     | LVCMOS33_OUT  | PL5D  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[4] | 16/3     | LVCMOS33_OUT  | PL8A  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[5] | 17/3     | LVCMOS33_OUT  | PL8B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[6] | 24/3     | LVCMOS33_OUT  | PL10C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[7] | 25/3     | LVCMOS33_OUT  | PL10D |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| fclk         | 63/1     | LVCMOS33_IN   | PR5C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| phase[0]     | 84/0     | LVCMOS33_OUT  | PT15A |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| phase[1]     | 85/0     | LVCMOS33_OUT  | PT12D |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| phase[2]     | 86/0     | LVCMOS33_OUT  | PT12C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| phase[3]     | 87/0     | LVCMOS33_OUT  | PT12B |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| q3           | 70/1     | LVCMOS33_IN   | PR3B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| rddata       | 96/0     | LVCMOS33_IN   | PT10B |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| rw           | 71/1     | LVCMOS33_IN   | PR3A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| select       | 78/0     | LVCMOS33_OUT  | PT16C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| sense        | 97/0     | LVCMOS33_IN   | PT10A |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| spi_clk      | 31/2     | LVCMOS33_OUT  | PB6C  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| spi_cs       | 27/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| spi_miso     | 32/2     | LVCMOS33_IN   | PB6D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| spi_mosi     | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| wrdata       | 83/0     | LVCMOS33_OUT  | PT15B |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
++--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      |     unused, PULL:DOWN |            |               | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      |     unused, PULL:DOWN |            |               | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      |     unused, PULL:DOWN |            |               | PL3A  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |               | PL3B  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |               | PL3C  |               |           |           |
+| 8/3      |     unused, PULL:DOWN |            |               | PL3D  |               |           |           |
+| 9/3      |     unused, PULL:DOWN |            |               | PL4A  |               |           |           |
+| 10/3     |     unused, PULL:DOWN |            |               | PL4B  |               |           |           |
+| 12/3     | debugInfo[0]          | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | debugInfo[1]          | LOCATED    | LVCMOS33_OUT  | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | debugInfo[2]          | LOCATED    | LVCMOS33_OUT  | PL5C  |               |           |           |
+| 15/3     | debugInfo[3]          | LOCATED    | LVCMOS33_OUT  | PL5D  |               |           |           |
+| 16/3     | debugInfo[4]          | LOCATED    | LVCMOS33_OUT  | PL8A  |               |           |           |
+| 17/3     | debugInfo[5]          | LOCATED    | LVCMOS33_OUT  | PL8B  |               |           |           |
+| 18/3     |     unused, PULL:DOWN |            |               | PL8C  |               |           |           |
+| 19/3     |     unused, PULL:DOWN |            |               | PL8D  |               |           |           |
+| 20/3     |     unused, PULL:DOWN |            |               | PL9A  | PCLKT3_0      |           |           |
+| 21/3     |     unused, PULL:DOWN |            |               | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | debugInfo[6]          | LOCATED    | LVCMOS33_OUT  | PL10C |               |           |           |
+| 25/3     | debugInfo[7]          | LOCATED    | LVCMOS33_OUT  | PL10D |               |           |           |
+| 27/2     | spi_cs                | LOCATED    | LVCMOS33_OUT  | PB4C  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |               | PB4D  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |               | PB6A  |               |           |           |
+| 30/2     | _en245                | LOCATED    | LVCMOS33_OUT  | PB6B  |               |           |           |
+| 31/2     | spi_clk               | LOCATED    | LVCMOS33_OUT  | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | spi_miso              | LOCATED    | LVCMOS33_IN   | PB6D  | SO/SPISO      |           |           |
+| 34/2     | _devsel               | LOCATED    | LVCMOS33_IN   | PB9A  | PCLKT2_0      |           |           |
+| 35/2     | data[0]               | LOCATED    | LVCMOS33_BIDI | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | data[1]               | LOCATED    | LVCMOS33_BIDI | PB11C |               |           |           |
+| 37/2     | data[2]               | LOCATED    | LVCMOS33_BIDI | PB11D |               |           |           |
+| 38/2     | data[3]               | LOCATED    | LVCMOS33_BIDI | PB11A | PCLKT2_1      |           |           |
+| 39/2     | data[4]               | LOCATED    | LVCMOS33_BIDI | PB11B | PCLKC2_1      |           |           |
+| 40/2     |     unused, PULL:DOWN |            |               | PB15A |               |           |           |
+| 41/2     |     unused, PULL:DOWN |            |               | PB15B |               |           |           |
+| 42/2     |     unused, PULL:DOWN |            |               | PB18A |               |           |           |
+| 43/2     |     unused, PULL:DOWN |            |               | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB18C |               |           |           |
+| 47/2     | data[5]               | LOCATED    | LVCMOS33_BIDI | PB18D |               |           |           |
+| 48/2     | Prohibited/Reserved   | PROHIBITED |               | PB20C | SN            |           |           |
+| 49/2     | spi_mosi              | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | data[6]               | LOCATED    | LVCMOS33_BIDI | PR10D | DQ1           |           |           |
+| 52/1     | data[7]               | LOCATED    | LVCMOS33_BIDI | PR10C | DQ1           |           |           |
+| 53/1     | _iosel                | LOCATED    | LVCMOS33_IN   | PR9D  | DQ1           |           |           |
+| 54/1     | addr[0]               | LOCATED    | LVCMOS33_IN   | PR9C  | DQ1           |           |           |
+| 57/1     | addr[1]               | LOCATED    | LVCMOS33_IN   | PR9B  | DQ1           |           |           |
+| 58/1     | addr[2]               | LOCATED    | LVCMOS33_IN   | PR9A  | DQ1           |           |           |
+| 59/1     | addr[3]               | LOCATED    | LVCMOS33_IN   | PR8D  | DQ1           |           |           |
+| 60/1     | addr[4]               | LOCATED    | LVCMOS33_IN   | PR8C  | DQ1           |           |           |
+| 61/1     | Prohibited/Reserved   | PROHIBITED |               | PR8A  | DQS1          |           |           |
+| 62/1     | addr[5]               | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     | fclk                  | LOCATED    | LVCMOS33_IN   | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | addr[6]               | LOCATED    | LVCMOS33_IN   | PR5B  | DQS0N         |           |           |
+| 65/1     | addr[7]               | LOCATED    | LVCMOS33_IN   | PR5A  | DQS0          |           |           |
+| 66/1     | addr[8]               | LOCATED    | LVCMOS33_IN   | PR4D  | DQ0           |           |           |
+| 67/1     | addr[9]               | LOCATED    | LVCMOS33_IN   | PR4C  | DQ0           |           |           |
+| 68/1     | addr[10]              | LOCATED    | LVCMOS33_IN   | PR4B  | DQ0           |           |           |
+| 69/1     | addr[11]              | LOCATED    | LVCMOS33_IN   | PR4A  | DQ0           |           |           |
+| 70/1     | q3                    | LOCATED    | LVCMOS33_IN   | PR3B  | DQ0           |           |           |
+| 71/1     | rw                    | LOCATED    | LVCMOS33_IN   | PR3A  | DQ0           |           |           |
+| 74/1     | _iostrobe             | LOCATED    | LVCMOS33_IN   | PR2B  | DQ0           |           |           |
+| 75/1     | _reset                | LOCATED    | LVCMOS33_IN   | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
+| 78/0     | select                | LOCATED    | LVCMOS33_OUT  | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
+| 82/0     | _enbl1                | LOCATED    | LVCMOS33_OUT  | PT15C | JTAGENB       |           |           |
+| 83/0     | wrdata                | LOCATED    | LVCMOS33_OUT  | PT15B |               |           |           |
+| 84/0     | phase[0]              | LOCATED    | LVCMOS33_OUT  | PT15A |               |           |           |
+| 85/0     | phase[1]              | LOCATED    | LVCMOS33_OUT  | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | phase[2]              | LOCATED    | LVCMOS33_OUT  | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | phase[3]              | LOCATED    | LVCMOS33_OUT  | PT12B | PCLKC0_1      |           |           |
+| 88/0     | _wrreq                | LOCATED    | LVCMOS33_OUT  | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | rddata                | LOCATED    | LVCMOS33_IN   | PT10B |               |           |           |
+| 97/0     | sense                 | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
+| 98/0     | _en35                 | LOCATED    | LVCMOS33_OUT  | PT9B  |               |           |           |
+| 99/0     | _enbl2                | LOCATED    | LVCMOS33_OUT  | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "_devsel"  SITE  "34";
+LOCATE  COMP  "_en245"  SITE  "30";
+LOCATE  COMP  "_en35"  SITE  "98";
+LOCATE  COMP  "_enbl1"  SITE  "82";
+LOCATE  COMP  "_enbl2"  SITE  "99";
+LOCATE  COMP  "_iosel"  SITE  "53";
+LOCATE  COMP  "_iostrobe"  SITE  "74";
+LOCATE  COMP  "_reset"  SITE  "75";
+LOCATE  COMP  "_wrreq"  SITE  "88";
+LOCATE  COMP  "addr[0]"  SITE  "54";
+LOCATE  COMP  "addr[10]"  SITE  "68";
+LOCATE  COMP  "addr[11]"  SITE  "69";
+LOCATE  COMP  "addr[1]"  SITE  "57";
+LOCATE  COMP  "addr[2]"  SITE  "58";
+LOCATE  COMP  "addr[3]"  SITE  "59";
+LOCATE  COMP  "addr[4]"  SITE  "60";
+LOCATE  COMP  "addr[5]"  SITE  "62";
+LOCATE  COMP  "addr[6]"  SITE  "64";
+LOCATE  COMP  "addr[7]"  SITE  "65";
+LOCATE  COMP  "addr[8]"  SITE  "66";
+LOCATE  COMP  "addr[9]"  SITE  "67";
+LOCATE  COMP  "data[0]"  SITE  "35";
+LOCATE  COMP  "data[1]"  SITE  "36";
+LOCATE  COMP  "data[2]"  SITE  "37";
+LOCATE  COMP  "data[3]"  SITE  "38";
+LOCATE  COMP  "data[4]"  SITE  "39";
+LOCATE  COMP  "data[5]"  SITE  "47";
+LOCATE  COMP  "data[6]"  SITE  "51";
+LOCATE  COMP  "data[7]"  SITE  "52";
+LOCATE  COMP  "debugInfo[0]"  SITE  "12";
+LOCATE  COMP  "debugInfo[1]"  SITE  "13";
+LOCATE  COMP  "debugInfo[2]"  SITE  "14";
+LOCATE  COMP  "debugInfo[3]"  SITE  "15";
+LOCATE  COMP  "debugInfo[4]"  SITE  "16";
+LOCATE  COMP  "debugInfo[5]"  SITE  "17";
+LOCATE  COMP  "debugInfo[6]"  SITE  "24";
+LOCATE  COMP  "debugInfo[7]"  SITE  "25";
+LOCATE  COMP  "fclk"  SITE  "63";
+LOCATE  COMP  "phase[0]"  SITE  "84";
+LOCATE  COMP  "phase[1]"  SITE  "85";
+LOCATE  COMP  "phase[2]"  SITE  "86";
+LOCATE  COMP  "phase[3]"  SITE  "87";
+LOCATE  COMP  "q3"  SITE  "70";
+LOCATE  COMP  "rddata"  SITE  "96";
+LOCATE  COMP  "rw"  SITE  "71";
+LOCATE  COMP  "select"  SITE  "78";
+LOCATE  COMP  "sense"  SITE  "97";
+LOCATE  COMP  "spi_clk"  SITE  "31";
+LOCATE  COMP  "spi_cs"  SITE  "27";
+LOCATE  COMP  "spi_miso"  SITE  "32";
+LOCATE  COMP  "spi_mosi"  SITE  "49";
+LOCATE  COMP  "wrdata"  SITE  "83";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Feb 22 10:56:42 2018
+
diff --git a/lattice/fpgatop/liron_fpgatop.par b/lattice/fpgatop/liron_fpgatop.par
new file mode 100644
index 0000000..689eaf4
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.par
@@ -0,0 +1,226 @@
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Feb 22 10:56:39 2018
+
+C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f liron_fpgatop.p2t
+liron_fpgatop_map.ncd liron_fpgatop.dir liron_fpgatop.prf -gui -msgset
+C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
+
+
+Preference file: liron_fpgatop.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -            -            -            -            05           Complete
+
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 5 secs 
+
+par done!
+
+Lattice Place and Route Report for Design "liron_fpgatop_map.ncd"
+Thu Feb 22 10:56:39 2018
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF liron_fpgatop_map.ncd liron_fpgatop.dir/5_1.ncd liron_fpgatop.prf
+Preference file: liron_fpgatop.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file liron_fpgatop_map.ncd.
+Design name: top
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)   52+4(JTAG)/108     52% used
+                  52+4(JTAG)/80      70% bonded
+
+   SLICE             58/640           9% used
+
+   GSR                1/1           100% used
+   EBR                4/7            57% used
+
+
+INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
+Number of Signals: 193
+Number of Connections: 582
+
+Pin Constraint Summary:
+   52 out of 52 pins locked (100% locked).
+
+The following 1 signal is selected to use the primary clock routing resources:
+    fclk_c (driver: fclk, clk load #: 27)
+
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    _devsel_c (driver: _devsel, clk load #: 8, sr load #: 0, ce load #: 0)
+
+Signal n440_c is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 2 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 43211.
+Finished Placer Phase 1.  REAL time: 3 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  43211
+Finished Placer Phase 2.  REAL time: 3 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 2 out of 8 (25%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Quadrants All (TL, TR, BL, BR) - Global Clocks:
+  PRIMARY "fclk_c" from comp "fclk" on CLK_PIN site "63 (PR5C)", clk load = 27
+  SECONDARY "_devsel_c" from comp "_devsel" on CLK_PIN site "34 (PB9A)", clk load = 8, ce load = 0, sr load = 0
+
+  PRIMARY  : 1 out of 8 (12%)
+  SECONDARY: 1 out of 8 (12%)
+
+Edge Clocks:
+  No edge clock selected.
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   52 + 4(JTAG) out of 108 (51.9%) PIO sites used.
+   52 + 4(JTAG) out of 80 (70.0%) bonded PIO sites used.
+   Number of PIO comps: 52; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 12 / 19 ( 63%) | 3.3V       | -         |
+| 1        | 20 / 21 ( 95%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 8 / 20 ( 40%)  | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 2 secs 
+
+Dumping design to file liron_fpgatop.dir/5_1.ncd.
+
+
+-----------------------------------------------------------------
+INFO - par: ASE feature is off due to non timing-driven settings.  
+-----------------------------------------------------------------
+
+0 connections routed; 582 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 4 secs 
+
+Start NBR router at 10:56:43 02/22/18
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 10:56:43 02/22/18
+
+Start NBR section for initial routing at 10:56:43 02/22/18
+Level 4, iteration 1
+19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 10:56:43 02/22/18
+Level 4, iteration 1
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+Level 4, iteration 2
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+
+Start NBR section for re-routing at 10:56:43 02/22/18
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+
+Start NBR section for post-routing at 10:56:43 02/22/18
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 3 secs 
+Total REAL time: 4 secs 
+Completely routed.
+End of route.  582 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file liron_fpgatop.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 
+PAR_SUMMARY::Timing score> = 
+PAR_SUMMARY::Worst  slack> = 
+PAR_SUMMARY::Timing score> = 
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 3 secs 
+Total REAL time to completion: 5 secs 
+
+par done!
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/lattice/fpgatop/liron_fpgatop.prf b/lattice/fpgatop/liron_fpgatop.prf
new file mode 100644
index 0000000..5e5979d
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.prf
@@ -0,0 +1,67 @@
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.9.0.99.2 -- WARNING: Map write only section -- Thu Feb 22 10:56:39 2018
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "data[7]" SITE "52" ;
+LOCATE COMP "data[6]" SITE "51" ;
+LOCATE COMP "data[5]" SITE "47" ;
+LOCATE COMP "data[4]" SITE "39" ;
+LOCATE COMP "data[3]" SITE "38" ;
+LOCATE COMP "data[2]" SITE "37" ;
+LOCATE COMP "data[1]" SITE "36" ;
+LOCATE COMP "data[0]" SITE "35" ;
+LOCATE COMP "wrdata" SITE "83" ;
+LOCATE COMP "phase[3]" SITE "87" ;
+LOCATE COMP "phase[2]" SITE "86" ;
+LOCATE COMP "phase[1]" SITE "85" ;
+LOCATE COMP "phase[0]" SITE "84" ;
+LOCATE COMP "_wrreq" SITE "88" ;
+LOCATE COMP "_enbl1" SITE "82" ;
+LOCATE COMP "_enbl2" SITE "99" ;
+LOCATE COMP "select" SITE "78" ;
+LOCATE COMP "_en35" SITE "98" ;
+LOCATE COMP "spi_clk" SITE "31" ;
+LOCATE COMP "spi_mosi" SITE "49" ;
+LOCATE COMP "spi_cs" SITE "27" ;
+LOCATE COMP "_en245" SITE "30" ;
+LOCATE COMP "debugInfo[7]" SITE "25" ;
+LOCATE COMP "debugInfo[6]" SITE "24" ;
+LOCATE COMP "debugInfo[5]" SITE "17" ;
+LOCATE COMP "debugInfo[4]" SITE "16" ;
+LOCATE COMP "debugInfo[3]" SITE "15" ;
+LOCATE COMP "debugInfo[2]" SITE "14" ;
+LOCATE COMP "debugInfo[1]" SITE "13" ;
+LOCATE COMP "debugInfo[0]" SITE "12" ;
+LOCATE COMP "addr[11]" SITE "69" ;
+LOCATE COMP "addr[10]" SITE "68" ;
+LOCATE COMP "addr[9]" SITE "67" ;
+LOCATE COMP "addr[8]" SITE "66" ;
+LOCATE COMP "addr[7]" SITE "65" ;
+LOCATE COMP "addr[6]" SITE "64" ;
+LOCATE COMP "addr[5]" SITE "62" ;
+LOCATE COMP "addr[4]" SITE "60" ;
+LOCATE COMP "addr[3]" SITE "59" ;
+LOCATE COMP "addr[2]" SITE "58" ;
+LOCATE COMP "addr[1]" SITE "57" ;
+LOCATE COMP "addr[0]" SITE "54" ;
+LOCATE COMP "fclk" SITE "63" ;
+LOCATE COMP "q3" SITE "70" ;
+LOCATE COMP "rw" SITE "71" ;
+LOCATE COMP "_iostrobe" SITE "74" ;
+LOCATE COMP "_iosel" SITE "53" ;
+LOCATE COMP "_devsel" SITE "34" ;
+LOCATE COMP "_reset" SITE "75" ;
+LOCATE COMP "sense" SITE "97" ;
+LOCATE COMP "rddata" SITE "96" ;
+LOCATE COMP "spi_miso" SITE "32" ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+PROHIBIT SITE "48" ;
+PROHIBIT SITE "61" ;
+COMMERCIAL ;
+
+// No timing preferences found. TRCE invokes auto-generation of timing preferences
+// Section Autogen
+FREQUENCY NET "fclk_c" 149.993 MHz ;
+// End Section Autogen
diff --git a/lattice/fpgatop/liron_fpgatop.pt b/lattice/fpgatop/liron_fpgatop.pt
new file mode 100644
index 0000000..e5e32de
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.pt
@@ -0,0 +1,10 @@
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 4
+-sphld m
diff --git a/lattice/fpgatop/liron_fpgatop.t2b b/lattice/fpgatop/liron_fpgatop.t2b
new file mode 100644
index 0000000..5e2ea9d
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.t2b
@@ -0,0 +1,5 @@
+
+
+-g RamCfg:Reset
+
+-path "C:/Users/chamberlin/Documents/Liron/lattice"  
diff --git a/lattice/fpgatop/liron_fpgatop.twr b/lattice/fpgatop/liron_fpgatop.twr
new file mode 100644
index 0000000..588e1df
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop.twr
@@ -0,0 +1,1163 @@
+
+Loading design for application trce from file liron_fpgatop.ncd.
+Design name: top
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.9.0.99.2
+Thu Feb 22 10:56:44 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o liron_fpgatop.twr -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf 
+Design file:     liron_fpgatop.ncd
+Preference file: liron_fpgatop.prf
+Device,speed:    LCMXO2-1200HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "fclk_c" 149.993000 MHz ;
+            565 items scored, 124 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.923ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i2  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i1
+
+   Delay:               9.308ns  (26.1% logic, 73.9% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.308ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_19 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.923ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.308   (26.1% logic, 73.9% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13A.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.923ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i6  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i5
+
+   Delay:               9.308ns  (26.1% logic, 73.9% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.308ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_21 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.923ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13D.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.308   (26.1% logic, 73.9% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13D.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.923ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i4  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i3
+
+   Delay:               9.308ns  (26.1% logic, 73.9% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.308ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_20 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.923ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13B.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.308   (26.1% logic, 73.9% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13B.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.909ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i0  (to fclk_c +)
+
+   Delay:               9.294ns  (26.2% logic, 73.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.294ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_18 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.909ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.091      R8C13B.F1 to      R9C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.294   (26.2% logic, 73.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R9C13A.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.909ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i7  (to fclk_c +)
+
+   Delay:               9.294ns  (26.2% logic, 73.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.294ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_22 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.909ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.091      R8C13B.F1 to      R9C13C.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.294   (26.2% logic, 73.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R9C13C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.207ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i4  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i3
+
+   Delay:               8.592ns  (28.3% logic, 71.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.592ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_20 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.207ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13B.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.592   (28.3% logic, 71.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13B.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.207ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i6  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i5
+
+   Delay:               8.592ns  (28.3% logic, 71.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.592ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_21 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.207ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13D.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.592   (28.3% logic, 71.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13D.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.207ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i2  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i1
+
+   Delay:               8.592ns  (28.3% logic, 71.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.592ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_19 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.207ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.592   (28.3% logic, 71.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13A.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.193ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i7  (to fclk_c +)
+
+   Delay:               8.578ns  (28.4% logic, 71.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.578ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_22 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.193ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.091      R8C13B.F1 to      R9C13C.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.578   (28.4% logic, 71.6% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R9C13C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.193ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i0  (to fclk_c +)
+
+   Delay:               8.578ns  (28.4% logic, 71.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.578ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_18 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.193ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.091      R8C13B.F1 to      R9C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.578   (28.4% logic, 71.6% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R9C13A.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 104.275MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "fclk_c" 149.993000 MHz ; |  149.993 MHz|  104.275 MHz|   5 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+1 preference(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+myIwm/fclk_c_enable_14                  |       5|      58|     46.77%
+                                        |        |        |
+myIwm/n1862                             |       4|      56|     45.16%
+                                        |        |        |
+myIwm/n163                              |       8|      53|     42.74%
+                                        |        |        |
+myIwm/n10                               |       3|      51|     41.13%
+                                        |        |        |
+myIwm/bitTimer_2                        |       8|      43|     34.68%
+                                        |        |        |
+myIwm/n87                               |       3|      39|     31.45%
+                                        |        |        |
+myIwm/n9                                |       1|      33|     26.61%
+                                        |        |        |
+myIwm/bitTimer_1                        |       9|      33|     26.61%
+                                        |        |        |
+myIwm/n4                                |       1|      24|     19.35%
+                                        |        |        |
+myIwm/n514                              |       7|      23|     18.55%
+                                        |        |        |
+myIwm/n1875                             |       2|      17|     13.71%
+                                        |        |        |
+myIwm/n1854                             |       2|      17|     13.71%
+                                        |        |        |
+myIwm/bitTimer_5                        |       8|      17|     13.71%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 2 clocks:
+
+Clock Domain: fclk_c   Source: fclk.PAD   Loads: 27
+   Covered under: FREQUENCY NET "fclk_c" 149.993000 MHz ;
+
+   Data transfers from:
+   Clock Domain: _devsel_c   Source: _devsel.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: _devsel_c   Source: _devsel.PAD   Loads: 13
+   No transfer within this clock domain is found
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 124  Score: 116771
+Cumulative negative slack: 116771
+
+Constraints cover 565 paths, 1 nets, and 301 connections (51.72% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.9.0.99.2
+Thu Feb 22 10:56:44 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o liron_fpgatop.twr -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf 
+Design file:     liron_fpgatop.ncd
+Preference file: liron_fpgatop.prf
+Device,speed:    LCMXO2-1200HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "fclk_c" 149.993000 MHz ;
+            565 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.307ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/rddataSync_i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/rddataSync_i1  (to fclk_c +)
+
+   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.288ns physical path delay myIwm/SLICE_42 to myIwm/SLICE_42 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.307ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_42 to myIwm/SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C12A.CLK to      R8C12A.Q0 myIwm/SLICE_42 (from fclk_c)
+ROUTE         4     0.155      R8C12A.Q0 to      R8C12A.M1 myIwm/rddataSync_0 (to fclk_c)
+                  --------
+                    0.288   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C12A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C12A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/wrdata_130  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/wrdata_130  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_29 to myIwm/SLICE_29 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_29 to myIwm/SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C14B.CLK to      R8C14B.Q0 myIwm/SLICE_29 (from fclk_c)
+ROUTE         2     0.132      R8C14B.Q0 to      R8C14B.A0 wrdata_c
+CTOF_DEL    ---     0.101      R8C14B.A0 to      R8C14B.F0 myIwm/SLICE_29
+ROUTE         1     0.000      R8C14B.F0 to     R8C14B.DI0 myIwm/wrdata_N_115 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C14B.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C14B.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i3  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i3  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_14 to myIwm/SLICE_14 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_14 to myIwm/SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11D.CLK to      R8C11D.Q0 myIwm/SLICE_14 (from fclk_c)
+ROUTE         4     0.132      R8C11D.Q0 to      R8C11D.A0 myIwm/clearBufferTimer_3
+CTOF_DEL    ---     0.101      R8C11D.A0 to      R8C11D.F0 myIwm/SLICE_14
+ROUTE         1     0.000      R8C11D.F0 to     R8C11D.DI0 myIwm/n69 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11D.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11D.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i2  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_13 to myIwm/SLICE_13 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_13 to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11C.CLK to      R8C11C.Q1 myIwm/SLICE_13 (from fclk_c)
+ROUTE         5     0.132      R8C11C.Q1 to      R8C11C.A1 myIwm/clearBufferTimer_2
+CTOF_DEL    ---     0.101      R8C11C.A1 to      R8C11C.F1 myIwm/SLICE_13
+ROUTE         1     0.000      R8C11C.F1 to     R8C11C.DI1 myIwm/n70 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_223__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_223__i2  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_5 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_5 to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14B.CLK to     R10C14B.Q0 myIwm/SLICE_5 (from fclk_c)
+ROUTE         2     0.132     R10C14B.Q0 to     R10C14B.A0 myIwm/bitCounter_2
+CTOF_DEL    ---     0.101     R10C14B.A0 to     R10C14B.F0 myIwm/SLICE_5
+ROUTE         1     0.000     R10C14B.F0 to    R10C14B.DI0 myIwm/n18_adj_148 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14B.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14B.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i1  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_13 to myIwm/SLICE_13 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_13 to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11C.CLK to      R8C11C.Q0 myIwm/SLICE_13 (from fclk_c)
+ROUTE         6     0.132      R8C11C.Q0 to      R8C11C.A0 myIwm/clearBufferTimer_1
+CTOF_DEL    ---     0.101      R8C11C.A0 to      R8C11C.F0 myIwm/SLICE_13
+ROUTE         1     0.000      R8C11C.F0 to     R8C11C.DI0 myIwm/n71 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_223__i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_223__i1  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_4 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_4 to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q1 myIwm/SLICE_4 (from fclk_c)
+ROUTE         3     0.132     R10C14C.Q1 to     R10C14C.A1 myIwm/bitCounter_1
+CTOF_DEL    ---     0.101     R10C14C.A1 to     R10C14C.F1 myIwm/SLICE_4
+ROUTE         1     0.000     R10C14C.F1 to    R10C14C.DI1 myIwm/n19_adj_149 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_223__i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_223__i0  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_4 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_4 to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q0 myIwm/SLICE_4 (from fclk_c)
+ROUTE         4     0.132     R10C14C.Q0 to     R10C14C.A0 myIwm/bitCounter_0
+CTOF_DEL    ---     0.101     R10C14C.A0 to     R10C14C.F0 myIwm/SLICE_4
+ROUTE         1     0.000     R10C14C.F0 to    R10C14C.DI0 myIwm/n20 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.380ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i0  (to fclk_c +)
+
+   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.367ns physical path delay myIwm/SLICE_12 to myIwm/SLICE_12 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.380ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_12 to myIwm/SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11A.CLK to      R8C11A.Q0 myIwm/SLICE_12 (from fclk_c)
+ROUTE         7     0.133      R8C11A.Q0 to      R8C11A.A0 myIwm/clearBufferTimer_0
+CTOF_DEL    ---     0.101      R8C11A.A0 to      R8C11A.F0 myIwm/SLICE_12
+ROUTE         1     0.000      R8C11A.F0 to     R8C11A.DI0 myIwm/clearBufferTimer_3_N_70_0 (to fclk_c)
+                  --------
+                    0.367   (63.8% logic, 36.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.381ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitTimer__i0  (to fclk_c +)
+
+   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.368ns physical path delay myIwm/SLICE_6 to myIwm/SLICE_6 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.381ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_6 to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C14A.CLK to      R8C14A.Q0 myIwm/SLICE_6 (from fclk_c)
+ROUTE         8     0.134      R8C14A.Q0 to      R8C14A.A0 myIwm/bitTimer_0
+CTOF_DEL    ---     0.101      R8C14A.A0 to      R8C14A.F0 myIwm/SLICE_6
+ROUTE         1     0.000      R8C14A.F0 to     R8C14A.DI0 myIwm/n1733 (to fclk_c)
+                  --------
+                    0.368   (63.6% logic, 36.4% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C14A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C14A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "fclk_c" 149.993000 MHz ; |     0.000 ns|     0.307 ns|   1  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 2 clocks:
+
+Clock Domain: fclk_c   Source: fclk.PAD   Loads: 27
+   Covered under: FREQUENCY NET "fclk_c" 149.993000 MHz ;
+
+   Data transfers from:
+   Clock Domain: _devsel_c   Source: _devsel.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: _devsel_c   Source: _devsel.PAD   Loads: 13
+   No transfer within this clock domain is found
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 565 paths, 1 nets, and 301 connections (51.72% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 124 (setup), 0 (hold)
+Score: 116771 (setup), 0 (hold)
+Cumulative negative slack: 116771 (116771+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/lattice/fpgatop/liron_fpgatop_bgn.html b/lattice/fpgatop/liron_fpgatop_bgn.html
new file mode 100644
index 0000000..65457b7
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_bgn.html
@@ -0,0 +1,148 @@
+
+Bitgen Report
+
+
+
BITGEN: Bitstream Generator Diamond (64-bit) 3.9.0.99.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Command: bitgen -g RamCfg:Reset -path C:/Users/chamberlin/Documents/Liron/lattice -w -jedec -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf 
+
+Loading design for application Bitgen from file liron_fpgatop.ncd.
+Design name: top
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from liron_fpgatop.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.94.
+ 
+Saving bit stream in "liron_fpgatop.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        511 Pages (128*511 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
+Initialized UFM Pages:                     0 Page.
+ 
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

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diff --git a/lattice/fpgatop/liron_fpgatop_lattice.synproj b/lattice/fpgatop/liron_fpgatop_lattice.synproj
new file mode 100644
index 0000000..a2b3a30
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_lattice.synproj
@@ -0,0 +1,44 @@
+-a "MachXO2"
+-d LCMXO2-1200HC
+-t TQFP100
+-s 4
+
+-optimization_goal Balanced
+-bram_utilization 100
+-ramstyle Auto
+-romstyle auto
+-dsp_utilization 100
+-use_dsp 1
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr Auto
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-loop_limit 1950
+
+
+
+-use_io_insertion 1
+-resolve_mixed_drivers 0
+-use_io_reg auto
+
+
+-lpf 1
+-p "C:/Users/chamberlin/Documents/Liron/lattice"
+-ver "C:/Users/chamberlin/Documents/Liron/lattice/top.v"
+"C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v"
+"C:/Users/chamberlin/Documents/Liron/lattice/iwm.v"
+"C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v"
+-top top
+
+
+-p "C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data" "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop" "C:/Users/chamberlin/Documents/Liron/lattice"
+
+-ngd "liron_fpgatop.ngd"
+
diff --git a/lattice/fpgatop/liron_fpgatop_map.asd b/lattice/fpgatop/liron_fpgatop_map.asd
new file mode 100644
index 0000000..fdc8f63
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_map.asd
@@ -0,0 +1,69 @@
+[ActiveSupport MAP]
+Device = LCMXO2-1200HC;
+Package = TQFP100;
+Performance = 4;
+LUTS_avail = 1280;
+LUTS_used = 113;
+FF_avail = 1360;
+FF_used = 43;
+INPUT_LVCMOS33 = 22;
+OUTPUT_LVCMOS33 = 22;
+BIDI_LVCMOS33 = 8;
+IO_avail = 80;
+IO_used = 52;
+EBR_avail = 7;
+EBR_used = 4;
+; Begin EBR Section
+Instance_Name = myROM/codeROM_0_0_3_0;
+Type = DP8KC;
+Width_A = 2;
+Depth_A = 4096;
+REGMODE_A = OUTREG;
+REGMODE_B = NOREG;
+RESETMODE = SYNC;
+ASYNC_RESET_RELEASE = SYNC;
+WRITEMODE_A = NORMAL;
+WRITEMODE_B = NORMAL;
+GSR = ENABLED;
+MEM_INIT_FILE = rom-full-4k.mem;
+MEM_LPC_FILE = codeROM.lpc;
+Instance_Name = myROM/codeROM_0_0_1_2;
+Type = DP8KC;
+Width_A = 2;
+Depth_A = 4096;
+REGMODE_A = OUTREG;
+REGMODE_B = NOREG;
+RESETMODE = SYNC;
+ASYNC_RESET_RELEASE = SYNC;
+WRITEMODE_A = NORMAL;
+WRITEMODE_B = NORMAL;
+GSR = ENABLED;
+MEM_INIT_FILE = rom-full-4k.mem;
+MEM_LPC_FILE = codeROM.lpc;
+Instance_Name = myROM/codeROM_0_0_0_3;
+Type = DP8KC;
+Width_A = 2;
+Depth_A = 4096;
+REGMODE_A = OUTREG;
+REGMODE_B = NOREG;
+RESETMODE = SYNC;
+ASYNC_RESET_RELEASE = SYNC;
+WRITEMODE_A = NORMAL;
+WRITEMODE_B = NORMAL;
+GSR = ENABLED;
+MEM_INIT_FILE = rom-full-4k.mem;
+MEM_LPC_FILE = codeROM.lpc;
+Instance_Name = myROM/codeROM_0_0_2_1;
+Type = DP8KC;
+Width_A = 2;
+Depth_A = 4096;
+REGMODE_A = OUTREG;
+REGMODE_B = NOREG;
+RESETMODE = SYNC;
+ASYNC_RESET_RELEASE = SYNC;
+WRITEMODE_A = NORMAL;
+WRITEMODE_B = NORMAL;
+GSR = ENABLED;
+MEM_INIT_FILE = rom-full-4k.mem;
+MEM_LPC_FILE = codeROM.lpc;
+; End EBR Section
diff --git a/lattice/fpgatop/liron_fpgatop_map.cam b/lattice/fpgatop/liron_fpgatop_map.cam
new file mode 100644
index 0000000..0b813ba
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_map.cam
@@ -0,0 +1,68 @@
+[ START MERGED ]
+_devsel_N_40 _devsel_c
+myIwm/n1873 q7
+myAddrDecoder/_iosel_N_24 n438_c
+[ END MERGED ]
+[ START CLIPPED ]
+VCC_net
+n1904
+[ END CLIPPED ]
+[ START DESIGN PREFS ]
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.9.0.99.2 -- WARNING: Map write only section -- Thu Feb 22 10:56:39 2018
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "data[7]" SITE "52" ;
+LOCATE COMP "data[6]" SITE "51" ;
+LOCATE COMP "data[5]" SITE "47" ;
+LOCATE COMP "data[4]" SITE "39" ;
+LOCATE COMP "data[3]" SITE "38" ;
+LOCATE COMP "data[2]" SITE "37" ;
+LOCATE COMP "data[1]" SITE "36" ;
+LOCATE COMP "data[0]" SITE "35" ;
+LOCATE COMP "wrdata" SITE "83" ;
+LOCATE COMP "phase[3]" SITE "87" ;
+LOCATE COMP "phase[2]" SITE "86" ;
+LOCATE COMP "phase[1]" SITE "85" ;
+LOCATE COMP "phase[0]" SITE "84" ;
+LOCATE COMP "_wrreq" SITE "88" ;
+LOCATE COMP "_enbl1" SITE "82" ;
+LOCATE COMP "_enbl2" SITE "99" ;
+LOCATE COMP "select" SITE "78" ;
+LOCATE COMP "_en35" SITE "98" ;
+LOCATE COMP "spi_clk" SITE "31" ;
+LOCATE COMP "spi_mosi" SITE "49" ;
+LOCATE COMP "spi_cs" SITE "27" ;
+LOCATE COMP "_en245" SITE "30" ;
+LOCATE COMP "debugInfo[7]" SITE "25" ;
+LOCATE COMP "debugInfo[6]" SITE "24" ;
+LOCATE COMP "debugInfo[5]" SITE "17" ;
+LOCATE COMP "debugInfo[4]" SITE "16" ;
+LOCATE COMP "debugInfo[3]" SITE "15" ;
+LOCATE COMP "debugInfo[2]" SITE "14" ;
+LOCATE COMP "debugInfo[1]" SITE "13" ;
+LOCATE COMP "debugInfo[0]" SITE "12" ;
+LOCATE COMP "addr[11]" SITE "69" ;
+LOCATE COMP "addr[10]" SITE "68" ;
+LOCATE COMP "addr[9]" SITE "67" ;
+LOCATE COMP "addr[8]" SITE "66" ;
+LOCATE COMP "addr[7]" SITE "65" ;
+LOCATE COMP "addr[6]" SITE "64" ;
+LOCATE COMP "addr[5]" SITE "62" ;
+LOCATE COMP "addr[4]" SITE "60" ;
+LOCATE COMP "addr[3]" SITE "59" ;
+LOCATE COMP "addr[2]" SITE "58" ;
+LOCATE COMP "addr[1]" SITE "57" ;
+LOCATE COMP "addr[0]" SITE "54" ;
+LOCATE COMP "fclk" SITE "63" ;
+LOCATE COMP "q3" SITE "70" ;
+LOCATE COMP "rw" SITE "71" ;
+LOCATE COMP "_iostrobe" SITE "74" ;
+LOCATE COMP "_iosel" SITE "53" ;
+LOCATE COMP "_devsel" SITE "34" ;
+LOCATE COMP "_reset" SITE "75" ;
+LOCATE COMP "sense" SITE "97" ;
+LOCATE COMP "rddata" SITE "96" ;
+LOCATE COMP "spi_miso" SITE "32" ;
+SCHEMATIC END ;
+[ END DESIGN PREFS ]
diff --git a/lattice/fpgatop/liron_fpgatop_map.hrr b/lattice/fpgatop/liron_fpgatop_map.hrr
new file mode 100644
index 0000000..2452477
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_map.hrr
@@ -0,0 +1,37 @@
+---------------------------------------------------
+Report for cell top
+   Instance path: top
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      58.00        100.0
+                                  LUT4	     113.00        100.0
+                                 IOBUF	         52        100.0
+                                PFUREG	         43        100.0
+                                   EBR	          4        100.0
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+                                   iwm	          1        92.2
+                               codeROM	          1         0.0
+                           addrDecoder	          1         2.9
+---------------------------------------------------
+Report for cell iwm
+   Instance path: top/myIwm
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      53.50        92.2
+                                  LUT4	     102.00        90.3
+                                PFUREG	         42        97.7
+---------------------------------------------------
+Report for cell codeROM
+   Instance path: top/myROM
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                   EBR	          4        100.0
+---------------------------------------------------
+Report for cell addrDecoder
+   Instance path: top/myAddrDecoder
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	       1.67         2.9
+                                  LUT4	       3.00         2.7
+                                PFUREG	          1         2.3
diff --git a/lattice/fpgatop/liron_fpgatop_map.ncd b/lattice/fpgatop/liron_fpgatop_map.ncd
new file mode 100644
index 0000000..1e06246
Binary files /dev/null and b/lattice/fpgatop/liron_fpgatop_map.ncd differ
diff --git a/lattice/fpgatop/liron_fpgatop_mrp.html b/lattice/fpgatop/liron_fpgatop_mrp.html
new file mode 100644
index 0000000..c2142f1
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_mrp.html
@@ -0,0 +1,489 @@
+
+Project Summary
+
+
+

+             Lattice Mapping Report File for Design Module 'top'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     liron_fpgatop.ngd -o liron_fpgatop_map.ncd -pr liron_fpgatop.prf -mp
+     liron_fpgatop.mrp -lpf
+     C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/liron_fpgatop.lpf -lpf
+     C:/Users/chamberlin/Documents/Liron/lattice/liron.lpf -c 0 -gui -msgset
+     C:/Users/chamberlin/Documents/Liron/lattice/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.9.0.99.2
+Mapped on:  02/22/18  10:56:38
+
+
+Design Summary
+   Number of registers:     43 out of  1520 (3%)
+      PFU registers:           43 out of  1280 (3%)
+      PIO registers:            0 out of   240 (0%)
+   Number of SLICEs:        58 out of   640 (9%)
+      SLICEs as Logic/ROM:     58 out of   640 (9%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:          0 out of   640 (0%)
+   Number of LUT4s:        113 out of  1280 (9%)
+      Number used as logic LUTs:        113
+      Number used as distributed RAM:     0
+      Number used as ripple logic:        0
+      Number used as shift registers:     0
+   Number of PIO sites used: 52 + 4(JTAG) out of 80 (70%)
+   Number of block RAMs:  4 out of 7 (57%)
+   Number of GSRs:  1 out of 1 (100%)
+   EFB used :       No
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   POR :            On
+   Bandgap :        On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Number of PLLs:  0 out of 1 (0%)
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  2
+     Net fclk_c: 27 loads, 27 rising, 0 falling (Driver: PIO fclk )
+     Net _devsel_c: 8 loads, 0 rising, 8 falling (Driver: PIO _devsel )
+
+   Number of Clock Enables:  17
+     Net q7: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_1: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_2: 1 loads, 1 LSLICEs
+     Net myIwm/fclk_c_enable_14: 5 loads, 5 LSLICEs
+     Net myIwm/fclk_c_enable_4: 1 loads, 1 LSLICEs
+     Net myIwm/fclk_c_enable_16: 2 loads, 2 LSLICEs
+     Net myIwm/fclk_c_enable_20: 3 loads, 3 LSLICEs
+     Net myIwm/fclk_c_enable_26: 4 loads, 4 LSLICEs
+     Net myIwm/_devsel_N_40_enable_3: 1 loads, 1 LSLICEs
+     Net myIwm/fclk_c_enable_30: 3 loads, 3 LSLICEs
+     Net myIwm/_devsel_N_40_enable_4: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_7: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_8: 1 loads, 1 LSLICEs
+     Net myIwm/fclk_c_enable_27: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_5: 1 loads, 1 LSLICEs
+     Net myIwm/_devsel_N_40_enable_6: 1 loads, 1 LSLICEs
+     Net n438_c: 1 loads, 1 LSLICEs
+   Number of LSRs:  4
+     Net q7: 1 loads, 1 LSLICEs
+     Net myIwm/n302: 3 loads, 3 LSLICEs
+     Net histrobe: 1 loads, 1 LSLICEs
+     Net myIwm/n648: 2 loads, 2 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net q7: 22 loads
+     Net addr_c_0: 17 loads
+     Net addr_c_1: 13 loads
+     Net addr_c_2: 13 loads
+     Net addr_c_3: 13 loads
+     Net q6: 13 loads
+     Net writeBufferEmpty: 12 loads
+     Net myIwm/n142: 11 loads
+     Net myIwm/n1871: 11 loads
+     Net myIwm/bitTimer_3: 10 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| data[7]             | BIDIR     | LVCMOS33  |            |
+
++---------------------+-----------+-----------+------------+
+| data[6]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[5]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[4]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[3]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[2]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[1]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| data[0]             | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| wrdata              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| phase[3]            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| phase[2]            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| phase[1]            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| phase[0]            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _wrreq              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _enbl1              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _enbl2              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| select              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _en35               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| spi_clk             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| spi_mosi            | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| spi_cs              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _en245              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[7]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[6]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[5]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[4]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[3]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[2]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| debugInfo[1]        | OUTPUT    | LVCMOS33  |            |
+
++---------------------+-----------+-----------+------------+
+| debugInfo[0]        | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[11]            | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[10]            | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[9]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[8]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[7]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[6]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[5]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[4]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[3]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[2]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[1]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| addr[0]             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| fclk                | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| q3                  | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| rw                  | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _iostrobe           | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _iosel              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _devsel             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| _reset              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| sense               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| rddata              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| spi_miso            | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Signal _devsel_N_40 was merged into signal _devsel_c
+Signal myAddrDecoder/_iosel_N_24 was merged into signal n438_c
+Signal myIwm/n1873 was merged into signal q7
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal n1904 undriven or does not drive anything - clipped.
+
+Block i1779 was optimized away.
+Block myAddrDecoder/_iosel_I_0_1_lut was optimized away.
+Block myIwm/i673_1_lut_rep_31 was optimized away.
+Block i2 was optimized away.
+Block m0_lut was optimized away.
+
+
+
+Memory Usage
+
+    
+         
+    INFO: Design contains EBR with GSR enabled. The GSR is only applicable for
+         output registers except FIFO. 
+    /myROM:
+    EBRs: 4
+    RAM SLICEs: 0
+    Logic SLICEs: 0
+    PFU Registers: 0
+    -Contains EBR codeROM_0_0_3_0:  TYPE= DP8KC,  Width_A= 2,  Depth_A= 4096,
+         REGMODE_A= OUTREG,  REGMODE_B= NOREG,  RESETMODE= SYNC,
+         ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A= NORMAL,  WRITEMODE_B= NORMAL,
+         GSR= ENABLED,  MEM_INIT_FILE= rom-full-4k.mem,  MEM_LPC_FILE=
+         codeROM.lpc
+    -Contains EBR codeROM_0_0_1_2:  TYPE= DP8KC,  Width_A= 2,  Depth_A= 4096,
+         REGMODE_A= OUTREG,  REGMODE_B= NOREG,  RESETMODE= SYNC,
+         ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A= NORMAL,  WRITEMODE_B= NORMAL,
+         GSR= ENABLED,  MEM_INIT_FILE= rom-full-4k.mem,  MEM_LPC_FILE=
+         codeROM.lpc
+    -Contains EBR codeROM_0_0_0_3:  TYPE= DP8KC,  Width_A= 2,  Depth_A= 4096,
+         REGMODE_A= OUTREG,  REGMODE_B= NOREG,  RESETMODE= SYNC,
+         ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A= NORMAL,  WRITEMODE_B= NORMAL,
+         GSR= ENABLED,  MEM_INIT_FILE= rom-full-4k.mem,  MEM_LPC_FILE=
+         codeROM.lpc
+    -Contains EBR codeROM_0_0_2_1:  TYPE= DP8KC,  Width_A= 2,  Depth_A= 4096,
+         REGMODE_A= OUTREG,  REGMODE_B= NOREG,  RESETMODE= SYNC,
+         ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A= NORMAL,  WRITEMODE_B= NORMAL,
+         GSR= ENABLED,  MEM_INIT_FILE= rom-full-4k.mem,  MEM_LPC_FILE=
+         codeROM.lpc
+
+     
+
+
+
+ASIC Components
+---------------
+
+Instance Name: myROM/codeROM_0_0_3_0
+         Type: DP8KC
+Instance Name: myROM/codeROM_0_0_1_2
+         Type: DP8KC
+Instance Name: myROM/codeROM_0_0_0_3
+         Type: DP8KC
+Instance Name: myROM/codeROM_0_0_2_1
+         Type: DP8KC
+
+
+
+
+
+
+
+GSR Usage
+---------
+
+GSR Component:
+   The Global Set Reset (GSR) resource has been used to implement a global reset
+        of the design. The reset signal used for GSR control is 'n440_c'.
+        
+
+     GSR Property:
+   The design components with GSR property set to ENABLED will respond to global
+        set reset while the components with GSR property set to DISABLED will
+        not.
+        
+
+     Components with disabled GSR Property
+-------------------------------------
+
+     These components have the GSR property set to DISABLED. The components will
+     not respond to the reset signal 'n440_c' via the GSR component.
+
+     Type and number of components of the type: 
+   Register = 17 
+
+     Type and instance name of component: 
+   Register : myIwm/rddataSync_i0
+   Register : myIwm/shifter_i0_i0
+   Register : myIwm/bitTimer__i0
+   Register : myIwm/rddataSync_i1
+   Register : myIwm/shifter_i0_i1
+   Register : myIwm/shifter_i0_i2
+   Register : myIwm/shifter_i0_i3
+   Register : myIwm/shifter_i0_i4
+   Register : myIwm/shifter_i0_i5
+   Register : myIwm/shifter_i0_i6
+   Register : myIwm/shifter_i0_i7
+   Register : myIwm/bitTimer__i1
+   Register : myIwm/bitTimer__i2
+   Register : myIwm/bitTimer__i3
+   Register : myIwm/bitTimer__i4
+   Register : myIwm/bitTimer__i5
+   Register : myAddrDecoder/romExpansionActive_16
+
+     Components with synchronous local reset also reset by asynchronous GSR
+----------------------------------------------------------------------
+
+     These components have the GSR property set to ENABLED and the local reset
+     is synchronous. The components will respond to the synchronous local reset
+     and to the unrelated asynchronous reset signal 'n440_c' via the GSR
+     component.
+
+     Type and number of components of the type: 
+   Register = 4 
+   DP8KC = 4
+
+     Type and instance name of component: 
+   Register : myIwm/_underrun_125
+   Register : myIwm/clearBufferTimer_i0_i3
+   Register : myIwm/clearBufferTimer_i0_i2
+
+   Register : myIwm/clearBufferTimer_i0_i1
+   DP8KC : myROM/codeROM_0_0_3_0
+   DP8KC : myROM/codeROM_0_0_1_2
+   DP8KC : myROM/codeROM_0_0_0_3
+   DP8KC : myROM/codeROM_0_0_2_1
+
+     EBR components with enabled GSR
+-------------------------------
+
+     These EBR components have the GSR property set to ENABLED. The components
+     will respond to the asynchronous reset signal 'n440_c' via the GSR
+     component.
+
+     Type and number of components of the type: 
+   DP8KC = 4
+
+     Type and instance name of component: 
+   DP8KC : myROM/codeROM_0_0_3_0
+   DP8KC : myROM/codeROM_0_0_1_2
+   DP8KC : myROM/codeROM_0_0_0_3
+   DP8KC : myROM/codeROM_0_0_2_1
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 38 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+
diff --git a/lattice/fpgatop/liron_fpgatop_pad.html b/lattice/fpgatop/liron_fpgatop_pad.html
new file mode 100644
index 0000000..3e8c456
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_pad.html
@@ -0,0 +1,344 @@
+
+PAD Specification File
+
+
+
PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Thu Feb 22 10:56:42 2018
+
+Pinout by Port Name:
++--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name    | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
++--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| _devsel      | 34/2     | LVCMOS33_IN   | PB9A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _en245       | 30/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _en35        | 98/0     | LVCMOS33_OUT  | PT9B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _enbl1       | 82/0     | LVCMOS33_OUT  | PT15C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _enbl2       | 99/0     | LVCMOS33_OUT  | PT9A  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| _iosel       | 53/1     | LVCMOS33_IN   | PR9D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _iostrobe    | 74/1     | LVCMOS33_IN   | PR2B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _reset       | 75/1     | LVCMOS33_IN   | PR2A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| _wrreq       | 88/0     | LVCMOS33_OUT  | PT12A |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| addr[0]      | 54/1     | LVCMOS33_IN   | PR9C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[10]     | 68/1     | LVCMOS33_IN   | PR4B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[11]     | 69/1     | LVCMOS33_IN   | PR4A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[1]      | 57/1     | LVCMOS33_IN   | PR9B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[2]      | 58/1     | LVCMOS33_IN   | PR9A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[3]      | 59/1     | LVCMOS33_IN   | PR8D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[4]      | 60/1     | LVCMOS33_IN   | PR8C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[5]      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[6]      | 64/1     | LVCMOS33_IN   | PR5B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[7]      | 65/1     | LVCMOS33_IN   | PR5A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[8]      | 66/1     | LVCMOS33_IN   | PR4D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| addr[9]      | 67/1     | LVCMOS33_IN   | PR4C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| data[0]      | 35/2     | LVCMOS33_BIDI | PB9B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[1]      | 36/2     | LVCMOS33_BIDI | PB11C |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[2]      | 37/2     | LVCMOS33_BIDI | PB11D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[3]      | 38/2     | LVCMOS33_BIDI | PB11A |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[4]      | 39/2     | LVCMOS33_BIDI | PB11B |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[5]      | 47/2     | LVCMOS33_BIDI | PB18D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[6]      | 51/1     | LVCMOS33_BIDI | PR10D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| data[7]      | 52/1     | LVCMOS33_BIDI | PR10C |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| debugInfo[0] | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[1] | 13/3     | LVCMOS33_OUT  | PL5B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[2] | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[3] | 15/3     | LVCMOS33_OUT  | PL5D  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[4] | 16/3     | LVCMOS33_OUT  | PL8A  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[5] | 17/3     | LVCMOS33_OUT  | PL8B  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[6] | 24/3     | LVCMOS33_OUT  | PL10C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| debugInfo[7] | 25/3     | LVCMOS33_OUT  | PL10D |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| fclk         | 63/1     | LVCMOS33_IN   | PR5C  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| phase[0]     | 84/0     | LVCMOS33_OUT  | PT15A |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| phase[1]     | 85/0     | LVCMOS33_OUT  | PT12D |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| phase[2]     | 86/0     | LVCMOS33_OUT  | PT12C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| phase[3]     | 87/0     | LVCMOS33_OUT  | PT12B |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| q3           | 70/1     | LVCMOS33_IN   | PR3B  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| rddata       | 96/0     | LVCMOS33_IN   | PT10B |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| rw           | 71/1     | LVCMOS33_IN   | PR3A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| select       | 78/0     | LVCMOS33_OUT  | PT16C |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| sense        | 97/0     | LVCMOS33_IN   | PT10A |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| spi_clk      | 31/2     | LVCMOS33_OUT  | PB6C  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| spi_cs       | 27/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| spi_miso     | 32/2     | LVCMOS33_IN   | PB6D  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
+| spi_mosi     | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
+| wrdata       | 83/0     | LVCMOS33_OUT  | PT15B |           |           | DRIVE:8mA PULL:KEEPER SLEW:SLOW                            |
++--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      |     unused, PULL:DOWN |            |               | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      |     unused, PULL:DOWN |            |               | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      |     unused, PULL:DOWN |            |               | PL3A  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |               | PL3B  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |               | PL3C  |               |           |           |
+| 8/3      |     unused, PULL:DOWN |            |               | PL3D  |               |           |           |
+| 9/3      |     unused, PULL:DOWN |            |               | PL4A  |               |           |           |
+| 10/3     |     unused, PULL:DOWN |            |               | PL4B  |               |           |           |
+| 12/3     | debugInfo[0]          | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | debugInfo[1]          | LOCATED    | LVCMOS33_OUT  | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | debugInfo[2]          | LOCATED    | LVCMOS33_OUT  | PL5C  |               |           |           |
+| 15/3     | debugInfo[3]          | LOCATED    | LVCMOS33_OUT  | PL5D  |               |           |           |
+| 16/3     | debugInfo[4]          | LOCATED    | LVCMOS33_OUT  | PL8A  |               |           |           |
+| 17/3     | debugInfo[5]          | LOCATED    | LVCMOS33_OUT  | PL8B  |               |           |           |
+| 18/3     |     unused, PULL:DOWN |            |               | PL8C  |               |           |           |
+| 19/3     |     unused, PULL:DOWN |            |               | PL8D  |               |           |           |
+| 20/3     |     unused, PULL:DOWN |            |               | PL9A  | PCLKT3_0      |           |           |
+| 21/3     |     unused, PULL:DOWN |            |               | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | debugInfo[6]          | LOCATED    | LVCMOS33_OUT  | PL10C |               |           |           |
+| 25/3     | debugInfo[7]          | LOCATED    | LVCMOS33_OUT  | PL10D |               |           |           |
+| 27/2     | spi_cs                | LOCATED    | LVCMOS33_OUT  | PB4C  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |               | PB4D  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |               | PB6A  |               |           |           |
+| 30/2     | _en245                | LOCATED    | LVCMOS33_OUT  | PB6B  |               |           |           |
+| 31/2     | spi_clk               | LOCATED    | LVCMOS33_OUT  | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | spi_miso              | LOCATED    | LVCMOS33_IN   | PB6D  | SO/SPISO      |           |           |
+| 34/2     | _devsel               | LOCATED    | LVCMOS33_IN   | PB9A  | PCLKT2_0      |           |           |
+| 35/2     | data[0]               | LOCATED    | LVCMOS33_BIDI | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | data[1]               | LOCATED    | LVCMOS33_BIDI | PB11C |               |           |           |
+| 37/2     | data[2]               | LOCATED    | LVCMOS33_BIDI | PB11D |               |           |           |
+| 38/2     | data[3]               | LOCATED    | LVCMOS33_BIDI | PB11A | PCLKT2_1      |           |           |
+| 39/2     | data[4]               | LOCATED    | LVCMOS33_BIDI | PB11B | PCLKC2_1      |           |           |
+| 40/2     |     unused, PULL:DOWN |            |               | PB15A |               |           |           |
+| 41/2     |     unused, PULL:DOWN |            |               | PB15B |               |           |           |
+| 42/2     |     unused, PULL:DOWN |            |               | PB18A |               |           |           |
+| 43/2     |     unused, PULL:DOWN |            |               | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB18C |               |           |           |
+| 47/2     | data[5]               | LOCATED    | LVCMOS33_BIDI | PB18D |               |           |           |
+| 48/2     | Prohibited/Reserved   | PROHIBITED |               | PB20C | SN            |           |           |
+| 49/2     | spi_mosi              | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | data[6]               | LOCATED    | LVCMOS33_BIDI | PR10D | DQ1           |           |           |
+| 52/1     | data[7]               | LOCATED    | LVCMOS33_BIDI | PR10C | DQ1           |           |           |
+| 53/1     | _iosel                | LOCATED    | LVCMOS33_IN   | PR9D  | DQ1           |           |           |
+| 54/1     | addr[0]               | LOCATED    | LVCMOS33_IN   | PR9C  | DQ1           |           |           |
+| 57/1     | addr[1]               | LOCATED    | LVCMOS33_IN   | PR9B  | DQ1           |           |           |
+| 58/1     | addr[2]               | LOCATED    | LVCMOS33_IN   | PR9A  | DQ1           |           |           |
+| 59/1     | addr[3]               | LOCATED    | LVCMOS33_IN   | PR8D  | DQ1           |           |           |
+| 60/1     | addr[4]               | LOCATED    | LVCMOS33_IN   | PR8C  | DQ1           |           |           |
+| 61/1     | Prohibited/Reserved   | PROHIBITED |               | PR8A  | DQS1          |           |           |
+| 62/1     | addr[5]               | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     | fclk                  | LOCATED    | LVCMOS33_IN   | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | addr[6]               | LOCATED    | LVCMOS33_IN   | PR5B  | DQS0N         |           |           |
+| 65/1     | addr[7]               | LOCATED    | LVCMOS33_IN   | PR5A  | DQS0          |           |           |
+| 66/1     | addr[8]               | LOCATED    | LVCMOS33_IN   | PR4D  | DQ0           |           |           |
+| 67/1     | addr[9]               | LOCATED    | LVCMOS33_IN   | PR4C  | DQ0           |           |           |
+| 68/1     | addr[10]              | LOCATED    | LVCMOS33_IN   | PR4B  | DQ0           |           |           |
+| 69/1     | addr[11]              | LOCATED    | LVCMOS33_IN   | PR4A  | DQ0           |           |           |
+| 70/1     | q3                    | LOCATED    | LVCMOS33_IN   | PR3B  | DQ0           |           |           |
+| 71/1     | rw                    | LOCATED    | LVCMOS33_IN   | PR3A  | DQ0           |           |           |
+| 74/1     | _iostrobe             | LOCATED    | LVCMOS33_IN   | PR2B  | DQ0           |           |           |
+| 75/1     | _reset                | LOCATED    | LVCMOS33_IN   | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
+| 78/0     | select                | LOCATED    | LVCMOS33_OUT  | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
+| 82/0     | _enbl1                | LOCATED    | LVCMOS33_OUT  | PT15C | JTAGENB       |           |           |
+| 83/0     | wrdata                | LOCATED    | LVCMOS33_OUT  | PT15B |               |           |           |
+| 84/0     | phase[0]              | LOCATED    | LVCMOS33_OUT  | PT15A |               |           |           |
+| 85/0     | phase[1]              | LOCATED    | LVCMOS33_OUT  | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | phase[2]              | LOCATED    | LVCMOS33_OUT  | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | phase[3]              | LOCATED    | LVCMOS33_OUT  | PT12B | PCLKC0_1      |           |           |
+| 88/0     | _wrreq                | LOCATED    | LVCMOS33_OUT  | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | rddata                | LOCATED    | LVCMOS33_IN   | PT10B |               |           |           |
+| 97/0     | sense                 | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
+| 98/0     | _en35                 | LOCATED    | LVCMOS33_OUT  | PT9B  |               |           |           |
+| 99/0     | _enbl2                | LOCATED    | LVCMOS33_OUT  | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "_devsel"  SITE  "34";
+LOCATE  COMP  "_en245"  SITE  "30";
+LOCATE  COMP  "_en35"  SITE  "98";
+LOCATE  COMP  "_enbl1"  SITE  "82";
+LOCATE  COMP  "_enbl2"  SITE  "99";
+LOCATE  COMP  "_iosel"  SITE  "53";
+LOCATE  COMP  "_iostrobe"  SITE  "74";
+LOCATE  COMP  "_reset"  SITE  "75";
+LOCATE  COMP  "_wrreq"  SITE  "88";
+LOCATE  COMP  "addr[0]"  SITE  "54";
+LOCATE  COMP  "addr[10]"  SITE  "68";
+LOCATE  COMP  "addr[11]"  SITE  "69";
+LOCATE  COMP  "addr[1]"  SITE  "57";
+LOCATE  COMP  "addr[2]"  SITE  "58";
+LOCATE  COMP  "addr[3]"  SITE  "59";
+LOCATE  COMP  "addr[4]"  SITE  "60";
+LOCATE  COMP  "addr[5]"  SITE  "62";
+LOCATE  COMP  "addr[6]"  SITE  "64";
+LOCATE  COMP  "addr[7]"  SITE  "65";
+LOCATE  COMP  "addr[8]"  SITE  "66";
+LOCATE  COMP  "addr[9]"  SITE  "67";
+LOCATE  COMP  "data[0]"  SITE  "35";
+LOCATE  COMP  "data[1]"  SITE  "36";
+LOCATE  COMP  "data[2]"  SITE  "37";
+LOCATE  COMP  "data[3]"  SITE  "38";
+LOCATE  COMP  "data[4]"  SITE  "39";
+LOCATE  COMP  "data[5]"  SITE  "47";
+LOCATE  COMP  "data[6]"  SITE  "51";
+LOCATE  COMP  "data[7]"  SITE  "52";
+LOCATE  COMP  "debugInfo[0]"  SITE  "12";
+LOCATE  COMP  "debugInfo[1]"  SITE  "13";
+LOCATE  COMP  "debugInfo[2]"  SITE  "14";
+LOCATE  COMP  "debugInfo[3]"  SITE  "15";
+LOCATE  COMP  "debugInfo[4]"  SITE  "16";
+LOCATE  COMP  "debugInfo[5]"  SITE  "17";
+LOCATE  COMP  "debugInfo[6]"  SITE  "24";
+LOCATE  COMP  "debugInfo[7]"  SITE  "25";
+LOCATE  COMP  "fclk"  SITE  "63";
+LOCATE  COMP  "phase[0]"  SITE  "84";
+LOCATE  COMP  "phase[1]"  SITE  "85";
+LOCATE  COMP  "phase[2]"  SITE  "86";
+LOCATE  COMP  "phase[3]"  SITE  "87";
+LOCATE  COMP  "q3"  SITE  "70";
+LOCATE  COMP  "rddata"  SITE  "96";
+LOCATE  COMP  "rw"  SITE  "71";
+LOCATE  COMP  "select"  SITE  "78";
+LOCATE  COMP  "sense"  SITE  "97";
+LOCATE  COMP  "spi_clk"  SITE  "31";
+LOCATE  COMP  "spi_cs"  SITE  "27";
+LOCATE  COMP  "spi_miso"  SITE  "32";
+LOCATE  COMP  "spi_mosi"  SITE  "49";
+LOCATE  COMP  "wrdata"  SITE  "83";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Feb 22 10:56:42 2018
+
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diff --git a/lattice/fpgatop/liron_fpgatop_par.html b/lattice/fpgatop/liron_fpgatop_par.html
new file mode 100644
index 0000000..24c5dc9
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_par.html
@@ -0,0 +1,295 @@
+
+Place & Route Report
+
+
+
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Feb 22 10:56:39 2018
+
+C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f liron_fpgatop.p2t
+liron_fpgatop_map.ncd liron_fpgatop.dir liron_fpgatop.prf -gui -msgset
+C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
+
+
+Preference file: liron_fpgatop.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -            -            -            -            05           Complete
+
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 5 secs 
+
+par done!
+
+Lattice Place and Route Report for Design "liron_fpgatop_map.ncd"
+Thu Feb 22 10:56:39 2018
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF liron_fpgatop_map.ncd liron_fpgatop.dir/5_1.ncd liron_fpgatop.prf
+Preference file: liron_fpgatop.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file liron_fpgatop_map.ncd.
+Design name: top
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   52+4(JTAG)/108     52% used
+                  52+4(JTAG)/80      70% bonded
+
+   SLICE             58/640           9% used
+
+   GSR                1/1           100% used
+   EBR                4/7            57% used
+
+
+INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
+Number of Signals: 193
+Number of Connections: 582
+
+Pin Constraint Summary:
+   52 out of 52 pins locked (100% locked).
+
+The following 1 signal is selected to use the primary clock routing resources:
+    fclk_c (driver: fclk, clk load #: 27)
+
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    _devsel_c (driver: _devsel, clk load #: 8, sr load #: 0, ce load #: 0)
+
+Signal n440_c is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 2 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 43211.
+Finished Placer Phase 1.  REAL time: 3 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  43211
+Finished Placer Phase 2.  REAL time: 3 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 2 out of 8 (25%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Quadrants All (TL, TR, BL, BR) - Global Clocks:
+  PRIMARY "fclk_c" from comp "fclk" on CLK_PIN site "63 (PR5C)", clk load = 27
+  SECONDARY "_devsel_c" from comp "_devsel" on CLK_PIN site "34 (PB9A)", clk load = 8, ce load = 0, sr load = 0
+
+  PRIMARY  : 1 out of 8 (12%)
+  SECONDARY: 1 out of 8 (12%)
+
+Edge Clocks:
+  No edge clock selected.
+
+
+
+
+I/O Usage Summary (final):
+   52 + 4(JTAG) out of 108 (51.9%) PIO sites used.
+   52 + 4(JTAG) out of 80 (70.0%) bonded PIO sites used.
+   Number of PIO comps: 52; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 12 / 19 ( 63%) | 3.3V       | -         |
+| 1        | 20 / 21 ( 95%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 8 / 20 ( 40%)  | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 2 secs 
+
+Dumping design to file liron_fpgatop.dir/5_1.ncd.
+
+
+-----------------------------------------------------------------
+INFO - par: ASE feature is off due to non timing-driven settings.  
+-----------------------------------------------------------------
+
+0 connections routed; 582 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 4 secs 
+
+Start NBR router at 10:56:43 02/22/18
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 10:56:43 02/22/18
+
+Start NBR section for initial routing at 10:56:43 02/22/18
+Level 4, iteration 1
+19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 10:56:43 02/22/18
+Level 4, iteration 1
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+Level 4, iteration 2
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+
+Start NBR section for re-routing at 10:56:43 02/22/18
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs 
+
+Start NBR section for post-routing at 10:56:43 02/22/18
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : <n/a>
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 3 secs 
+Total REAL time: 4 secs 
+Completely routed.
+End of route.  582 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file liron_fpgatop.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = <n/a>
+PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
+PAR_SUMMARY::Worst  slack<hold /<ns>> = <n/a>
+PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 3 secs 
+Total REAL time to completion: 5 secs 
+
+par done!
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
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diff --git a/lattice/fpgatop/liron_fpgatop_summary.html b/lattice/fpgatop/liron_fpgatop_summary.html
new file mode 100644
index 0000000..6b505fa
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_summary.html
@@ -0,0 +1,83 @@
+
+Project Summary
+
+
+

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liron project summary
Module Name:lironSynthesis:Lattice LSE
Implementation Name:fpgatopStrategy Name:Strategy1
Last Process:JEDEC FileState:Passed
Target Device:LCMXO2-1200HC-4TG100CDevice Family:MachXO2
Device Type:LCMXO2-1200HCPackage Type:TQFP100
Performance grade:4Operating conditions:COM
Logic preference file:liron.lpf
Physical Preference file:fpgatop/liron_fpgatop.prf
Product Version:3.9.0.99.2Patch Version:
Updated:2018/03/19 12:36:44
Implementation Location:C:/Users/chamberlin/Documents/Liron/lattice/fpgatop
Project File:C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf

+

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diff --git a/lattice/fpgatop/liron_fpgatop_trce.asd b/lattice/fpgatop/liron_fpgatop_trce.asd
new file mode 100644
index 0000000..05da955
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_trce.asd
@@ -0,0 +1,11 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Fmax_0 = 104.275 MHz (149.993 MHz);
+Failed = 1 (Total 1);
+Clock_ports = 2;
+Clock_nets = 2;
+; Hold Analysis
+Fmax_0 = 0.307 ns (0.000 ns);
+Failed = 0 (Total 1);
+Clock_ports = 2;
+Clock_nets = 2;
diff --git a/lattice/fpgatop/liron_fpgatop_twr.html b/lattice/fpgatop/liron_fpgatop_twr.html
new file mode 100644
index 0000000..2aab8ca
--- /dev/null
+++ b/lattice/fpgatop/liron_fpgatop_twr.html
@@ -0,0 +1,1238 @@
+
+Lattice TRACE Report
+
+
+
Place & Route TRACE Report
+
+Loading design for application trce from file liron_fpgatop.ncd.
+Design name: top
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.9.0.99.2
+Thu Feb 22 10:56:44 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o liron_fpgatop.twr -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf 
+Design file:     liron_fpgatop.ncd
+Preference file: liron_fpgatop.prf
+Device,speed:    LCMXO2-1200HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "fclk_c" 149.993000 MHz (124 errors)
    • 
+                565 items scored, 124 timing errors detected.
+Warning: 104.275MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "fclk_c" 149.993000 MHz ;
+            565 items scored, 124 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.923ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i2  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i1
+
+   Delay:               9.308ns  (26.1% logic, 73.9% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.308ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_19 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.923ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.308   (26.1% logic, 73.9% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13A.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.923ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i6  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i5
+
+   Delay:               9.308ns  (26.1% logic, 73.9% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.308ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_21 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.923ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13D.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.308   (26.1% logic, 73.9% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13D.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.923ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i4  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i3
+
+   Delay:               9.308ns  (26.1% logic, 73.9% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.308ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_20 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.923ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13B.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.308   (26.1% logic, 73.9% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13B.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.909ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i0  (to fclk_c +)
+
+   Delay:               9.294ns  (26.2% logic, 73.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.294ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_18 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.909ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.091      R8C13B.F1 to      R9C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.294   (26.2% logic, 73.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R9C13A.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.909ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i7  (to fclk_c +)
+
+   Delay:               9.294ns  (26.2% logic, 73.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.294ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_22 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.909ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.520      R8C15C.Q0 to      R9C14D.A0 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14D.A0 to      R9C14D.F0 myIwm/SLICE_37
+ROUTE         1     1.535      R9C14D.F0 to      R9C14D.B1 myIwm/n4
+CTOF_DEL    ---     0.495      R9C14D.B1 to      R9C14D.F1 myIwm/SLICE_37
+ROUTE         3     1.749      R9C14D.F1 to      R8C13C.B0 myIwm/n87
+CTOF_DEL    ---     0.495      R8C13C.B0 to      R8C13C.F0 myIwm/SLICE_41
+ROUTE         1     0.967      R8C13C.F0 to      R8C13B.A1 myIwm/n9
+CTOF_DEL    ---     0.495      R8C13B.A1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.091      R8C13B.F1 to      R9C13C.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    9.294   (26.2% logic, 73.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R9C13C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.207ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i4  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i3
+
+   Delay:               8.592ns  (28.3% logic, 71.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.592ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_20 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.207ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13B.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.592   (28.3% logic, 71.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13B.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.207ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i6  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i5
+
+   Delay:               8.592ns  (28.3% logic, 71.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.592ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_21 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.207ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13D.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.592   (28.3% logic, 71.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13D.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.207ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i2  (to fclk_c +)
+                   FF                        myIwm/shifter_i0_i1
+
+   Delay:               8.592ns  (28.3% logic, 71.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.592ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_19 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.207ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.105      R8C13B.F1 to     R10C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.592   (28.3% logic, 71.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to    R10C13A.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.193ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i7  (to fclk_c +)
+
+   Delay:               8.578ns  (28.4% logic, 71.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.578ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_22 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.193ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.091      R8C13B.F1 to      R9C13C.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.578   (28.4% logic, 71.6% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_22:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R9C13C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.193ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/shifter_i0_i0  (to fclk_c +)
+
+   Delay:               8.578ns  (28.4% logic, 71.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.578ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_18 exceeds
+      6.667ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 6.385ns) by 2.193ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_7 to myIwm/SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15C.CLK to      R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
+ROUTE         8     1.954      R8C15C.Q0 to      R9C14C.B1 myIwm/bitTimer_2
+CTOF_DEL    ---     0.495      R9C14C.B1 to      R9C14C.F1 myIwm/SLICE_39
+ROUTE         3     0.984      R9C14C.F1 to      R9C14A.A1 myIwm/n10
+CTOF_DEL    ---     0.495      R9C14A.A1 to      R9C14A.F1 myIwm/SLICE_38
+ROUTE         4     1.474      R9C14A.F1 to      R8C13B.B0 myIwm/n1862
+CTOF_DEL    ---     0.495      R8C13B.B0 to      R8C13B.F0 myIwm/SLICE_36
+ROUTE         8     0.643      R8C13B.F0 to      R8C13B.D1 myIwm/n163
+CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 myIwm/SLICE_36
+ROUTE         5     1.091      R8C13B.F1 to      R9C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
+                  --------
+                    8.578   (28.4% logic, 71.6% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R8C15C.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     2.264       63.PADDI to     R9C13A.CLK fclk_c
+                  --------
+                    2.264   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 104.275MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "fclk_c" 149.993000 MHz ; |  149.993 MHz|  104.275 MHz|   5 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+1 preference(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+myIwm/fclk_c_enable_14                  |       5|      58|     46.77%
+                                        |        |        |
+myIwm/n1862                             |       4|      56|     45.16%
+                                        |        |        |
+myIwm/n163                              |       8|      53|     42.74%
+                                        |        |        |
+myIwm/n10                               |       3|      51|     41.13%
+                                        |        |        |
+myIwm/bitTimer_2                        |       8|      43|     34.68%
+                                        |        |        |
+myIwm/n87                               |       3|      39|     31.45%
+                                        |        |        |
+myIwm/n9                                |       1|      33|     26.61%
+                                        |        |        |
+myIwm/bitTimer_1                        |       9|      33|     26.61%
+                                        |        |        |
+myIwm/n4                                |       1|      24|     19.35%
+                                        |        |        |
+myIwm/n514                              |       7|      23|     18.55%
+                                        |        |        |
+myIwm/n1875                             |       2|      17|     13.71%
+                                        |        |        |
+myIwm/n1854                             |       2|      17|     13.71%
+                                        |        |        |
+myIwm/bitTimer_5                        |       8|      17|     13.71%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 2 clocks:
+
+Clock Domain: fclk_c   Source: fclk.PAD   Loads: 27
+   Covered under: FREQUENCY NET "fclk_c" 149.993000 MHz ;
+
+   Data transfers from:
+   Clock Domain: _devsel_c   Source: _devsel.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: _devsel_c   Source: _devsel.PAD   Loads: 13
+   No transfer within this clock domain is found
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 124  Score: 116771
+Cumulative negative slack: 116771
+
+Constraints cover 565 paths, 1 nets, and 301 connections (51.72% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.9.0.99.2
+Thu Feb 22 10:56:44 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o liron_fpgatop.twr -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf 
+Design file:     liron_fpgatop.ncd
+Preference file: liron_fpgatop.prf
+Device,speed:    LCMXO2-1200HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "fclk_c" 149.993000 MHz (0 errors)
    •             565 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "fclk_c" 149.993000 MHz ;
+            565 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.307ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/rddataSync_i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/rddataSync_i1  (to fclk_c +)
+
+   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.288ns physical path delay myIwm/SLICE_42 to myIwm/SLICE_42 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.307ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_42 to myIwm/SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C12A.CLK to      R8C12A.Q0 myIwm/SLICE_42 (from fclk_c)
+ROUTE         4     0.155      R8C12A.Q0 to      R8C12A.M1 myIwm/rddataSync_0 (to fclk_c)
+                  --------
+                    0.288   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C12A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C12A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/wrdata_130  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/wrdata_130  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_29 to myIwm/SLICE_29 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_29 to myIwm/SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C14B.CLK to      R8C14B.Q0 myIwm/SLICE_29 (from fclk_c)
+ROUTE         2     0.132      R8C14B.Q0 to      R8C14B.A0 wrdata_c
+CTOF_DEL    ---     0.101      R8C14B.A0 to      R8C14B.F0 myIwm/SLICE_29
+ROUTE         1     0.000      R8C14B.F0 to     R8C14B.DI0 myIwm/wrdata_N_115 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C14B.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C14B.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i3  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i3  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_14 to myIwm/SLICE_14 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_14 to myIwm/SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11D.CLK to      R8C11D.Q0 myIwm/SLICE_14 (from fclk_c)
+ROUTE         4     0.132      R8C11D.Q0 to      R8C11D.A0 myIwm/clearBufferTimer_3
+CTOF_DEL    ---     0.101      R8C11D.A0 to      R8C11D.F0 myIwm/SLICE_14
+ROUTE         1     0.000      R8C11D.F0 to     R8C11D.DI0 myIwm/n69 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11D.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11D.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i2  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_13 to myIwm/SLICE_13 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_13 to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11C.CLK to      R8C11C.Q1 myIwm/SLICE_13 (from fclk_c)
+ROUTE         5     0.132      R8C11C.Q1 to      R8C11C.A1 myIwm/clearBufferTimer_2
+CTOF_DEL    ---     0.101      R8C11C.A1 to      R8C11C.F1 myIwm/SLICE_13
+ROUTE         1     0.000      R8C11C.F1 to     R8C11C.DI1 myIwm/n70 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_223__i2  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_223__i2  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_5 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_5 to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14B.CLK to     R10C14B.Q0 myIwm/SLICE_5 (from fclk_c)
+ROUTE         2     0.132     R10C14B.Q0 to     R10C14B.A0 myIwm/bitCounter_2
+CTOF_DEL    ---     0.101     R10C14B.A0 to     R10C14B.F0 myIwm/SLICE_5
+ROUTE         1     0.000     R10C14B.F0 to    R10C14B.DI0 myIwm/n18_adj_148 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14B.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14B.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i1  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_13 to myIwm/SLICE_13 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_13 to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11C.CLK to      R8C11C.Q0 myIwm/SLICE_13 (from fclk_c)
+ROUTE         6     0.132      R8C11C.Q0 to      R8C11C.A0 myIwm/clearBufferTimer_1
+CTOF_DEL    ---     0.101      R8C11C.A0 to      R8C11C.F0 myIwm/SLICE_13
+ROUTE         1     0.000      R8C11C.F0 to     R8C11C.DI0 myIwm/n71 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_223__i1  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_223__i1  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_4 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_4 to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q1 myIwm/SLICE_4 (from fclk_c)
+ROUTE         3     0.132     R10C14C.Q1 to     R10C14C.A1 myIwm/bitCounter_1
+CTOF_DEL    ---     0.101     R10C14C.A1 to     R10C14C.F1 myIwm/SLICE_4
+ROUTE         1     0.000     R10C14C.F1 to    R10C14C.DI1 myIwm/n19_adj_149 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitCounter_223__i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitCounter_223__i0  (to fclk_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_4 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_4 to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q0 myIwm/SLICE_4 (from fclk_c)
+ROUTE         4     0.132     R10C14C.Q0 to     R10C14C.A0 myIwm/bitCounter_0
+CTOF_DEL    ---     0.101     R10C14C.A0 to     R10C14C.F0 myIwm/SLICE_4
+ROUTE         1     0.000     R10C14C.F0 to    R10C14C.DI0 myIwm/n20 (to fclk_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to    R10C14C.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.380ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/clearBufferTimer_i0_i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/clearBufferTimer_i0_i0  (to fclk_c +)
+
+   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.367ns physical path delay myIwm/SLICE_12 to myIwm/SLICE_12 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.380ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_12 to myIwm/SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11A.CLK to      R8C11A.Q0 myIwm/SLICE_12 (from fclk_c)
+ROUTE         7     0.133      R8C11A.Q0 to      R8C11A.A0 myIwm/clearBufferTimer_0
+CTOF_DEL    ---     0.101      R8C11A.A0 to      R8C11A.F0 myIwm/SLICE_12
+ROUTE         1     0.000      R8C11A.F0 to     R8C11A.DI0 myIwm/clearBufferTimer_3_N_70_0 (to fclk_c)
+                  --------
+                    0.367   (63.8% logic, 36.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C11A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.381ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              myIwm/bitTimer__i0  (from fclk_c +)
+   Destination:    FF         Data in        myIwm/bitTimer__i0  (to fclk_c +)
+
+   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.368ns physical path delay myIwm/SLICE_6 to myIwm/SLICE_6 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.381ns
+
+ Physical Path Details:
+
+      Data path myIwm/SLICE_6 to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C14A.CLK to      R8C14A.Q0 myIwm/SLICE_6 (from fclk_c)
+ROUTE         8     0.134      R8C14A.Q0 to      R8C14A.A0 myIwm/bitTimer_0
+CTOF_DEL    ---     0.101      R8C14A.A0 to      R8C14A.F0 myIwm/SLICE_6
+ROUTE         1     0.000      R8C14A.F0 to     R8C14A.DI0 myIwm/n1733 (to fclk_c)
+                  --------
+                    0.368   (63.6% logic, 36.4% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path fclk to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C14A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path fclk to myIwm/SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        27     0.788       63.PADDI to     R8C14A.CLK fclk_c
+                  --------
+                    0.788   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "fclk_c" 149.993000 MHz ; |     0.000 ns|     0.307 ns|   1  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 2 clocks:
+
+Clock Domain: fclk_c   Source: fclk.PAD   Loads: 27
+   Covered under: FREQUENCY NET "fclk_c" 149.993000 MHz ;
+
+   Data transfers from:
+   Clock Domain: _devsel_c   Source: _devsel.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: _devsel_c   Source: _devsel.PAD   Loads: 13
+   No transfer within this clock domain is found
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 565 paths, 1 nets, and 301 connections (51.72% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 124 (setup), 0 (hold)
+Score: 116771 (setup), 0 (hold)
+Cumulative negative slack: 116771 (116771+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
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+
    
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+
diff --git a/lattice/fpgatop/message.xml b/lattice/fpgatop/message.xml
new file mode 100644
index 0000000..9f6e87d
--- /dev/null
+++ b/lattice/fpgatop/message.xml
@@ -0,0 +1,97 @@
+
+
+    
+        
+            35002000
+            Info
+        
+        
+            35001781
+            Info
+        
+        
+            35901018
+            Info
+            c:/users/chamberlin/documents/liron/lattice/top.v(2): 
+            top
+            c:/users/chamberlin/documents/liron/lattice/top.v
+            2
+        
+        
+            35901018
+            Info
+            c:/users/chamberlin/documents/liron/lattice/addrdecoder.v(2): 
+            addrDecoder
+            c:/users/chamberlin/documents/liron/lattice/addrdecoder.v
+            2
+        
+        
+            35901018
+            Info
+            c:/users/chamberlin/documents/liron/lattice/iwm.v(2): 
+            iwm
+            c:/users/chamberlin/documents/liron/lattice/iwm.v
+            2
+        
+        
+            35901018
+            Info
+            c:/users/chamberlin/documents/liron/lattice/coderom.v(8): 
+            codeROM
+            c:/users/chamberlin/documents/liron/lattice/coderom.v
+            8
+        
+        
+            35901018
+            Info
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): 
+            DP8KC_renamed_due_excessive_length_1
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+            1291
+        
+        
+            35901018
+            Info
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): 
+            DP8KC_renamed_due_excessive_length_2
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+            1291
+        
+        
+            35901018
+            Info
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): 
+            DP8KC_renamed_due_excessive_length_3
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+            1291
+        
+        
+            35901018
+            Info
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120): 
+            VHI
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+            1120
+        
+        
+            35901018
+            Info
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124): 
+            VLO
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+            1124
+        
+        
+            35901018
+            Info
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): 
+            DP8KC_renamed_due_excessive_length_4
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+            1291
+        
+        
+            35001611
+            Warning
+        
+    
+
\ No newline at end of file
diff --git a/lattice/fpgatop/synthesis_lse.html b/lattice/fpgatop/synthesis_lse.html
new file mode 100644
index 0000000..1ef9603
--- /dev/null
+++ b/lattice/fpgatop/synthesis_lse.html
@@ -0,0 +1,267 @@
+
+Synthesis and Ngdbuild Report
+
+
+
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.9.0.99.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Feb 22 10:56:36 2018
+
+
+Command Line:  synthesis -f liron_fpgatop_lattice.synproj -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-1200HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-1200HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = top.
+Target frequency = 1.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/chamberlin/Documents/Liron/lattice (searchpath added)
+-p C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data (searchpath added)
+-p C:/Users/chamberlin/Documents/Liron/lattice/fpgatop (searchpath added)
+-p C:/Users/chamberlin/Documents/Liron/lattice (searchpath added)
+Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/top.v
+Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v
+Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/iwm.v
+Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v
+NGD file = liron_fpgatop.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/top.v. VERI-1482
+Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/addrdecoder.v. VERI-1482
+Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/iwm.v. VERI-1482
+Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/coderom.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): top
+INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/top.v(2): compiling module top. VERI-1018
+INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/addrdecoder.v(2): compiling module addrDecoder. VERI-1018
+INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/iwm.v(2): compiling module iwm. VERI-1018
+INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/coderom.v(8): compiling module codeROM. VERI-1018
+INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_1. VERI-1018
+INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_2. VERI-1018
+INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_3. VERI-1018
+INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120): compiling module VHI. VERI-1018
+INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124): compiling module VLO. VERI-1018
+INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_4. VERI-1018
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Top-level module name = top.
+######## Converting I/O port _enbl2 to output.
+######## Converting I/O port select to output.
+######## Converting I/O port _en35 to output.
+######## Missing driver on net spi_clk. Patching with GND.
+######## Missing driver on net spi_mosi. Patching with GND.
+######## Missing driver on net spi_cs. Patching with GND.
+
+
+
+GSR instance connected to net n440_c.
+Applying 1.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in top_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file liron_fpgatop.ngd.
+
+################### Begin Area Report (top)######################
+Number of register bits => 43 of 1520 (2 % )
+BB => 8
+DP8KC => 4
+FD1P3AX => 29
+FD1P3IX => 10
+FD1P3JX => 1
+FD1S3AX => 2
+FD1S3AY => 1
+GSR => 1
+IB => 22
+INV => 1
+LUT4 => 115
+OB => 19
+OBZ => 3
+PFUMX => 1
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 2
+  Net : fclk_c, loads : 39
+  Net : _devsel_c, loads : 6
+Clock Enable Nets
+Number of Clock Enables: 17
+Top 10 highest fanout Clock Enables:
+  Net : myIwm/q7, loads : 21
+  Net : myIwm/fclk_c_enable_14, loads : 8
+  Net : myIwm/fclk_c_enable_26, loads : 7
+  Net : myIwm/fclk_c_enable_20, loads : 6
+  Net : myIwm/fclk_c_enable_30, loads : 4
+  Net : myIwm/fclk_c_enable_16, loads : 3
+  Net : myIwm/_devsel_N_40_enable_4, loads : 1
+  Net : myIwm/fclk_c_enable_27, loads : 1
+  Net : myIwm/_devsel_N_40_enable_5, loads : 1
+  Net : myIwm/_devsel_N_40_enable_1, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : myIwm/q7, loads : 21
+  Net : addr_c_0, loads : 17
+  Net : addr_c_3, loads : 13
+  Net : addr_c_2, loads : 13
+  Net : addr_c_1, loads : 13
+  Net : myIwm/q6, loads : 12
+  Net : myIwm/writeBufferEmpty, loads : 11
+  Net : myIwm/n142, loads : 11
+  Net : myIwm/n1871, loads : 11
+  Net : myIwm/bitTimer_3, loads : 10
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk1 [get_nets _devsel_c]               |            -|            -|     0  
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk0 [get_nets fclk_c]                  |    1.000 MHz|   99.890 MHz|     5  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+Peak Memory Usage: 53.680  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.920  secs
+--------------------------------------------------------------
+
+
+
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diff --git a/lattice/fpgatop/top_lse.twr b/lattice/fpgatop/top_lse.twr
new file mode 100644
index 0000000..b32447f
--- /dev/null
+++ b/lattice/fpgatop/top_lse.twr
@@ -0,0 +1,158 @@
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Thu Feb 22 10:56:37 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     top
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 1000.000000 -name clk1 [get_nets _devsel_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 1000.000000 -name clk0 [get_nets fclk_c]
+            702 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 989.989ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1P3IX    CK             \myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FD1P3AX    SP             \myIwm/shifter_i0_i0  (to fclk_c +)
+
+   Delay:                   9.726ns  (24.8% logic, 75.2% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.726ns data_path \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i0 meets
+    1000.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 999.715ns) by 989.989ns
+
+ Path Details: \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i0
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              \myIwm/bitTimer__i1 (from fclk_c)
+Route         9   e 1.632                                  \myIwm/bitTimer[1]
+LUT4        ---     0.493              D to Z              \myIwm/i4_4_lut
+Route         3   e 1.258                                  \myIwm/n10
+LUT4        ---     0.493              B to Z              \myIwm/i5_3_lut_rep_20
+Route         4   e 1.340                                  \myIwm/n1862
+LUT4        ---     0.493              B to Z              \myIwm/i145_3_lut_4_lut
+Route         8   e 1.540                                  \myIwm/n163
+LUT4        ---     0.493              B to Z              \myIwm/i1_4_lut_adj_28
+Route         8   e 1.540                                  \myIwm/fclk_c_enable_14
+                  --------
+                    9.726  (24.8% logic, 75.2% route), 5 logic levels.
+
+
+Passed:  The following path meets requirements by 989.989ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1P3IX    CK             \myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FD1P3AX    SP             \myIwm/shifter_i0_i1  (to fclk_c +)
+
+   Delay:                   9.726ns  (24.8% logic, 75.2% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.726ns data_path \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i1 meets
+    1000.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 999.715ns) by 989.989ns
+
+ Path Details: \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i1
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              \myIwm/bitTimer__i1 (from fclk_c)
+Route         9   e 1.632                                  \myIwm/bitTimer[1]
+LUT4        ---     0.493              D to Z              \myIwm/i4_4_lut
+Route         3   e 1.258                                  \myIwm/n10
+LUT4        ---     0.493              B to Z              \myIwm/i5_3_lut_rep_20
+Route         4   e 1.340                                  \myIwm/n1862
+LUT4        ---     0.493              B to Z              \myIwm/i145_3_lut_4_lut
+Route         8   e 1.540                                  \myIwm/n163
+LUT4        ---     0.493              B to Z              \myIwm/i1_4_lut_adj_28
+Route         8   e 1.540                                  \myIwm/fclk_c_enable_14
+                  --------
+                    9.726  (24.8% logic, 75.2% route), 5 logic levels.
+
+
+Passed:  The following path meets requirements by 989.989ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1P3IX    CK             \myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FD1P3AX    SP             \myIwm/shifter_i0_i2  (to fclk_c +)
+
+   Delay:                   9.726ns  (24.8% logic, 75.2% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.726ns data_path \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i2 meets
+    1000.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 999.715ns) by 989.989ns
+
+ Path Details: \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i2
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              \myIwm/bitTimer__i1 (from fclk_c)
+Route         9   e 1.632                                  \myIwm/bitTimer[1]
+LUT4        ---     0.493              D to Z              \myIwm/i4_4_lut
+Route         3   e 1.258                                  \myIwm/n10
+LUT4        ---     0.493              B to Z              \myIwm/i5_3_lut_rep_20
+Route         4   e 1.340                                  \myIwm/n1862
+LUT4        ---     0.493              B to Z              \myIwm/i145_3_lut_4_lut
+Route         8   e 1.540                                  \myIwm/n163
+LUT4        ---     0.493              B to Z              \myIwm/i1_4_lut_adj_28
+Route         8   e 1.540                                  \myIwm/fclk_c_enable_14
+                  --------
+                    9.726  (24.8% logic, 75.2% route), 5 logic levels.
+
+Report: 10.011 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk1 [get_nets _devsel_c]               |            -|            -|     0  
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk0 [get_nets fclk_c]                  |  1000.000 ns|    10.011 ns|     5  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+
+Timing summary:
+---------------
+
+Timing errors: 0  Score: 0
+
+Constraints cover  702 paths, 106 nets, and 328 connections (53.9% coverage)
+
+
+Peak memory: 55623680 bytes, TRCE: 2555904 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
diff --git a/lattice/fpgatop/top_lse_lsetwr.html b/lattice/fpgatop/top_lse_lsetwr.html
new file mode 100644
index 0000000..ec3b746
--- /dev/null
+++ b/lattice/fpgatop/top_lse_lsetwr.html
@@ -0,0 +1,223 @@
+
+Lattice Synthesis Timing Report
+
+
+
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Thu Feb 22 10:56:37 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     top
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 1000.000000 -name clk1 [get_nets _devsel_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 1000.000000 -name clk0 [get_nets fclk_c]
+            702 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 989.989ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1P3IX    CK             \myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FD1P3AX    SP             \myIwm/shifter_i0_i0  (to fclk_c +)
+
+   Delay:                   9.726ns  (24.8% logic, 75.2% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.726ns data_path \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i0 meets
+    1000.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 999.715ns) by 989.989ns
+
+ Path Details: \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i0
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              \myIwm/bitTimer__i1 (from fclk_c)
+Route         9   e 1.632                                  \myIwm/bitTimer[1]
+LUT4        ---     0.493              D to Z              \myIwm/i4_4_lut
+Route         3   e 1.258                                  \myIwm/n10
+LUT4        ---     0.493              B to Z              \myIwm/i5_3_lut_rep_20
+Route         4   e 1.340                                  \myIwm/n1862
+LUT4        ---     0.493              B to Z              \myIwm/i145_3_lut_4_lut
+Route         8   e 1.540                                  \myIwm/n163
+LUT4        ---     0.493              B to Z              \myIwm/i1_4_lut_adj_28
+Route         8   e 1.540                                  \myIwm/fclk_c_enable_14
+                  --------
+                    9.726  (24.8% logic, 75.2% route), 5 logic levels.
+
+
+Passed:  The following path meets requirements by 989.989ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1P3IX    CK             \myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FD1P3AX    SP             \myIwm/shifter_i0_i1  (to fclk_c +)
+
+   Delay:                   9.726ns  (24.8% logic, 75.2% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.726ns data_path \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i1 meets
+    1000.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 999.715ns) by 989.989ns
+
+ Path Details: \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i1
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              \myIwm/bitTimer__i1 (from fclk_c)
+Route         9   e 1.632                                  \myIwm/bitTimer[1]
+LUT4        ---     0.493              D to Z              \myIwm/i4_4_lut
+Route         3   e 1.258                                  \myIwm/n10
+LUT4        ---     0.493              B to Z              \myIwm/i5_3_lut_rep_20
+Route         4   e 1.340                                  \myIwm/n1862
+LUT4        ---     0.493              B to Z              \myIwm/i145_3_lut_4_lut
+Route         8   e 1.540                                  \myIwm/n163
+LUT4        ---     0.493              B to Z              \myIwm/i1_4_lut_adj_28
+Route         8   e 1.540                                  \myIwm/fclk_c_enable_14
+                  --------
+                    9.726  (24.8% logic, 75.2% route), 5 logic levels.
+
+
+Passed:  The following path meets requirements by 989.989ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1P3IX    CK             \myIwm/bitTimer__i1  (from fclk_c +)
+   Destination:    FD1P3AX    SP             \myIwm/shifter_i0_i2  (to fclk_c +)
+
+   Delay:                   9.726ns  (24.8% logic, 75.2% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.726ns data_path \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i2 meets
+    1000.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 999.715ns) by 989.989ns
+
+ Path Details: \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i2
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              \myIwm/bitTimer__i1 (from fclk_c)
+Route         9   e 1.632                                  \myIwm/bitTimer[1]
+LUT4        ---     0.493              D to Z              \myIwm/i4_4_lut
+Route         3   e 1.258                                  \myIwm/n10
+LUT4        ---     0.493              B to Z              \myIwm/i5_3_lut_rep_20
+Route         4   e 1.340                                  \myIwm/n1862
+LUT4        ---     0.493              B to Z              \myIwm/i145_3_lut_4_lut
+Route         8   e 1.540                                  \myIwm/n163
+LUT4        ---     0.493              B to Z              \myIwm/i1_4_lut_adj_28
+Route         8   e 1.540                                  \myIwm/fclk_c_enable_14
+                  --------
+                    9.726  (24.8% logic, 75.2% route), 5 logic levels.
+
+Report: 10.011 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk1 [get_nets _devsel_c]               |            -|            -|     0  
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk0 [get_nets fclk_c]                  |  1000.000 ns|    10.011 ns|     5  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+
+Timing summary:
+---------------
+
+Timing errors: 0  Score: 0
+
+Constraints cover  702 paths, 106 nets, and 328 connections (53.9% coverage)
+
+
+Peak memory: 55623680 bytes, TRCE: 2555904 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
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diff --git a/lattice/fpgatop/top_prim.v b/lattice/fpgatop/top_prim.v
new file mode 100644
index 0000000..d29a10a
--- /dev/null
+++ b/lattice/fpgatop/top_prim.v
@@ -0,0 +1,997 @@
+// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.9.0.99.2
+// Netlist written on Thu Feb 22 10:56:38 2018
+//
+// Verilog Description of module top
+//
+
+module top (addr, fclk, q3, data, rw, _iostrobe, _iosel, _devsel, 
+            _reset, wrdata, phase, _wrreq, _enbl1, _enbl2, select, 
+            _en35, sense, rddata, spi_clk, spi_mosi, spi_miso, spi_cs, 
+            _en245, debugInfo) /* synthesis syn_module_defined=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(2[8:11])
+    input [11:0]addr;   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    input fclk;   // c:/users/chamberlin/documents/liron/lattice/top.v(5[8:12])
+    input q3;   // c:/users/chamberlin/documents/liron/lattice/top.v(6[8:10])
+    inout [7:0]data;   // c:/users/chamberlin/documents/liron/lattice/top.v(7[14:18])
+    input rw;   // c:/users/chamberlin/documents/liron/lattice/top.v(8[8:10])
+    input _iostrobe;   // c:/users/chamberlin/documents/liron/lattice/top.v(9[8:17])
+    input _iosel;   // c:/users/chamberlin/documents/liron/lattice/top.v(10[8:14])
+    input _devsel;   // c:/users/chamberlin/documents/liron/lattice/top.v(11[8:15])
+    input _reset;   // c:/users/chamberlin/documents/liron/lattice/top.v(12[8:14])
+    output wrdata;   // c:/users/chamberlin/documents/liron/lattice/top.v(14[9:15])
+    output [3:0]phase;   // c:/users/chamberlin/documents/liron/lattice/top.v(15[15:20])
+    output _wrreq;   // c:/users/chamberlin/documents/liron/lattice/top.v(16[9:15])
+    output _enbl1;   // c:/users/chamberlin/documents/liron/lattice/top.v(17[9:15])
+    output _enbl2 /* synthesis .original_dir=IN_OUT */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(18[8:14])
+    output select /* synthesis .original_dir=IN_OUT */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(19[8:14])
+    output _en35 /* synthesis .original_dir=IN_OUT */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(20[8:13])
+    input sense;   // c:/users/chamberlin/documents/liron/lattice/top.v(21[8:13])
+    input rddata;   // c:/users/chamberlin/documents/liron/lattice/top.v(22[8:14])
+    output spi_clk;   // c:/users/chamberlin/documents/liron/lattice/top.v(24[9:16])
+    output spi_mosi;   // c:/users/chamberlin/documents/liron/lattice/top.v(25[9:17])
+    input spi_miso;   // c:/users/chamberlin/documents/liron/lattice/top.v(26[8:16])
+    output spi_cs;   // c:/users/chamberlin/documents/liron/lattice/top.v(27[9:15])
+    output _en245;   // c:/users/chamberlin/documents/liron/lattice/top.v(29[9:15])
+    output [7:0]debugInfo;   // c:/users/chamberlin/documents/liron/lattice/top.v(31[15:24])
+    
+    wire fclk_c /* synthesis SET_AS_NETWORK=fclk_c, is_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(5[8:12])
+    wire _devsel_c /* synthesis is_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(11[8:15])
+    wire _devsel_N_40 /* synthesis is_inv_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(14[22:27])
+    
+    wire GND_net, VCC_net, addr_c_11, addr_c_10, addr_c_9, addr_c_8, 
+        addr_c_7, addr_c_6, addr_c_5, addr_c_4, addr_c_3, addr_c_2, 
+        addr_c_1, addr_c_0, n436_c, debugInfo_c_c, n439_c, n438_c, 
+        n440_c, wrdata_c, phase_c_3, phase_c_2, phase_c_1, phase_c_0, 
+        sense_c, rddata_c, n441_c, debugInfo_c_7;
+    wire [7:0]iwmDataOut;   // c:/users/chamberlin/documents/liron/lattice/top.v(70[13:23])
+    wire [7:0]romOutput;   // c:/users/chamberlin/documents/liron/lattice/top.v(89[13:22])
+    
+    wire _en245_N_19, histrobe, n1869;
+    wire [7:0]data_7__N_1;
+    
+    wire data_7__N_9;
+    wire [7:0]buffer;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(25[12:18])
+    
+    wire q6, q7, writeBufferEmpty, n1868, _enbl1_N_124, _wrreq_N_119, 
+        data_out_7, n1904, n1905, n1863, data_out_6, data_out_5, 
+        data_out_4, data_out_3, data_out_2, data_out_1, data_out_0, 
+        n1847, n1846;
+    
+    VHI i2 (.Z(VCC_net));
+    INV i1779 (.A(_devsel_c), .Z(_devsel_N_40));   // c:/users/chamberlin/documents/liron/lattice/top.v(11[8:15])
+    BB data_pad_7 (.I(data_7__N_1[7]), .T(data_7__N_9), .B(data[7]), .O(data_out_7));   // c:/users/chamberlin/documents/liron/lattice/top.v(108[9:13])
+    VLO i1 (.Z(GND_net));
+    LUT4 buffer_7__bdd_3_lut (.A(buffer[7]), .B(sense_c), .C(q6), .Z(n1846)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
+    defparam buffer_7__bdd_3_lut.init = 16'hcaca;
+    TSALL TSALL_INST (.TSALL(GND_net));
+    LUT4 iwmDataOut_7__I_0_i7_3_lut_4_lut (.A(debugInfo_c_c), .B(n1869), 
+         .C(romOutput[6]), .D(iwmDataOut[6]), .Z(data_7__N_1[6])) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(107[24:39])
+    defparam iwmDataOut_7__I_0_i7_3_lut_4_lut.init = 16'hf780;
+    iwm myIwm (.writeBufferEmpty(writeBufferEmpty), .q7(q7), .fclk_c(fclk_c), 
+        .rddata_c(rddata_c), .n436_c(n436_c), .q6(q6), ._devsel_c(_devsel_c), 
+        ._devsel_N_40(_devsel_N_40), .addr_c_0(addr_c_0), .data_out_0(data_out_0), 
+        .histrobe(histrobe), .addr_c_5(addr_c_5), .addr_c_9(addr_c_9), 
+        .addr_c_7(addr_c_7), .addr_c_4(addr_c_4), .addr_c_2(addr_c_2), 
+        .addr_c_11(addr_c_11), .addr_c_8(addr_c_8), .addr_c_6(addr_c_6), 
+        .addr_c_10(addr_c_10), .n439_c(n439_c), .\buffer[3] (buffer[3]), 
+        .wrdata_c(wrdata_c), .n1904(n1904), .\buffer[7] (buffer[7]), .n1868(n1868), 
+        .\iwmDataOut[6] (iwmDataOut[6]), .addr_c_1(addr_c_1), .addr_c_3(addr_c_3), 
+        .n440_c(n440_c), .n1869(n1869), .debugInfo_c_c(debugInfo_c_c), 
+        .data_7__N_9(data_7__N_9), ._wrreq_N_119(_wrreq_N_119), ._enbl1_N_124(_enbl1_N_124), 
+        .\buffer[4] (buffer[4]), .phase_c_1(phase_c_1), .phase_c_3(phase_c_3), 
+        .phase_c_2(phase_c_2), .phase_c_0(phase_c_0), .data_out_1(data_out_1), 
+        .data_out_2(data_out_2), .data_out_3(data_out_3), .data_out_4(data_out_4), 
+        .data_out_5(data_out_5), .data_out_6(data_out_6), .data_out_7(data_out_7), 
+        .n1863(n1863), .\romOutput[5] (romOutput[5]), .\data_7__N_1[5] (data_7__N_1[5]), 
+        .\romOutput[2] (romOutput[2]), .\data_7__N_1[2] (data_7__N_1[2]), 
+        .\romOutput[1] (romOutput[1]), .\data_7__N_1[1] (data_7__N_1[1]), 
+        .\romOutput[0] (romOutput[0]), .\data_7__N_1[0] (data_7__N_1[0])) /* synthesis syn_module_defined=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(72[6] 87[3])
+    LUT4 n1847_bdd_3_lut_4_lut (.A(debugInfo_c_c), .B(n1869), .C(romOutput[7]), 
+         .D(n1847), .Z(data_7__N_1[7])) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(107[24:39])
+    defparam n1847_bdd_3_lut_4_lut.init = 16'hf780;
+    PUR PUR_INST (.PUR(VCC_net));
+    defparam PUR_INST.RST_PULSE = 1;
+    LUT4 m1_lut (.Z(n1905)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
+    defparam m1_lut.init = 16'hffff;
+    LUT4 iwmDataOut_7__I_0_i5_4_lut (.A(buffer[4]), .B(romOutput[4]), .C(n1863), 
+         .D(n1868), .Z(data_7__N_1[4])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(108[16] 110[18])
+    defparam iwmDataOut_7__I_0_i5_4_lut.init = 16'hcac0;
+    BB data_pad_6 (.I(data_7__N_1[6]), .T(data_7__N_9), .B(data[6]), .O(data_out_6));   // c:/users/chamberlin/documents/liron/lattice/top.v(108[9:13])
+    BB data_pad_5 (.I(data_7__N_1[5]), .T(data_7__N_9), .B(data[5]), .O(data_out_5));   // c:/users/chamberlin/documents/liron/lattice/top.v(108[9:13])
+    BB data_pad_4 (.I(data_7__N_1[4]), .T(data_7__N_9), .B(data[4]), .O(data_out_4));   // c:/users/chamberlin/documents/liron/lattice/top.v(108[9:13])
+    BB data_pad_3 (.I(data_7__N_1[3]), .T(data_7__N_9), .B(data[3]), .O(data_out_3));   // c:/users/chamberlin/documents/liron/lattice/top.v(108[9:13])
+    BB data_pad_2 (.I(data_7__N_1[2]), .T(data_7__N_9), .B(data[2]), .O(data_out_2));   // c:/users/chamberlin/documents/liron/lattice/top.v(108[9:13])
+    LUT4 iwmDataOut_7__I_0_i4_4_lut (.A(buffer[3]), .B(romOutput[3]), .C(n1863), 
+         .D(n1868), .Z(data_7__N_1[3])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(108[16] 110[18])
+    defparam iwmDataOut_7__I_0_i4_4_lut.init = 16'hcac0;
+    BB data_pad_1 (.I(data_7__N_1[1]), .T(data_7__N_9), .B(data[1]), .O(data_out_1));   // c:/users/chamberlin/documents/liron/lattice/top.v(108[9:13])
+    BB data_pad_0 (.I(data_7__N_1[0]), .T(data_7__N_9), .B(data[0]), .O(data_out_0));   // c:/users/chamberlin/documents/liron/lattice/top.v(108[9:13])
+    OB wrdata_pad (.I(wrdata_c), .O(wrdata));   // c:/users/chamberlin/documents/liron/lattice/top.v(14[9:15])
+    OB phase_pad_3 (.I(phase_c_3), .O(phase[3]));   // c:/users/chamberlin/documents/liron/lattice/top.v(15[15:20])
+    OB phase_pad_2 (.I(phase_c_2), .O(phase[2]));   // c:/users/chamberlin/documents/liron/lattice/top.v(15[15:20])
+    OB phase_pad_1 (.I(phase_c_1), .O(phase[1]));   // c:/users/chamberlin/documents/liron/lattice/top.v(15[15:20])
+    OB phase_pad_0 (.I(phase_c_0), .O(phase[0]));   // c:/users/chamberlin/documents/liron/lattice/top.v(15[15:20])
+    OB _wrreq_pad (.I(_wrreq_N_119), .O(_wrreq));   // c:/users/chamberlin/documents/liron/lattice/top.v(16[9:15])
+    OB _enbl1_pad (.I(_enbl1_N_124), .O(_enbl1));   // c:/users/chamberlin/documents/liron/lattice/top.v(17[9:15])
+    OBZ _enbl2_pad (.I(GND_net), .T(VCC_net), .O(_enbl2));   // c:/users/chamberlin/documents/liron/lattice/top.v(56[9:15])
+    OBZ select_pad (.I(GND_net), .T(VCC_net), .O(select));   // c:/users/chamberlin/documents/liron/lattice/top.v(57[9:15])
+    OBZ _en35_pad (.I(GND_net), .T(VCC_net), .O(_en35));   // c:/users/chamberlin/documents/liron/lattice/top.v(58[9:14])
+    OB spi_clk_pad (.I(GND_net), .O(spi_clk));   // c:/users/chamberlin/documents/liron/lattice/top.v(24[9:16])
+    OB spi_mosi_pad (.I(GND_net), .O(spi_mosi));   // c:/users/chamberlin/documents/liron/lattice/top.v(25[9:17])
+    OB spi_cs_pad (.I(GND_net), .O(spi_cs));   // c:/users/chamberlin/documents/liron/lattice/top.v(27[9:15])
+    OB _en245_pad (.I(_en245_N_19), .O(_en245));   // c:/users/chamberlin/documents/liron/lattice/top.v(29[9:15])
+    OB debugInfo_pad_7 (.I(debugInfo_c_7), .O(debugInfo[7]));   // c:/users/chamberlin/documents/liron/lattice/top.v(31[15:24])
+    OB debugInfo_pad_6 (.I(debugInfo_c_c), .O(debugInfo[6]));   // c:/users/chamberlin/documents/liron/lattice/top.v(31[15:24])
+    OB debugInfo_pad_5 (.I(n436_c), .O(debugInfo[5]));   // c:/users/chamberlin/documents/liron/lattice/top.v(31[15:24])
+    OB debugInfo_pad_4 (.I(n1863), .O(debugInfo[4]));   // c:/users/chamberlin/documents/liron/lattice/top.v(31[15:24])
+    OB debugInfo_pad_3 (.I(n438_c), .O(debugInfo[3]));   // c:/users/chamberlin/documents/liron/lattice/top.v(31[15:24])
+    OB debugInfo_pad_2 (.I(n439_c), .O(debugInfo[2]));   // c:/users/chamberlin/documents/liron/lattice/top.v(31[15:24])
+    OB debugInfo_pad_1 (.I(n440_c), .O(debugInfo[1]));   // c:/users/chamberlin/documents/liron/lattice/top.v(31[15:24])
+    OB debugInfo_pad_0 (.I(n441_c), .O(debugInfo[0]));   // c:/users/chamberlin/documents/liron/lattice/top.v(31[15:24])
+    IB addr_pad_11 (.I(addr[11]), .O(addr_c_11));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_10 (.I(addr[10]), .O(addr_c_10));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_9 (.I(addr[9]), .O(addr_c_9));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_8 (.I(addr[8]), .O(addr_c_8));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_7 (.I(addr[7]), .O(addr_c_7));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_6 (.I(addr[6]), .O(addr_c_6));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_5 (.I(addr[5]), .O(addr_c_5));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_4 (.I(addr[4]), .O(addr_c_4));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_3 (.I(addr[3]), .O(addr_c_3));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_2 (.I(addr[2]), .O(addr_c_2));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_1 (.I(addr[1]), .O(addr_c_1));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB addr_pad_0 (.I(addr[0]), .O(addr_c_0));   // c:/users/chamberlin/documents/liron/lattice/top.v(4[15:19])
+    IB fclk_pad (.I(fclk), .O(fclk_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(5[8:12])
+    IB n436_pad (.I(q3), .O(n436_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(6[8:10])
+    IB debugInfo_c_pad (.I(rw), .O(debugInfo_c_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(8[8:10])
+    IB n439_pad (.I(_iostrobe), .O(n439_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(9[8:17])
+    IB n438_pad (.I(_iosel), .O(n438_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(10[8:14])
+    IB _devsel_pad (.I(_devsel), .O(_devsel_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(11[8:15])
+    IB n440_pad (.I(_reset), .O(n440_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(12[8:14])
+    IB sense_pad (.I(sense), .O(sense_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(21[8:13])
+    IB rddata_pad (.I(rddata), .O(rddata_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(22[8:14])
+    IB n441_pad (.I(spi_miso), .O(n441_c));   // c:/users/chamberlin/documents/liron/lattice/top.v(26[8:16])
+    LUT4 n1846_bdd_3_lut (.A(n1846), .B(writeBufferEmpty), .C(q7), .Z(n1847)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
+    defparam n1846_bdd_3_lut.init = 16'hcaca;
+    GSR GSR_INST (.GSR(n440_c));
+    codeROM myROM (.addr_c_11(addr_c_11), .addr_c_10(addr_c_10), .addr_c_9(addr_c_9), 
+            .addr_c_8(addr_c_8), .addr_c_7(addr_c_7), .addr_c_6(addr_c_6), 
+            .addr_c_5(addr_c_5), .addr_c_4(addr_c_4), .addr_c_3(addr_c_3), 
+            .addr_c_2(addr_c_2), .addr_c_1(addr_c_1), .addr_c_0(addr_c_0), 
+            .fclk_c(fclk_c), .VCC_net(VCC_net), .GND_net(GND_net), .romOutput({romOutput})) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(91[10] 97[3])
+    addrDecoder myAddrDecoder (.n438_c(n438_c), .debugInfo_c_7(debugInfo_c_7), 
+            .fclk_c(fclk_c), .histrobe(histrobe), .n1905(n1905), .n439_c(n439_c), 
+            .n1869(n1869), .debugInfo_c_c(debugInfo_c_c), .n1863(n1863), 
+            ._devsel_c(_devsel_c), ._en245_N_19(_en245_N_19)) /* synthesis syn_module_defined=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(60[14] 68[3])
+    LUT4 m0_lut (.Z(n1904)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
+    defparam m0_lut.init = 16'h0000;
+    
+endmodule
+//
+// Verilog Description of module TSALL
+// module not written out since it is a black-box. 
+//
+
+//
+// Verilog Description of module iwm
+//
+
+module iwm (writeBufferEmpty, q7, fclk_c, rddata_c, n436_c, q6, 
+            _devsel_c, _devsel_N_40, addr_c_0, data_out_0, histrobe, 
+            addr_c_5, addr_c_9, addr_c_7, addr_c_4, addr_c_2, addr_c_11, 
+            addr_c_8, addr_c_6, addr_c_10, n439_c, \buffer[3] , wrdata_c, 
+            n1904, \buffer[7] , n1868, \iwmDataOut[6] , addr_c_1, 
+            addr_c_3, n440_c, n1869, debugInfo_c_c, data_7__N_9, _wrreq_N_119, 
+            _enbl1_N_124, \buffer[4] , phase_c_1, phase_c_3, phase_c_2, 
+            phase_c_0, data_out_1, data_out_2, data_out_3, data_out_4, 
+            data_out_5, data_out_6, data_out_7, n1863, \romOutput[5] , 
+            \data_7__N_1[5] , \romOutput[2] , \data_7__N_1[2] , \romOutput[1] , 
+            \data_7__N_1[1] , \romOutput[0] , \data_7__N_1[0] ) /* synthesis syn_module_defined=1 */ ;
+    output writeBufferEmpty;
+    output q7;
+    input fclk_c;
+    input rddata_c;
+    input n436_c;
+    output q6;
+    input _devsel_c;
+    input _devsel_N_40;
+    input addr_c_0;
+    input data_out_0;
+    output histrobe;
+    input addr_c_5;
+    input addr_c_9;
+    input addr_c_7;
+    input addr_c_4;
+    input addr_c_2;
+    input addr_c_11;
+    input addr_c_8;
+    input addr_c_6;
+    input addr_c_10;
+    input n439_c;
+    output \buffer[3] ;
+    output wrdata_c;
+    input n1904;
+    output \buffer[7] ;
+    output n1868;
+    output \iwmDataOut[6] ;
+    input addr_c_1;
+    input addr_c_3;
+    input n440_c;
+    input n1869;
+    input debugInfo_c_c;
+    output data_7__N_9;
+    output _wrreq_N_119;
+    output _enbl1_N_124;
+    output \buffer[4] ;
+    output phase_c_1;
+    output phase_c_3;
+    output phase_c_2;
+    output phase_c_0;
+    input data_out_1;
+    input data_out_2;
+    input data_out_3;
+    input data_out_4;
+    input data_out_5;
+    input data_out_6;
+    input data_out_7;
+    input n1863;
+    input \romOutput[5] ;
+    output \data_7__N_1[5] ;
+    input \romOutput[2] ;
+    output \data_7__N_1[2] ;
+    input \romOutput[1] ;
+    output \data_7__N_1[1] ;
+    input \romOutput[0] ;
+    output \data_7__N_1[0] ;
+    
+    wire fclk_c /* synthesis SET_AS_NETWORK=fclk_c, is_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(5[8:12])
+    wire _devsel_c /* synthesis is_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(11[8:15])
+    wire _devsel_N_40 /* synthesis is_inv_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(14[22:27])
+    
+    wire n142, n1858, writeBufferEmpty_N_139;
+    wire [7:0]buffer;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(25[12:18])
+    wire [7:0]shifter;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(24[12:19])
+    
+    wire n1871;
+    wire [7:0]n229_adj_150;
+    wire [1:0]rddataSync;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(164[12:22])
+    
+    wire n6, n514, n163;
+    wire [7:0]shifter_7__N_100;
+    
+    wire n1862, n1877, driveSelect, _devsel_N_40_enable_1, _devsel_N_40_enable_2, 
+        fclk_c_enable_14;
+    wire [7:0]buffer_7__N_49;
+    wire [5:0]bitTimer;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(170[12:20])
+    
+    wire n4, n87, fclk_c_enable_4, n10, fclk_c_enable_16, fclk_c_enable_20, 
+        n302, n1733, n19, n1866, n17, n18, fclk_c_enable_26, n1903, 
+        n1854, n9, n8, wrdata_N_115, _devsel_N_40_enable_3, _underrun, 
+        n1873, n1875, n1867, n7, fclk_c_enable_30, n1864;
+    wire [3:0]clearBufferTimer;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(172[12:28])
+    
+    wire n1872;
+    wire [3:0]clearBufferTimer_3__N_70;
+    
+    wire n1861, n1859, n278, motorOn;
+    wire [2:0]bitCounter;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(171[12:22])
+    wire [2:0]n1;
+    
+    wire n1865, n1775, _devsel_N_40_enable_4;
+    wire [7:0]n229;
+    
+    wire _devsel_N_40_enable_7, _devsel_N_40_enable_8, n2, n1721, fclk_c_enable_27;
+    wire [3:0]n68;
+    
+    wire n276, n277, n279, n1860, n648, _devsel_N_40_enable_5, _devsel_N_40_enable_6, 
+        n1870, n1855, n1876, n14;
+    
+    LUT4 i966_4_lut (.A(writeBufferEmpty), .B(n142), .C(q7), .D(n1858), 
+         .Z(writeBufferEmpty_N_139)) /* synthesis lut_function=(!(A (B)+!A (B+((D)+!C)))) */ ;
+    defparam i966_4_lut.init = 16'h2232;
+    LUT4 mux_79_i2_4_lut_4_lut_4_lut (.A(writeBufferEmpty), .B(buffer[1]), 
+         .C(shifter[0]), .D(n1871), .Z(n229_adj_150[1])) /* synthesis lut_function=(!(A ((D)+!C)+!A !(B (C+(D))+!B !((D)+!C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam mux_79_i2_4_lut_4_lut_4_lut.init = 16'h44f0;
+    FD1S3AX rddataSync_i0 (.D(rddata_c), .CK(fclk_c), .Q(rddataSync[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(165[9] 167[5])
+    defparam rddataSync_i0.GSR = "DISABLED";
+    LUT4 i3_4_lut (.A(n436_c), .B(n6), .C(q6), .D(_devsel_c), .Z(n142)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(72[19:65])
+    defparam i3_4_lut.init = 16'h0040;
+    LUT4 n514_bdd_4_lut_1776 (.A(n514), .B(shifter[2]), .C(n229_adj_150[3]), 
+         .D(n163), .Z(shifter_7__N_100[3])) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
+    defparam n514_bdd_4_lut_1776.init = 16'h88f0;
+    LUT4 mux_85_i1_then_4_lut (.A(writeBufferEmpty), .B(buffer[0]), .C(n1871), 
+         .D(n1862), .Z(n1877)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam mux_85_i1_then_4_lut.init = 16'h0040;
+    FD1P3AX driveSelect_120 (.D(addr_c_0), .SP(_devsel_N_40_enable_1), .CK(_devsel_N_40), 
+            .Q(driveSelect)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam driveSelect_120.GSR = "ENABLED";
+    LUT4 n514_bdd_4_lut_1775 (.A(n514), .B(shifter[3]), .C(n229_adj_150[4]), 
+         .D(n163), .Z(shifter_7__N_100[4])) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
+    defparam n514_bdd_4_lut_1775.init = 16'h88f0;
+    FD1P3AX q7_122 (.D(addr_c_0), .SP(_devsel_N_40_enable_2), .CK(_devsel_N_40), 
+            .Q(q7)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam q7_122.GSR = "ENABLED";
+    FD1P3AX shifter_i0_i0 (.D(shifter_7__N_100[0]), .SP(fclk_c_enable_14), 
+            .CK(fclk_c), .Q(shifter[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam shifter_i0_i0.GSR = "DISABLED";
+    LUT4 i145_3_lut_4_lut (.A(q7), .B(n1862), .C(n1871), .D(writeBufferEmpty), 
+         .Z(n163)) /* synthesis lut_function=((B+(C (D)))+!A) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(265[9] 267[7])
+    defparam i145_3_lut_4_lut.init = 16'hfddd;
+    LUT4 mux_103_i1_3_lut (.A(shifter[0]), .B(data_out_0), .C(n142), .Z(buffer_7__N_49[0])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(285[10] 287[8])
+    defparam mux_103_i1_3_lut.init = 16'hcaca;
+    LUT4 n514_bdd_4_lut_1774 (.A(n514), .B(shifter[4]), .C(n229_adj_150[5]), 
+         .D(n163), .Z(shifter_7__N_100[5])) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
+    defparam n514_bdd_4_lut_1774.init = 16'h88f0;
+    LUT4 i1_2_lut (.A(bitTimer[2]), .B(bitTimer[1]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i1_2_lut.init = 16'h8888;
+    LUT4 i2_4_lut (.A(bitTimer[5]), .B(bitTimer[4]), .C(bitTimer[3]), 
+         .D(n4), .Z(n87)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;
+    defparam i2_4_lut.init = 16'hfeee;
+    LUT4 shifter_5__bdd_4_lut (.A(shifter[5]), .B(n514), .C(n229_adj_150[6]), 
+         .D(n163), .Z(shifter_7__N_100[6])) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
+    defparam shifter_5__bdd_4_lut.init = 16'h88f0;
+    LUT4 shifter_1__bdd_4_lut (.A(shifter[1]), .B(n514), .C(n229_adj_150[2]), 
+         .D(n163), .Z(shifter_7__N_100[2])) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
+    defparam shifter_1__bdd_4_lut.init = 16'h88f0;
+    LUT4 i1_2_lut_3_lut_3_lut (.A(n1871), .B(writeBufferEmpty), .C(n1862), 
+         .Z(fclk_c_enable_4)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
+    defparam i1_2_lut_3_lut_3_lut.init = 16'h0808;
+    LUT4 n514_bdd_4_lut_1773 (.A(n514), .B(shifter[6]), .C(n229_adj_150[7]), 
+         .D(n163), .Z(shifter_7__N_100[7])) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
+    defparam n514_bdd_4_lut_1773.init = 16'h88f0;
+    LUT4 i5_3_lut_rep_20 (.A(bitTimer[3]), .B(n10), .C(bitTimer[4]), .Z(n1862)) /* synthesis lut_function=((B+!(C))+!A) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(235[9:23])
+    defparam i5_3_lut_rep_20.init = 16'hdfdf;
+    LUT4 i210_2_lut_rep_14_4_lut (.A(bitTimer[3]), .B(n10), .C(bitTimer[4]), 
+         .D(q7), .Z(fclk_c_enable_16)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(235[9:23])
+    defparam i210_2_lut_rep_14_4_lut.init = 16'h2000;
+    FD1P3IX bitTimer__i0 (.D(n1733), .SP(fclk_c_enable_20), .CD(n302), 
+            .CK(fclk_c), .Q(bitTimer[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam bitTimer__i0.GSR = "DISABLED";
+    LUT4 i1_4_lut (.A(n19), .B(n1866), .C(n17), .D(n18), .Z(histrobe)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1_4_lut.init = 16'h8000;
+    FD1S3AY writeBufferEmpty_126 (.D(writeBufferEmpty_N_139), .CK(fclk_c), 
+            .Q(writeBufferEmpty)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam writeBufferEmpty_126.GSR = "ENABLED";
+    LUT4 i8_4_lut (.A(addr_c_5), .B(addr_c_9), .C(addr_c_7), .D(addr_c_0), 
+         .Z(n19)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i8_4_lut.init = 16'h8000;
+    LUT4 i6_3_lut (.A(addr_c_4), .B(addr_c_2), .C(addr_c_11), .Z(n17)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i6_3_lut.init = 16'h8080;
+    LUT4 i7_4_lut (.A(addr_c_8), .B(addr_c_6), .C(addr_c_10), .D(n439_c), 
+         .Z(n18)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i7_4_lut.init = 16'h0080;
+    FD1P3AX buffer_i0 (.D(buffer_7__N_49[0]), .SP(fclk_c_enable_26), .CK(fclk_c), 
+            .Q(buffer[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam buffer_i0.GSR = "ENABLED";
+    LUT4 i643_4_lut (.A(shifter[7]), .B(n87), .C(n1903), .D(n1854), 
+         .Z(n9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;
+    defparam i643_4_lut.init = 16'hcfca;
+    LUT4 mux_79_i4_4_lut_4_lut_4_lut (.A(writeBufferEmpty), .B(\buffer[3] ), 
+         .C(shifter[2]), .D(n1871), .Z(n229_adj_150[3])) /* synthesis lut_function=(!(A ((D)+!C)+!A !(B (C+(D))+!B !((D)+!C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam mux_79_i4_4_lut_4_lut_4_lut.init = 16'h44f0;
+    LUT4 i1001_2_lut_rep_16_2_lut_4_lut (.A(bitTimer[3]), .B(n10), .C(bitTimer[4]), 
+         .D(n1871), .Z(n1858)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(235[9:23])
+    defparam i1001_2_lut_rep_16_2_lut_4_lut.init = 16'hdfff;
+    LUT4 wrdata_I_0_4_lut (.A(wrdata_c), .B(shifter[7]), .C(n8), .D(bitTimer[4]), 
+         .Z(wrdata_N_115)) /* synthesis lut_function=(A (((D)+!C)+!B)+!A !(((D)+!C)+!B)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(261[5] 263[8])
+    defparam wrdata_I_0_4_lut.init = 16'haa6a;
+    FD1P3AX q6_121 (.D(addr_c_0), .SP(_devsel_N_40_enable_3), .CK(_devsel_N_40), 
+            .Q(q6)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam q6_121.GSR = "ENABLED";
+    FD1P3JX _underrun_125 (.D(n1904), .SP(fclk_c_enable_4), .PD(n1873), 
+            .CK(fclk_c), .Q(_underrun));   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam _underrun_125.GSR = "ENABLED";
+    LUT4 i3_4_lut_adj_17 (.A(n1875), .B(bitTimer[3]), .C(bitTimer[5]), 
+         .D(bitTimer[0]), .Z(n8)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
+    defparam i3_4_lut_adj_17.init = 16'h0100;
+    LUT4 i1743_3_lut_rep_15_4_lut (.A(\buffer[7] ), .B(n1867), .C(n7), 
+         .D(n1868), .Z(fclk_c_enable_30)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (C (D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(189[10:59])
+    defparam i1743_3_lut_rep_15_4_lut.init = 16'hf200;
+    LUT4 mux_49_i1_4_lut (.A(n1864), .B(clearBufferTimer[0]), .C(n7), 
+         .D(n1872), .Z(clearBufferTimer_3__N_70[0])) /* synthesis lut_function=(!(A (B (C)+!B (C (D)))+!A (B+((D)+!C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(193[10] 202[8])
+    defparam mux_49_i1_4_lut.init = 16'h0a3a;
+    LUT4 i3_4_lut_adj_18 (.A(clearBufferTimer[0]), .B(clearBufferTimer[2]), 
+         .C(clearBufferTimer[1]), .D(clearBufferTimer[3]), .Z(n7)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(187[9:30])
+    defparam i3_4_lut_adj_18.init = 16'hfffe;
+    LUT4 i984_3_lut_4_lut (.A(bitTimer[3]), .B(n1861), .C(n1859), .D(bitTimer[4]), 
+         .Z(n278)) /* synthesis lut_function=(!(A (B (C+(D))+!B (C+!(D)))+!A (C+!(D)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(227[19:34])
+    defparam i984_3_lut_4_lut.init = 16'h0708;
+    LUT4 i2_2_lut_3_lut (.A(q7), .B(motorOn), .C(addr_c_0), .Z(n6)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(72[19:65])
+    defparam i2_2_lut_3_lut.init = 16'h8080;
+    LUT4 i341_2_lut_rep_12_4_lut (.A(n1875), .B(bitTimer[4]), .C(bitTimer[3]), 
+         .D(bitTimer[5]), .Z(n1854)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;
+    defparam i341_2_lut_rep_12_4_lut.init = 16'hec00;
+    FD1P3AX wrdata_130 (.D(wrdata_N_115), .SP(q7), .CK(fclk_c), .Q(wrdata_c));   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam wrdata_130.GSR = "ENABLED";
+    LUT4 i1536_3_lut (.A(bitCounter[2]), .B(bitCounter[1]), .C(bitCounter[0]), 
+         .Z(n1[2])) /* synthesis lut_function=(!(A (B (C))+!A !(B (C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(252[21:38])
+    defparam i1536_3_lut.init = 16'h6a6a;
+    LUT4 i1529_2_lut (.A(bitCounter[1]), .B(bitCounter[0]), .Z(n1[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(252[21:38])
+    defparam i1529_2_lut.init = 16'h6666;
+    LUT4 i1_3_lut_4_lut (.A(n1865), .B(bitTimer[5]), .C(shifter[7]), .D(n1903), 
+         .Z(n1775)) /* synthesis lut_function=(!(A (B+((D)+!C))+!A ((D)+!C))) */ ;
+    defparam i1_3_lut_4_lut.init = 16'h0070;
+    FD1P3AX motorOn_119 (.D(addr_c_0), .SP(_devsel_N_40_enable_4), .CK(_devsel_N_40), 
+            .Q(motorOn)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam motorOn_119.GSR = "ENABLED";
+    LUT4 mux_177_i7_4_lut (.A(buffer[6]), .B(_underrun), .C(q7), .D(q6), 
+         .Z(\iwmDataOut[6] )) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(152[3] 159[10])
+    defparam mux_177_i7_4_lut.init = 16'hc0ca;
+    LUT4 i1_2_lut_rep_24 (.A(addr_c_1), .B(addr_c_3), .Z(n1866)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1_2_lut_rep_24.init = 16'h8888;
+    LUT4 mux_178_Mux_5_i1_3_lut (.A(buffer[5]), .B(motorOn), .C(q6), .Z(n229[5])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(152[3] 159[10])
+    defparam mux_178_Mux_5_i1_3_lut.init = 16'hcaca;
+    LUT4 i1_2_lut_3_lut (.A(addr_c_1), .B(addr_c_3), .C(addr_c_2), .Z(_devsel_N_40_enable_1)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1_2_lut_3_lut.init = 16'h0808;
+    LUT4 i1_2_lut_3_lut_adj_19 (.A(addr_c_1), .B(addr_c_3), .C(addr_c_2), 
+         .Z(_devsel_N_40_enable_2)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1_2_lut_3_lut_adj_19.init = 16'h8080;
+    FD1P3AX clearBufferTimer_i0_i0 (.D(clearBufferTimer_3__N_70[0]), .SP(fclk_c_enable_30), 
+            .CK(fclk_c), .Q(clearBufferTimer[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam clearBufferTimer_i0_i0.GSR = "ENABLED";
+    LUT4 i1752_2_lut_3_lut (.A(addr_c_1), .B(addr_c_3), .C(addr_c_2), 
+         .Z(_devsel_N_40_enable_7)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1752_2_lut_3_lut.init = 16'h1010;
+    LUT4 i53_2_lut_rep_34 (.A(rddataSync[1]), .B(rddataSync[0]), .Z(n1903)) /* synthesis lut_function=(!((B)+!A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(205[9:39])
+    defparam i53_2_lut_rep_34.init = 16'h2222;
+    LUT4 i1746_2_lut_3_lut (.A(addr_c_1), .B(addr_c_3), .C(addr_c_2), 
+         .Z(_devsel_N_40_enable_8)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1746_2_lut_3_lut.init = 16'h0101;
+    FD1P3AX bitCounter_223__i2 (.D(n1[2]), .SP(fclk_c_enable_16), .CK(fclk_c), 
+            .Q(bitCounter[2]));   // c:/users/chamberlin/documents/liron/lattice/iwm.v(252[21:38])
+    defparam bitCounter_223__i2.GSR = "ENABLED";
+    LUT4 i1003_2_lut_rep_25 (.A(_devsel_c), .B(addr_c_0), .Z(n1867)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1003_2_lut_rep_25.init = 16'heeee;
+    FD1P3AX bitCounter_223__i1 (.D(n1[1]), .SP(fclk_c_enable_16), .CK(fclk_c), 
+            .Q(bitCounter[1]));   // c:/users/chamberlin/documents/liron/lattice/iwm.v(252[21:38])
+    defparam bitCounter_223__i1.GSR = "ENABLED";
+    FD1S3AX rddataSync_i1 (.D(rddataSync[0]), .CK(fclk_c), .Q(rddataSync[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(165[9] 167[5])
+    defparam rddataSync_i1.GSR = "DISABLED";
+    LUT4 i1_3_lut (.A(q7), .B(n440_c), .C(q6), .Z(fclk_c_enable_20)) /* synthesis lut_function=(A (B)+!A !((C)+!B)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(28[10:12])
+    defparam i1_3_lut.init = 16'h8c8c;
+    LUT4 i1749_3_lut_4_lut (.A(_devsel_c), .B(addr_c_0), .C(n1869), .D(debugInfo_c_c), 
+         .Z(data_7__N_9)) /* synthesis lut_function=(!(A (C (D))+!A (B (C (D))+!B (D)))) */ ;
+    defparam i1749_3_lut_4_lut.init = 16'h0eff;
+    LUT4 i1736_2_lut_3_lut (.A(q7), .B(motorOn), .C(_underrun), .Z(_wrreq_N_119)) /* synthesis lut_function=(!(A (B (C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(72[19:65])
+    defparam i1736_2_lut_3_lut.init = 16'h7f7f;
+    LUT4 i975_2_lut (.A(buffer[2]), .B(q6), .Z(n229[2])) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(152[3] 159[10])
+    defparam i975_2_lut.init = 16'heeee;
+    FD1P3AX shifter_i0_i1 (.D(shifter_7__N_100[1]), .SP(fclk_c_enable_14), 
+            .CK(fclk_c), .Q(shifter[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam shifter_i0_i1.GSR = "DISABLED";
+    LUT4 i4_4_lut (.A(bitTimer[2]), .B(bitTimer[5]), .C(bitTimer[0]), 
+         .D(bitTimer[1]), .Z(n10)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(235[9:23])
+    defparam i4_4_lut.init = 16'hfffd;
+    LUT4 i1_4_lut_adj_20 (.A(n440_c), .B(n2), .C(n1862), .D(q7), .Z(n302)) /* synthesis lut_function=(!((B (C (D))+!B (C+!(D)))+!A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(28[10:12])
+    defparam i1_4_lut_adj_20.init = 16'h0a88;
+    LUT4 i338_2_lut_rep_33 (.A(bitTimer[1]), .B(bitTimer[2]), .Z(n1875)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i338_2_lut_rep_33.init = 16'heeee;
+    FD1P3AX shifter_i0_i2 (.D(shifter_7__N_100[2]), .SP(fclk_c_enable_14), 
+            .CK(fclk_c), .Q(shifter[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam shifter_i0_i2.GSR = "DISABLED";
+    FD1P3AX shifter_i0_i3 (.D(shifter_7__N_100[3]), .SP(fclk_c_enable_14), 
+            .CK(fclk_c), .Q(shifter[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam shifter_i0_i3.GSR = "DISABLED";
+    FD1P3AX shifter_i0_i4 (.D(shifter_7__N_100[4]), .SP(fclk_c_enable_14), 
+            .CK(fclk_c), .Q(shifter[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam shifter_i0_i4.GSR = "DISABLED";
+    FD1P3AX shifter_i0_i5 (.D(shifter_7__N_100[5]), .SP(fclk_c_enable_14), 
+            .CK(fclk_c), .Q(shifter[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam shifter_i0_i5.GSR = "DISABLED";
+    FD1P3AX shifter_i0_i6 (.D(shifter_7__N_100[6]), .SP(fclk_c_enable_14), 
+            .CK(fclk_c), .Q(shifter[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam shifter_i0_i6.GSR = "DISABLED";
+    FD1P3AX shifter_i0_i7 (.D(shifter_7__N_100[7]), .SP(fclk_c_enable_14), 
+            .CK(fclk_c), .Q(shifter[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam shifter_i0_i7.GSR = "DISABLED";
+    FD1P3IX bitTimer__i1 (.D(n1721), .SP(fclk_c_enable_20), .CD(n302), 
+            .CK(fclk_c), .Q(bitTimer[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam bitTimer__i1.GSR = "DISABLED";
+    LUT4 i1_2_lut_rep_22_3_lut (.A(_devsel_c), .B(addr_c_0), .C(\buffer[7] ), 
+         .Z(n1864)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
+    defparam i1_2_lut_rep_22_3_lut.init = 16'h1010;
+    FD1P3AX bitCounter_223__i0 (.D(n1[0]), .SP(fclk_c_enable_16), .CK(fclk_c), 
+            .Q(bitCounter[0]));   // c:/users/chamberlin/documents/liron/lattice/iwm.v(252[21:38])
+    defparam bitCounter_223__i0.GSR = "ENABLED";
+    LUT4 i1741_2_lut_rep_26 (.A(q7), .B(q6), .Z(n1868)) /* synthesis lut_function=(!(A+(B))) */ ;
+    defparam i1741_2_lut_rep_26.init = 16'h1111;
+    LUT4 i976_2_lut (.A(buffer[1]), .B(q6), .Z(n229[1])) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(152[3] 159[10])
+    defparam i976_2_lut.init = 16'heeee;
+    LUT4 i969_2_lut (.A(buffer[0]), .B(q6), .Z(n229[0])) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(152[3] 159[10])
+    defparam i969_2_lut.init = 16'heeee;
+    LUT4 i1733_2_lut (.A(motorOn), .B(driveSelect), .Z(_enbl1_N_124)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(68[18:43])
+    defparam i1733_2_lut.init = 16'hdddd;
+    LUT4 i1_3_lut_4_lut_adj_21 (.A(q7), .B(q6), .C(n1775), .D(n142), 
+         .Z(fclk_c_enable_26)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C+(D)))) */ ;
+    defparam i1_3_lut_4_lut_adj_21.init = 16'hff10;
+    LUT4 i1_3_lut_adj_22 (.A(n1859), .B(bitTimer[0]), .C(bitTimer[1]), 
+         .Z(n1721)) /* synthesis lut_function=(A+!(B (C)+!B !(C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(220[11] 228[9])
+    defparam i1_3_lut_adj_22.init = 16'hbebe;
+    LUT4 i319_3_lut_rep_23_4_lut (.A(bitTimer[1]), .B(bitTimer[2]), .C(bitTimer[3]), 
+         .D(bitTimer[4]), .Z(n1865)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;
+    defparam i319_3_lut_rep_23_4_lut.init = 16'hffe0;
+    LUT4 i1_3_lut_rep_17 (.A(n1865), .B(bitTimer[5]), .C(q7), .Z(n1859)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
+    defparam i1_3_lut_rep_17.init = 16'h0808;
+    LUT4 i1_2_lut_3_lut_adj_23 (.A(q7), .B(q6), .C(n142), .Z(fclk_c_enable_27)) /* synthesis lut_function=(A (C)+!A ((C)+!B)) */ ;
+    defparam i1_2_lut_3_lut_adj_23.init = 16'hf1f1;
+    LUT4 i257_3_lut_4_lut (.A(clearBufferTimer[1]), .B(clearBufferTimer[0]), 
+         .C(clearBufferTimer[2]), .D(clearBufferTimer[3]), .Z(n68[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(200[27:50])
+    defparam i257_3_lut_4_lut.init = 16'h7f80;
+    LUT4 i1_4_lut_adj_24 (.A(n1868), .B(n1854), .C(n87), .D(n1903), 
+         .Z(n514)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
+    defparam i1_4_lut_adj_24.init = 16'ha088;
+    FD1P3IX bitTimer__i2 (.D(n276), .SP(fclk_c_enable_20), .CD(n302), 
+            .CK(fclk_c), .Q(bitTimer[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam bitTimer__i2.GSR = "DISABLED";
+    FD1P3IX bitTimer__i3 (.D(n277), .SP(fclk_c_enable_20), .CD(n302), 
+            .CK(fclk_c), .Q(bitTimer[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam bitTimer__i3.GSR = "DISABLED";
+    FD1P3IX bitTimer__i4 (.D(n278), .SP(fclk_c_enable_20), .CD(n302), 
+            .CK(fclk_c), .Q(bitTimer[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam bitTimer__i4.GSR = "DISABLED";
+    FD1P3IX bitTimer__i5 (.D(n279), .SP(fclk_c_enable_20), .CD(n302), 
+            .CK(fclk_c), .Q(bitTimer[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam bitTimer__i5.GSR = "DISABLED";
+    FD1P3AX buffer_i1 (.D(buffer_7__N_49[1]), .SP(fclk_c_enable_26), .CK(fclk_c), 
+            .Q(buffer[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam buffer_i1.GSR = "ENABLED";
+    LUT4 i1754_2_lut_3_lut_4_lut (.A(n1864), .B(n1868), .C(n7), .D(n1860), 
+         .Z(n648)) /* synthesis lut_function=(!(A ((C (D))+!B)+!A (((D)+!C)+!B))) */ ;
+    defparam i1754_2_lut_3_lut_4_lut.init = 16'h08c8;
+    LUT4 i250_2_lut_3_lut (.A(clearBufferTimer[1]), .B(clearBufferTimer[0]), 
+         .C(clearBufferTimer[2]), .Z(n68[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(200[27:50])
+    defparam i250_2_lut_3_lut.init = 16'h7878;
+    FD1P3AX buffer_i2 (.D(buffer_7__N_49[2]), .SP(fclk_c_enable_26), .CK(fclk_c), 
+            .Q(buffer[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam buffer_i2.GSR = "ENABLED";
+    FD1P3AX buffer_i3 (.D(buffer_7__N_49[3]), .SP(fclk_c_enable_26), .CK(fclk_c), 
+            .Q(\buffer[3] )) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam buffer_i3.GSR = "ENABLED";
+    FD1P3AX buffer_i4 (.D(buffer_7__N_49[4]), .SP(fclk_c_enable_26), .CK(fclk_c), 
+            .Q(\buffer[4] )) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam buffer_i4.GSR = "ENABLED";
+    FD1P3AX buffer_i5 (.D(buffer_7__N_49[5]), .SP(fclk_c_enable_26), .CK(fclk_c), 
+            .Q(buffer[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam buffer_i5.GSR = "ENABLED";
+    FD1P3AX buffer_i6 (.D(buffer_7__N_49[6]), .SP(fclk_c_enable_26), .CK(fclk_c), 
+            .Q(buffer[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam buffer_i6.GSR = "ENABLED";
+    FD1P3AX buffer_i7 (.D(buffer_7__N_49[7]), .SP(fclk_c_enable_27), .CK(fclk_c), 
+            .Q(\buffer[7] )) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam buffer_i7.GSR = "ENABLED";
+    FD1P3AX phase_i2 (.D(addr_c_0), .SP(_devsel_N_40_enable_5), .CK(_devsel_N_40), 
+            .Q(phase_c_1)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam phase_i2.GSR = "ENABLED";
+    FD1P3AX phase_i4 (.D(addr_c_0), .SP(_devsel_N_40_enable_6), .CK(_devsel_N_40), 
+            .Q(phase_c_3)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam phase_i4.GSR = "ENABLED";
+    LUT4 i1527_1_lut (.A(bitCounter[0]), .Z(n1[0])) /* synthesis lut_function=(!(A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(252[21:38])
+    defparam i1527_1_lut.init = 16'h5555;
+    LUT4 i1_2_lut_3_lut_adj_25 (.A(addr_c_1), .B(addr_c_3), .C(addr_c_2), 
+         .Z(_devsel_N_40_enable_5)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1_2_lut_3_lut_adj_25.init = 16'h0202;
+    LUT4 i1_2_lut_3_lut_adj_26 (.A(addr_c_1), .B(addr_c_3), .C(addr_c_2), 
+         .Z(_devsel_N_40_enable_6)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1_2_lut_3_lut_adj_26.init = 16'h2020;
+    LUT4 i274_2_lut_rep_28 (.A(bitTimer[1]), .B(bitTimer[0]), .Z(n1870)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(227[19:34])
+    defparam i274_2_lut_rep_28.init = 16'h8888;
+    LUT4 i982_3_lut_4_lut (.A(bitTimer[1]), .B(bitTimer[0]), .C(n1859), 
+         .D(bitTimer[2]), .Z(n276)) /* synthesis lut_function=(A (B (C+!(D))+!B (C+(D)))+!A (C+(D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(227[19:34])
+    defparam i982_3_lut_4_lut.init = 16'hf7f8;
+    LUT4 i281_2_lut_rep_19_3_lut (.A(bitTimer[1]), .B(bitTimer[0]), .C(bitTimer[2]), 
+         .Z(n1861)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(227[19:34])
+    defparam i281_2_lut_rep_19_3_lut.init = 16'h8080;
+    LUT4 i985_4_lut (.A(bitTimer[5]), .B(n1859), .C(bitTimer[4]), .D(n1855), 
+         .Z(n279)) /* synthesis lut_function=(!(A (B+(C (D)))+!A (B+!(C (D))))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(220[11] 228[9])
+    defparam i985_4_lut.init = 16'h1222;
+    LUT4 mux_85_i1_else_4_lut_4_lut (.A(rddataSync[1]), .B(rddataSync[0]), 
+         .C(n87), .D(q6), .Z(n1876)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(205[9:39])
+    defparam mux_85_i1_else_4_lut_4_lut.init = 16'h0020;
+    FD1P3IX clearBufferTimer_i0_i3 (.D(n68[3]), .SP(fclk_c_enable_30), .CD(n648), 
+            .CK(fclk_c), .Q(clearBufferTimer[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam clearBufferTimer_i0_i3.GSR = "ENABLED";
+    FD1P3IX clearBufferTimer_i0_i2 (.D(n68[2]), .SP(fclk_c_enable_30), .CD(n648), 
+            .CK(fclk_c), .Q(clearBufferTimer[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam clearBufferTimer_i0_i2.GSR = "ENABLED";
+    FD1P3IX clearBufferTimer_i0_i1 (.D(n68[1]), .SP(fclk_c_enable_30), .CD(n648), 
+            .CK(fclk_c), .Q(clearBufferTimer[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam clearBufferTimer_i0_i1.GSR = "ENABLED";
+    FD1P3AX phase_i3 (.D(addr_c_0), .SP(_devsel_N_40_enable_7), .CK(_devsel_N_40), 
+            .Q(phase_c_2)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam phase_i3.GSR = "ENABLED";
+    FD1P3AX phase_i1 (.D(addr_c_0), .SP(_devsel_N_40_enable_8), .CK(_devsel_N_40), 
+            .Q(phase_c_0)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=6, LSE_RCOL=3, LSE_LLINE=72, LSE_RLINE=87 */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam phase_i1.GSR = "ENABLED";
+    LUT4 mux_79_i8_4_lut_4_lut_4_lut (.A(writeBufferEmpty), .B(shifter[6]), 
+         .C(\buffer[7] ), .D(n1871), .Z(n229_adj_150[7])) /* synthesis lut_function=(!(A ((D)+!B)+!A !(B (C+!(D))+!B (C (D))))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam mux_79_i8_4_lut_4_lut_4_lut.init = 16'h50cc;
+    LUT4 i288_2_lut_rep_13_3_lut_4_lut (.A(bitTimer[1]), .B(bitTimer[0]), 
+         .C(bitTimer[3]), .D(bitTimer[2]), .Z(n1855)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(227[19:34])
+    defparam i288_2_lut_rep_13_3_lut_4_lut.init = 16'h8000;
+    LUT4 i2_3_lut_rep_29 (.A(bitCounter[1]), .B(bitCounter[2]), .C(bitCounter[0]), 
+         .Z(n1871)) /* synthesis lut_function=(A (B (C))) */ ;
+    defparam i2_3_lut_rep_29.init = 16'h8080;
+    LUT4 mux_103_i2_3_lut (.A(shifter[1]), .B(data_out_1), .C(n142), .Z(buffer_7__N_49[1])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(285[10] 287[8])
+    defparam mux_103_i2_3_lut.init = 16'hcaca;
+    LUT4 i2_3_lut_rep_30 (.A(clearBufferTimer[1]), .B(clearBufferTimer[3]), 
+         .C(clearBufferTimer[2]), .Z(n1872)) /* synthesis lut_function=(A (B (C))) */ ;
+    defparam i2_3_lut_rep_30.init = 16'h8080;
+    LUT4 mux_103_i3_3_lut (.A(shifter[2]), .B(data_out_2), .C(n142), .Z(buffer_7__N_49[2])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(285[10] 287[8])
+    defparam mux_103_i3_3_lut.init = 16'hcaca;
+    LUT4 mux_103_i4_3_lut (.A(shifter[3]), .B(data_out_3), .C(n142), .Z(buffer_7__N_49[3])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(285[10] 287[8])
+    defparam mux_103_i4_3_lut.init = 16'hcaca;
+    LUT4 mux_103_i5_3_lut (.A(shifter[4]), .B(data_out_4), .C(n142), .Z(buffer_7__N_49[4])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(285[10] 287[8])
+    defparam mux_103_i5_3_lut.init = 16'hcaca;
+    LUT4 mux_103_i6_3_lut (.A(shifter[5]), .B(data_out_5), .C(n142), .Z(buffer_7__N_49[5])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(285[10] 287[8])
+    defparam mux_103_i6_3_lut.init = 16'hcaca;
+    LUT4 i1_2_lut_rep_18_4_lut (.A(clearBufferTimer[1]), .B(clearBufferTimer[3]), 
+         .C(clearBufferTimer[2]), .D(clearBufferTimer[0]), .Z(n1860)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;
+    defparam i1_2_lut_rep_18_4_lut.init = 16'hff7f;
+    LUT4 mux_103_i7_3_lut (.A(shifter[6]), .B(data_out_6), .C(n142), .Z(buffer_7__N_49[6])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(285[10] 287[8])
+    defparam mux_103_i7_3_lut.init = 16'hcaca;
+    LUT4 i1757_2_lut_4_lut (.A(n1865), .B(bitTimer[5]), .C(q7), .D(bitTimer[0]), 
+         .Z(n1733)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (D))+!A (D))) */ ;
+    defparam i1757_2_lut_4_lut.init = 16'h00f7;
+    LUT4 i20_4_lut (.A(n1775), .B(data_out_7), .C(n142), .D(n14), .Z(buffer_7__N_49[7])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;
+    defparam i20_4_lut.init = 16'hcfca;
+    LUT4 i673_1_lut_rep_31 (.A(q7), .Z(n1873)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam i673_1_lut_rep_31.init = 16'h5555;
+    LUT4 iwmDataOut_7__I_0_i6_4_lut_4_lut (.A(q7), .B(n1863), .C(\romOutput[5] ), 
+         .D(n229[5]), .Z(\data_7__N_1[5] )) /* synthesis lut_function=(A (B (C))+!A (B (C)+!B (D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam iwmDataOut_7__I_0_i6_4_lut_4_lut.init = 16'hd1c0;
+    LUT4 iwmDataOut_7__I_0_i3_4_lut_4_lut (.A(q7), .B(n1863), .C(\romOutput[2] ), 
+         .D(n229[2]), .Z(\data_7__N_1[2] )) /* synthesis lut_function=(A (B (C))+!A (B (C)+!B (D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam iwmDataOut_7__I_0_i3_4_lut_4_lut.init = 16'hd1c0;
+    LUT4 iwmDataOut_7__I_0_i2_4_lut_4_lut (.A(q7), .B(n1863), .C(\romOutput[1] ), 
+         .D(n229[1]), .Z(\data_7__N_1[1] )) /* synthesis lut_function=(A (B (C))+!A (B (C)+!B (D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam iwmDataOut_7__I_0_i2_4_lut_4_lut.init = 16'hd1c0;
+    LUT4 i1_3_lut_4_lut_adj_27 (.A(clearBufferTimer[0]), .B(n1872), .C(n7), 
+         .D(\buffer[7] ), .Z(n14)) /* synthesis lut_function=(A (D)+!A !(B (C+!(D))+!B !(D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(195[10:34])
+    defparam i1_3_lut_4_lut_adj_27.init = 16'hbf00;
+    LUT4 i983_3_lut_4_lut (.A(bitTimer[2]), .B(n1870), .C(n1859), .D(bitTimer[3]), 
+         .Z(n277)) /* synthesis lut_function=(A (B (C+!(D))+!B (C+(D)))+!A (C+(D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(227[19:34])
+    defparam i983_3_lut_4_lut.init = 16'hf7f8;
+    LUT4 iwmDataOut_7__I_0_i1_4_lut_4_lut (.A(q7), .B(n1863), .C(\romOutput[0] ), 
+         .D(n229[0]), .Z(\data_7__N_1[0] )) /* synthesis lut_function=(A (B (C))+!A (B (C)+!B (D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(44[8] 63[6])
+    defparam iwmDataOut_7__I_0_i1_4_lut_4_lut.init = 16'hd1c0;
+    LUT4 i1731_2_lut_3_lut (.A(addr_c_1), .B(addr_c_3), .C(addr_c_2), 
+         .Z(_devsel_N_40_enable_3)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1731_2_lut_3_lut.init = 16'h4040;
+    LUT4 i1729_2_lut_3_lut (.A(addr_c_1), .B(addr_c_3), .C(addr_c_2), 
+         .Z(_devsel_N_40_enable_4)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(45[4] 62[11])
+    defparam i1729_2_lut_3_lut.init = 16'h0404;
+    LUT4 i1_3_lut_3_lut_4_lut (.A(rddataSync[1]), .B(rddataSync[0]), .C(q6), 
+         .D(q7), .Z(n2)) /* synthesis lut_function=(!(A (B (C+!(D))+!B (C))+!A (C+!(D)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(205[9:39])
+    defparam i1_3_lut_3_lut_4_lut.init = 16'h0f02;
+    LUT4 mux_79_i5_4_lut_4_lut_4_lut (.A(writeBufferEmpty), .B(\buffer[4] ), 
+         .C(shifter[3]), .D(n1871), .Z(n229_adj_150[4])) /* synthesis lut_function=(!(A ((D)+!C)+!A !(B (C+(D))+!B !((D)+!C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam mux_79_i5_4_lut_4_lut_4_lut.init = 16'h44f0;
+    LUT4 mux_79_i3_4_lut_4_lut_4_lut (.A(writeBufferEmpty), .B(buffer[2]), 
+         .C(shifter[1]), .D(n1871), .Z(n229_adj_150[2])) /* synthesis lut_function=(!(A ((D)+!C)+!A !(B (C+(D))+!B !((D)+!C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam mux_79_i3_4_lut_4_lut_4_lut.init = 16'h44f0;
+    LUT4 i243_2_lut (.A(clearBufferTimer[1]), .B(clearBufferTimer[0]), .Z(n68[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(200[27:50])
+    defparam i243_2_lut.init = 16'h6666;
+    LUT4 n514_bdd_4_lut (.A(n514), .B(shifter[0]), .C(n229_adj_150[1]), 
+         .D(n163), .Z(shifter_7__N_100[1])) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
+    defparam n514_bdd_4_lut.init = 16'h88f0;
+    LUT4 mux_79_i6_4_lut_4_lut_4_lut (.A(writeBufferEmpty), .B(buffer[5]), 
+         .C(shifter[4]), .D(n1871), .Z(n229_adj_150[5])) /* synthesis lut_function=(!(A ((D)+!C)+!A !(B (C+(D))+!B !((D)+!C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam mux_79_i6_4_lut_4_lut_4_lut.init = 16'h44f0;
+    LUT4 i1_4_lut_adj_28 (.A(n440_c), .B(n163), .C(n1868), .D(n9), .Z(fclk_c_enable_14)) /* synthesis lut_function=(A ((C (D))+!B)) */ ;
+    defparam i1_4_lut_adj_28.init = 16'ha222;
+    LUT4 mux_79_i7_4_lut_4_lut_4_lut (.A(writeBufferEmpty), .B(buffer[6]), 
+         .C(shifter[5]), .D(n1871), .Z(n229_adj_150[6])) /* synthesis lut_function=(!(A ((D)+!C)+!A !(B (C+(D))+!B !((D)+!C)))) */ ;   // c:/users/chamberlin/documents/liron/lattice/iwm.v(183[8] 289[6])
+    defparam mux_79_i7_4_lut_4_lut_4_lut.init = 16'h44f0;
+    PFUMX i1761 (.BLUT(n1876), .ALUT(n1877), .C0(q7), .Z(shifter_7__N_100[0]));
+    
+endmodule
+//
+// Verilog Description of module PUR
+// module not written out since it is a black-box. 
+//
+
+//
+// Verilog Description of module codeROM
+//
+
+module codeROM (addr_c_11, addr_c_10, addr_c_9, addr_c_8, addr_c_7, 
+            addr_c_6, addr_c_5, addr_c_4, addr_c_3, addr_c_2, addr_c_1, 
+            addr_c_0, fclk_c, VCC_net, GND_net, romOutput) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;
+    input addr_c_11;
+    input addr_c_10;
+    input addr_c_9;
+    input addr_c_8;
+    input addr_c_7;
+    input addr_c_6;
+    input addr_c_5;
+    input addr_c_4;
+    input addr_c_3;
+    input addr_c_2;
+    input addr_c_1;
+    input addr_c_0;
+    input fclk_c;
+    input VCC_net;
+    input GND_net;
+    output [7:0]romOutput;
+    
+    wire fclk_c /* synthesis SET_AS_NETWORK=fclk_c, is_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(5[8:12])
+    
+    DP8KC codeROM_0_0_3_0 (.DIA0(GND_net), .DIA1(GND_net), .DIA2(GND_net), 
+          .DIA3(GND_net), .DIA4(GND_net), .DIA5(GND_net), .DIA6(GND_net), 
+          .DIA7(GND_net), .DIA8(GND_net), .ADA0(GND_net), .ADA1(addr_c_0), 
+          .ADA2(addr_c_1), .ADA3(addr_c_2), .ADA4(addr_c_3), .ADA5(addr_c_4), 
+          .ADA6(addr_c_5), .ADA7(addr_c_6), .ADA8(addr_c_7), .ADA9(addr_c_8), 
+          .ADA10(addr_c_9), .ADA11(addr_c_10), .ADA12(addr_c_11), .CEA(VCC_net), 
+          .OCEA(VCC_net), .CLKA(fclk_c), .WEA(GND_net), .CSA0(GND_net), 
+          .CSA1(GND_net), .CSA2(GND_net), .RSTA(GND_net), .DIB0(GND_net), 
+          .DIB1(GND_net), .DIB2(GND_net), .DIB3(GND_net), .DIB4(GND_net), 
+          .DIB5(GND_net), .DIB6(GND_net), .DIB7(GND_net), .DIB8(GND_net), 
+          .ADB0(GND_net), .ADB1(GND_net), .ADB2(GND_net), .ADB3(GND_net), 
+          .ADB4(GND_net), .ADB5(GND_net), .ADB6(GND_net), .ADB7(GND_net), 
+          .ADB8(GND_net), .ADB9(GND_net), .ADB10(GND_net), .ADB11(GND_net), 
+          .ADB12(GND_net), .CEB(VCC_net), .OCEB(VCC_net), .CLKB(GND_net), 
+          .WEB(GND_net), .CSB0(GND_net), .CSB1(GND_net), .CSB2(GND_net), 
+          .RSTB(GND_net), .DOA0(romOutput[6]), .DOA1(romOutput[7])) /* synthesis MEM_LPC_FILE="codeROM.lpc", MEM_INIT_FILE="rom-full-4k.mem", syn_instantiated=1, LSE_LINE_FILE_ID=3, LSE_LCOL=10, LSE_RCOL=3, LSE_LLINE=91, LSE_RLINE=97 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(91[10] 97[3])
+    defparam codeROM_0_0_3_0.DATA_WIDTH_A = 2;
+    defparam codeROM_0_0_3_0.DATA_WIDTH_B = 2;
+    defparam codeROM_0_0_3_0.REGMODE_A = "OUTREG";
+    defparam codeROM_0_0_3_0.REGMODE_B = "NOREG";
+    defparam codeROM_0_0_3_0.CSDECODE_A = "0b000";
+    defparam codeROM_0_0_3_0.CSDECODE_B = "0b111";
+    defparam codeROM_0_0_3_0.WRITEMODE_A = "NORMAL";
+    defparam codeROM_0_0_3_0.WRITEMODE_B = "NORMAL";
+    defparam codeROM_0_0_3_0.GSR = "ENABLED";
+    defparam codeROM_0_0_3_0.RESETMODE = "SYNC";
+    defparam codeROM_0_0_3_0.ASYNC_RESET_RELEASE = "SYNC";
+    defparam codeROM_0_0_3_0.INIT_DATA = "STATIC";
+    defparam codeROM_0_0_3_0.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECF1FEBF1FEBE1FEFE1FEFF";
+    defparam codeROM_0_0_3_0.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    defparam codeROM_0_0_3_0.INITVAL_02 = "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422";
+    defparam codeROM_0_0_3_0.INITVAL_03 = "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467";
+    defparam codeROM_0_0_3_0.INITVAL_04 = "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422";
+    defparam codeROM_0_0_3_0.INITVAL_05 = "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467";
+    defparam codeROM_0_0_3_0.INITVAL_06 = "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422";
+    defparam codeROM_0_0_3_0.INITVAL_07 = "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467";
+    defparam codeROM_0_0_3_0.INITVAL_08 = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422";
+    defparam codeROM_0_0_3_0.INITVAL_09 = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67";
+    defparam codeROM_0_0_3_0.INITVAL_0A = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422";
+    defparam codeROM_0_0_3_0.INITVAL_0B = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67";
+    defparam codeROM_0_0_3_0.INITVAL_0C = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422";
+    defparam codeROM_0_0_3_0.INITVAL_0D = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67";
+    defparam codeROM_0_0_3_0.INITVAL_0E = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422";
+    defparam codeROM_0_0_3_0.INITVAL_0F = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67";
+    defparam codeROM_0_0_3_0.INITVAL_10 = "0x130BC09AB91C2BE176861C66F042BC10CF319E1B19E21164EB170DB15C2E16A3E01C8B15CB80583C";
+    defparam codeROM_0_0_3_0.INITVAL_11 = "0x03641136A80DA060DCA112ED707A060DCA116819174861A0661D4191209712E3D00C661D63A0D06E";
+    defparam codeROM_0_0_3_0.INITVAL_12 = "0x1D6AC036460C4660CC6218AFF086FF0F4E819C881808E05CBD074F317885174CE142B506ED00CCEA";
+    defparam codeROM_0_0_3_0.INITVAL_13 = "0x13EBC0583C0DCBA182651D63A142791EC92098E9118E813059128361929608C4C1D0BF1E4CE116AC";
+    defparam codeROM_0_0_3_0.INITVAL_14 = "0x1E4BB10ECA05C08110881108810482104821002A1002A10000054AA1300113CBA1D6AC03CBA182FF";
+    defparam codeROM_0_0_3_0.INITVAL_15 = "0x04E3314C630DA0000000000411E6DB01E0816838132C11F8F604C1911CC00CC3910C8E0C4A60328E";
+    defparam codeROM_0_0_3_0.INITVAL_16 = "0x0324C12866052990CAF90A8D91B8CD0AEE50BE8D1126C0DE0D12EE60643507C2410298136E61F294";
+    defparam codeROM_0_0_3_0.INITVAL_17 = "0x03211130431201A17A490CE27032C909ED004C2913E0E0DCAE0F4E90E4610324C128011302602C65";
+    defparam codeROM_0_0_3_0.INITVAL_18 = "0x0523E0CE6F10C620CC2E090D81329B1366604C1911CF400C6E02431000000DE0818AD31669B06A89";
+    defparam codeROM_0_0_3_0.INITVAL_19 = "0x06C620C8F9100660CC6604C2E0E698158AC1588F06C331CE48130B6076E604CBD110EF096C2066F7";
+    defparam codeROM_0_0_3_0.INITVAL_1A = "0x0DA381DC191128D100660642D034991328C110CF0AE2512885152881983E0CC660CCD300CA60CC66";
+    defparam codeROM_0_0_3_0.INITVAL_1B = "0x04C590CAA718C00110101A419034381C6D90429A06633066220E40111C39130C8182860C69800C63";
+    defparam codeROM_0_0_3_0.INITVAL_1C = "0x1E08B18C000D8861908E0349903439122B41D46512C4E0CCF61A617058181309F00CA604C6604C26";
+    defparam codeROM_0_0_3_0.INITVAL_1D = "0x1FEBF1FCF31FCFF1FEBB1E6FF176C71FE0F1C4330463206698110B0044E419E2305C3800C000C608";
+    defparam codeROM_0_0_3_0.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00086FE1F6FE1E6FF";
+    defparam codeROM_0_0_3_0.INITVAL_1F = "0x1E0FE17EAF1FEFB1FEAA156BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    DP8KC codeROM_0_0_1_2 (.DIA0(GND_net), .DIA1(GND_net), .DIA2(GND_net), 
+          .DIA3(GND_net), .DIA4(GND_net), .DIA5(GND_net), .DIA6(GND_net), 
+          .DIA7(GND_net), .DIA8(GND_net), .ADA0(GND_net), .ADA1(addr_c_0), 
+          .ADA2(addr_c_1), .ADA3(addr_c_2), .ADA4(addr_c_3), .ADA5(addr_c_4), 
+          .ADA6(addr_c_5), .ADA7(addr_c_6), .ADA8(addr_c_7), .ADA9(addr_c_8), 
+          .ADA10(addr_c_9), .ADA11(addr_c_10), .ADA12(addr_c_11), .CEA(VCC_net), 
+          .OCEA(VCC_net), .CLKA(fclk_c), .WEA(GND_net), .CSA0(GND_net), 
+          .CSA1(GND_net), .CSA2(GND_net), .RSTA(GND_net), .DIB0(GND_net), 
+          .DIB1(GND_net), .DIB2(GND_net), .DIB3(GND_net), .DIB4(GND_net), 
+          .DIB5(GND_net), .DIB6(GND_net), .DIB7(GND_net), .DIB8(GND_net), 
+          .ADB0(GND_net), .ADB1(GND_net), .ADB2(GND_net), .ADB3(GND_net), 
+          .ADB4(GND_net), .ADB5(GND_net), .ADB6(GND_net), .ADB7(GND_net), 
+          .ADB8(GND_net), .ADB9(GND_net), .ADB10(GND_net), .ADB11(GND_net), 
+          .ADB12(GND_net), .CEB(VCC_net), .OCEB(VCC_net), .CLKB(GND_net), 
+          .WEB(GND_net), .CSB0(GND_net), .CSB1(GND_net), .CSB2(GND_net), 
+          .RSTB(GND_net), .DOA0(romOutput[2]), .DOA1(romOutput[3])) /* synthesis MEM_LPC_FILE="codeROM.lpc", MEM_INIT_FILE="rom-full-4k.mem", syn_instantiated=1, LSE_LINE_FILE_ID=3, LSE_LCOL=10, LSE_RCOL=3, LSE_LLINE=91, LSE_RLINE=97 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(91[10] 97[3])
+    defparam codeROM_0_0_1_2.DATA_WIDTH_A = 2;
+    defparam codeROM_0_0_1_2.DATA_WIDTH_B = 2;
+    defparam codeROM_0_0_1_2.REGMODE_A = "OUTREG";
+    defparam codeROM_0_0_1_2.REGMODE_B = "NOREG";
+    defparam codeROM_0_0_1_2.CSDECODE_A = "0b000";
+    defparam codeROM_0_0_1_2.CSDECODE_B = "0b111";
+    defparam codeROM_0_0_1_2.WRITEMODE_A = "NORMAL";
+    defparam codeROM_0_0_1_2.WRITEMODE_B = "NORMAL";
+    defparam codeROM_0_0_1_2.GSR = "ENABLED";
+    defparam codeROM_0_0_1_2.RESETMODE = "SYNC";
+    defparam codeROM_0_0_1_2.ASYNC_RESET_RELEASE = "SYNC";
+    defparam codeROM_0_0_1_2.INIT_DATA = "STATIC";
+    defparam codeROM_0_0_1_2.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEC314034116201AA84082C9";
+    defparam codeROM_0_0_1_2.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    defparam codeROM_0_0_1_2.INITVAL_02 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000";
+    defparam codeROM_0_0_1_2.INITVAL_03 = "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95";
+    defparam codeROM_0_0_1_2.INITVAL_04 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000";
+    defparam codeROM_0_0_1_2.INITVAL_05 = "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95";
+    defparam codeROM_0_0_1_2.INITVAL_06 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000";
+    defparam codeROM_0_0_1_2.INITVAL_07 = "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95";
+    defparam codeROM_0_0_1_2.INITVAL_08 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000";
+    defparam codeROM_0_0_1_2.INITVAL_09 = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95";
+    defparam codeROM_0_0_1_2.INITVAL_0A = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000";
+    defparam codeROM_0_0_1_2.INITVAL_0B = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95";
+    defparam codeROM_0_0_1_2.INITVAL_0C = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000";
+    defparam codeROM_0_0_1_2.INITVAL_0D = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95";
+    defparam codeROM_0_0_1_2.INITVAL_0E = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000";
+    defparam codeROM_0_0_1_2.INITVAL_0F = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95";
+    defparam codeROM_0_0_1_2.INITVAL_10 = "0x1882818473092231C0F9188DA0146805A92094260940A0843E01E881FC401D6A2086C0164E80922C";
+    defparam codeROM_0_0_1_2.INITVAL_11 = "0x10C180A0F203061086C80D4F509061086C80C2B501E2D10CD4078B4088AA06A480DA4907C0F124D3";
+    defparam codeROM_0_0_1_2.INITVAL_12 = "0x078F9008A9024550AA12178AA11E3C01E0E006D2160A2106E011EA2150A809E831D06F012860283C";
+    defparam codeROM_0_0_1_2.INITVAL_13 = "0x010AC11628002C31601107C0F040F30C8200303C0D03C028950AC4D19044114E807A10164831E038";
+    defparam codeROM_0_0_1_2.INITVAL_14 = "0x1E0A2106C2094011000000000000000000000000000000000000000014AA082C70183B002C3160CA";
+    defparam codeROM_0_0_1_2.INITVAL_15 = "0x04A4004A501BE01000900089018CE6194030406914886182B919A6F0B68117A6F0B69B130AD0DE5B";
+    defparam codeROM_0_0_1_2.INITVAL_16 = "0x16C6814C490565602889024350A80102424094D30945B1C04A0CCFD0C06D14E491347506CF915A56";
+    defparam codeROM_0_0_1_2.INITVAL_17 = "0x15426150A61406A15CC01320D16C430D0A60120A088E31C6E919E2C0A0561286010C031244504A55";
+    defparam codeROM_0_0_1_2.INITVAL_18 = "0x0D6B303018104481280F1840412A521241400A690B4FC0341A04042054AA03E09034E40CCA605062";
+    defparam codeROM_0_0_1_2.INITVAL_19 = "0x0029213CCC082B90A45D05AA802CE610690140A210A861FECA120A40DC24092910902C196C210889";
+    defparam codeROM_0_0_1_2.INITVAL_1A = "0x03E2C09615082A00E2A918C49048B70AA50012031EA090A8A9052020243302A550A8921922112295";
+    defparam codeROM_0_0_1_2.INITVAL_1B = "0x0CA960306A09000000080546A0D46A1188600CA601C4A1144C040461C46A0E8390125B0ACD503698";
+    defparam codeROM_0_0_1_2.INITVAL_1C = "0x050D2082AA128821B21B0DCA40DC6E08CB914C180CA9A1324D106790903416CA61922504A2105221";
+    defparam codeROM_0_0_1_2.INITVAL_1D = "0x1F8120A8F2048700F8011E0C107C0D05E130E00E180A800CA4028B00A8AC0361803C3011CAA1308F";
+    defparam codeROM_0_0_1_2.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE08002F01A4241E251";
+    defparam codeROM_0_0_1_2.INITVAL_1F = "0x1E00C19C310A6C11801A010BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    DP8KC codeROM_0_0_0_3 (.DIA0(GND_net), .DIA1(GND_net), .DIA2(GND_net), 
+          .DIA3(GND_net), .DIA4(GND_net), .DIA5(GND_net), .DIA6(GND_net), 
+          .DIA7(GND_net), .DIA8(GND_net), .ADA0(GND_net), .ADA1(addr_c_0), 
+          .ADA2(addr_c_1), .ADA3(addr_c_2), .ADA4(addr_c_3), .ADA5(addr_c_4), 
+          .ADA6(addr_c_5), .ADA7(addr_c_6), .ADA8(addr_c_7), .ADA9(addr_c_8), 
+          .ADA10(addr_c_9), .ADA11(addr_c_10), .ADA12(addr_c_11), .CEA(VCC_net), 
+          .OCEA(VCC_net), .CLKA(fclk_c), .WEA(GND_net), .CSA0(GND_net), 
+          .CSA1(GND_net), .CSA2(GND_net), .RSTA(GND_net), .DIB0(GND_net), 
+          .DIB1(GND_net), .DIB2(GND_net), .DIB3(GND_net), .DIB4(GND_net), 
+          .DIB5(GND_net), .DIB6(GND_net), .DIB7(GND_net), .DIB8(GND_net), 
+          .ADB0(GND_net), .ADB1(GND_net), .ADB2(GND_net), .ADB3(GND_net), 
+          .ADB4(GND_net), .ADB5(GND_net), .ADB6(GND_net), .ADB7(GND_net), 
+          .ADB8(GND_net), .ADB9(GND_net), .ADB10(GND_net), .ADB11(GND_net), 
+          .ADB12(GND_net), .CEB(VCC_net), .OCEB(VCC_net), .CLKB(GND_net), 
+          .WEB(GND_net), .CSB0(GND_net), .CSB1(GND_net), .CSB2(GND_net), 
+          .RSTB(GND_net), .DOA0(romOutput[0]), .DOA1(romOutput[1])) /* synthesis MEM_LPC_FILE="codeROM.lpc", MEM_INIT_FILE="rom-full-4k.mem", syn_instantiated=1, LSE_LINE_FILE_ID=3, LSE_LCOL=10, LSE_RCOL=3, LSE_LLINE=91, LSE_RLINE=97 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(91[10] 97[3])
+    defparam codeROM_0_0_0_3.DATA_WIDTH_A = 2;
+    defparam codeROM_0_0_0_3.DATA_WIDTH_B = 2;
+    defparam codeROM_0_0_0_3.REGMODE_A = "OUTREG";
+    defparam codeROM_0_0_0_3.REGMODE_B = "NOREG";
+    defparam codeROM_0_0_0_3.CSDECODE_A = "0b000";
+    defparam codeROM_0_0_0_3.CSDECODE_B = "0b111";
+    defparam codeROM_0_0_0_3.WRITEMODE_A = "NORMAL";
+    defparam codeROM_0_0_0_3.WRITEMODE_B = "NORMAL";
+    defparam codeROM_0_0_0_3.GSR = "ENABLED";
+    defparam codeROM_0_0_0_3.RESETMODE = "SYNC";
+    defparam codeROM_0_0_0_3.ASYNC_RESET_RELEASE = "SYNC";
+    defparam codeROM_0_0_0_3.INIT_DATA = "STATIC";
+    defparam codeROM_0_0_0_3.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECE0FA0506A181206C0CE66";
+    defparam codeROM_0_0_0_3.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    defparam codeROM_0_0_0_3.INITVAL_02 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180501864309E5B04C020C20803C22";
+    defparam codeROM_0_0_0_3.INITVAL_03 = "0x160300301000E0902A28102000400C000560601D02E010E6380229B0E01008C6D18041032B70026E";
+    defparam codeROM_0_0_0_3.INITVAL_04 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180601864309E6B054021420803C22";
+    defparam codeROM_0_0_0_3.INITVAL_05 = "0x160300301000E0902A28102000400C000560601D02E01166380229B0E01008C6D18041032B70026E";
+    defparam codeROM_0_0_0_3.INITVAL_06 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180701864309E7B05C021C20803C22";
+    defparam codeROM_0_0_0_3.INITVAL_07 = "0x160300301000E0902A28102000400C000560601D02E011E6380229B0E01008C6D18041032B70026E";
+    defparam codeROM_0_0_0_3.INITVAL_08 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180401864309E4B044020420803C22";
+    defparam codeROM_0_0_0_3.INITVAL_09 = "0x160300301000E0902A28102000400C000560601D02E01066380229B0E01008C6D18041032B70026E";
+    defparam codeROM_0_0_0_3.INITVAL_0A = "0x100460DAC00821916E01008661B807140111367002AD516CA5180501864309E5B04C020C20803C22";
+    defparam codeROM_0_0_0_3.INITVAL_0B = "0x160300301000E0902A28102000400C000560601D02E010E6380229B0E01008C6D18041032B70026E";
+    defparam codeROM_0_0_0_3.INITVAL_0C = "0x100460DAC00821916E01008661B807140111367002AD516CA5180601864309E6B054021420803C22";
+    defparam codeROM_0_0_0_3.INITVAL_0D = "0x160300301000E0902A28102000400C000560601D02E01166380229B0E01008C6D18041032B70026E";
+    defparam codeROM_0_0_0_3.INITVAL_0E = "0x100460DAC00821916E01008661B807140111367002AD516CA5180701864309E7B05C021C20803C22";
+    defparam codeROM_0_0_0_3.INITVAL_0F = "0x160300301000E0902A28102000400C000560601D02E011E6380229B0E01008C6D18041032B70026E";
+    defparam codeROM_0_0_0_3.INITVAL_10 = "0x0A82706670008410E0251881400E500226110835108060C017004441BA410A800184600A67419228";
+    defparam codeROM_0_0_0_3.INITVAL_11 = "0x0E86A0C851122A512245080CE082A11224408CB608A1D03499028650AC4019C4114A9402E0008251";
+    defparam codeROM_0_0_0_3.INITVAL_12 = "0x048590684112AD5122110A0A919ECF00204004601624010250082400A09808AC00484419C1A1B214";
+    defparam codeROM_0_0_0_3.INITVAL_13 = "0x1101C11610002451601102E0002420002180D8050D80406856088C10804409ADC00C030C0C00C05C";
+    defparam codeROM_0_0_0_3.INITVAL_14 = "0x0A06210241094010800000000000000000000000000000000000000014A8084410481B0064D16048";
+    defparam codeROM_0_0_0_3.INITVAL_15 = "0x03C0403A5C15E241244902040000890881302005080C410022012C50C203032850A2010581918A61";
+    defparam codeROM_0_0_0_3.INITVAL_16 = "0x00A800341502014022C008A111341208A09036221085F0108B0ECD11B0D104A4606A5510C1D12C44";
+    defparam codeROM_0_0_0_3.INITVAL_17 = "0x0101809644088041123019C81006A0090BA1DC23080D20864E00A041D09D04A88030410C88D02A91";
+    defparam codeROM_0_0_0_3.INITVAL_18 = "0x0265D148D0012101220706429092441089108A840A233002E2130091B0A21AA05062DC0B04204078";
+    defparam codeROM_0_0_0_3.INITVAL_19 = "0x1121113A76160120325902A5C198800864108242194C1024C00884118E011848212E2500A41108C8";
+    defparam codeROM_0_0_0_3.INITVAL_1A = "0x1363C0121809242080101920B06C5614E8210C2118CC008C40090500061D14A51030A219A1D15C99";
+    defparam codeROM_0_0_0_3.INITVAL_1B = "0x0B4241A461086D51BEC10008408C44000040484209A4109AE8024401440402C3400A611A8640022C";
+    defparam codeROM_0_0_0_3.INITVAL_1C = "0x0409311AAA038091CA2100C48108441187602A9309231012450840A080240AA6A19A150229D13219";
+    defparam codeROM_0_0_0_3.INITVAL_1D = "0x15E1D120E31A04907C101C4E907A0100A220348D1501A10040108480DCA3060680522C024AA0301B";
+    defparam codeROM_0_0_0_3.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00020F8186D01C04D";
+    defparam codeROM_0_0_0_3.INITVAL_1F = "0x1E07417209022F10021108E3F1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    DP8KC codeROM_0_0_2_1 (.DIA0(GND_net), .DIA1(GND_net), .DIA2(GND_net), 
+          .DIA3(GND_net), .DIA4(GND_net), .DIA5(GND_net), .DIA6(GND_net), 
+          .DIA7(GND_net), .DIA8(GND_net), .ADA0(GND_net), .ADA1(addr_c_0), 
+          .ADA2(addr_c_1), .ADA3(addr_c_2), .ADA4(addr_c_3), .ADA5(addr_c_4), 
+          .ADA6(addr_c_5), .ADA7(addr_c_6), .ADA8(addr_c_7), .ADA9(addr_c_8), 
+          .ADA10(addr_c_9), .ADA11(addr_c_10), .ADA12(addr_c_11), .CEA(VCC_net), 
+          .OCEA(VCC_net), .CLKA(fclk_c), .WEA(GND_net), .CSA0(GND_net), 
+          .CSA1(GND_net), .CSA2(GND_net), .RSTA(GND_net), .DIB0(GND_net), 
+          .DIB1(GND_net), .DIB2(GND_net), .DIB3(GND_net), .DIB4(GND_net), 
+          .DIB5(GND_net), .DIB6(GND_net), .DIB7(GND_net), .DIB8(GND_net), 
+          .ADB0(GND_net), .ADB1(GND_net), .ADB2(GND_net), .ADB3(GND_net), 
+          .ADB4(GND_net), .ADB5(GND_net), .ADB6(GND_net), .ADB7(GND_net), 
+          .ADB8(GND_net), .ADB9(GND_net), .ADB10(GND_net), .ADB11(GND_net), 
+          .ADB12(GND_net), .CEB(VCC_net), .OCEB(VCC_net), .CLKB(GND_net), 
+          .WEB(GND_net), .CSB0(GND_net), .CSB1(GND_net), .CSB2(GND_net), 
+          .RSTB(GND_net), .DOA0(romOutput[4]), .DOA1(romOutput[5])) /* synthesis MEM_LPC_FILE="codeROM.lpc", MEM_INIT_FILE="rom-full-4k.mem", syn_instantiated=1, LSE_LINE_FILE_ID=3, LSE_LCOL=10, LSE_RCOL=3, LSE_LLINE=91, LSE_RLINE=97 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(91[10] 97[3])
+    defparam codeROM_0_0_2_1.DATA_WIDTH_A = 2;
+    defparam codeROM_0_0_2_1.DATA_WIDTH_B = 2;
+    defparam codeROM_0_0_2_1.REGMODE_A = "OUTREG";
+    defparam codeROM_0_0_2_1.REGMODE_B = "NOREG";
+    defparam codeROM_0_0_2_1.CSDECODE_A = "0b000";
+    defparam codeROM_0_0_2_1.CSDECODE_B = "0b111";
+    defparam codeROM_0_0_2_1.WRITEMODE_A = "NORMAL";
+    defparam codeROM_0_0_2_1.WRITEMODE_B = "NORMAL";
+    defparam codeROM_0_0_2_1.GSR = "ENABLED";
+    defparam codeROM_0_0_2_1.RESETMODE = "SYNC";
+    defparam codeROM_0_0_2_1.ASYNC_RESET_RELEASE = "SYNC";
+    defparam codeROM_0_0_2_1.INIT_DATA = "STATIC";
+    defparam codeROM_0_0_2_1.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECE158AA150BA15EBE176B8";
+    defparam codeROM_0_0_2_1.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    defparam codeROM_0_0_2_1.INITVAL_02 = "0x0200108AD11000500E46000141BA19108000A4740C826110041A28C02088106881844F048F30042A";
+    defparam codeROM_0_0_2_1.INITVAL_03 = "0x0603B0C2A9036C60326D00A2304A0D0301A1E86012646040C0000510E860002411A28000A3708C66";
+    defparam codeROM_0_0_2_1.INITVAL_04 = "0x0200108AD21000500E4A000141BA29108000A47414826110041A48C02088106881844F048F30042A";
+    defparam codeROM_0_0_2_1.INITVAL_05 = "0x0603B0C2A9056CA0526D00A2304A0D0501A1E8A01264A040C0000510E8A0002411A48000A3709466";
+    defparam codeROM_0_0_2_1.INITVAL_06 = "0x0200108AD31000500E4E000141BA39108000A4741C826110041A68C02088106881844F048F30042A";
+    defparam codeROM_0_0_2_1.INITVAL_07 = "0x0603B0C2A9076CE0726D00A2304A0D0701A1E8E01264E040C0000510E8E0002411A68000A3709C66";
+    defparam codeROM_0_0_2_1.INITVAL_08 = "0x0200108AD01000500E42000141BA09108000A47404826110041A08C02088106881844F048F30042A";
+    defparam codeROM_0_0_2_1.INITVAL_09 = "0x0603B0C2A9016C20126D00A2304A0D0101A1E82012642040C0000510E820002411A08000A3708466";
+    defparam codeROM_0_0_2_1.INITVAL_0A = "0x0200108AD11000500E46000141BA19108000A4740C826110041A28C02088106881844F048F30042A";
+    defparam codeROM_0_0_2_1.INITVAL_0B = "0x0603B0C2A9036C60326D00A2304A0D0301A1E86012646040C0000510E860002411A28000A3708C66";
+    defparam codeROM_0_0_2_1.INITVAL_0C = "0x0200108AD21000500E4A000141BA29108000A47414826110041A48C02088106881844F048F30042A";
+    defparam codeROM_0_0_2_1.INITVAL_0D = "0x0603B0C2A9056CA0526D00A2304A0D0501A1E8A01264A040C0000510E8A0002411A48000A3709466";
+    defparam codeROM_0_0_2_1.INITVAL_0E = "0x0200108AD31000500E4E000141BA39108000A4741C826110041A68C02088106881844F048F30042A";
+    defparam codeROM_0_0_2_1.INITVAL_0F = "0x0603B0C2A9076CE0726D00A2304A0D0701A1E8E01264E040C0000510E8E0002411A68000A3709C66";
+    defparam codeROM_0_0_2_1.INITVAL_10 = "0x090A1008A4002C00E8161CE2110086004180C2980C281168070821C03C20180F4060F8060CA0408A";
+    defparam codeROM_0_0_2_1.INITVAL_11 = "0x03021038100C0840E04114046020840E04110401182020100700808000A010C101007600E4308020";
+    defparam codeROM_0_0_2_1.INITVAL_12 = "0x01830120960944608C02064A80D8FC1060D1E0CF03084040741061810C80102D01C08C0600808E04";
+    defparam codeROM_0_0_2_1.INITVAL_13 = "0x15A0E0408E0C0C30140000E43042A400A0301A0C01A0C12099032B212000002ED018B4018D01B03D";
+    defparam codeROM_0_0_2_1.INITVAL_14 = "0x050B4050A202088100000000000000000000000000000000000000005001140C301831140C3034D0";
+    defparam codeROM_0_0_2_1.INITVAL_15 = "0x04C320486705E000020000022126581C68809434134530C8D60203801C081843011A4D0C4E00700E";
+    defparam codeROM_0_0_2_1.INITVAL_16 = "0x092BD030740409200AD10A8C9130C90AE450A4DC1106103230010700420209654112081007003A19";
+    defparam codeROM_0_0_2_1.INITVAL_17 = "0x000230D0930CE3E02206040321808413A080402815A600A0530060E0C2420B0BD012300BE2404C46";
+    defparam codeROM_0_0_2_1.INITVAL_18 = "0x0568B04A2D0027208E21008881221C138070483D01E0009E0A00600054A20448819AC1106D3080DB";
+    defparam codeROM_0_0_2_1.INITVAL_19 = "0x0240209C2C128F60844004029046DA12A9512C8C06410000201088107E4104C0415440010A202454";
+    defparam codeROM_0_0_2_1.INITVAL_1A = "0x0408E1669101084108F61A41212080010841104800C5903091192C90964B04824046380482008460";
+    defparam codeROM_0_0_2_1.INITVAL_1B = "0x04008040A8140000002C1CC3C07C3E1AC860465807038070A3004531BC35110680B08D0464909E65";
+    defparam codeROM_0_0_2_1.INITVAL_1C = "0x0809C140000DA010388D06C9206A35146701B4080408D0CCB2050C40208010098048240482004820";
+    defparam codeROM_0_0_2_1.INITVAL_1D = "0x0008008400084000808900214110830DC8C0FC180C282026D8140BA10CF009C21058B6004000C608";
+    defparam codeROM_0_0_2_1.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00082020304200010";
+    defparam codeROM_0_0_2_1.INITVAL_1F = "0x1E812150AE1FC8A178BF1D0BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
+    
+endmodule
+//
+// Verilog Description of module addrDecoder
+//
+
+module addrDecoder (n438_c, debugInfo_c_7, fclk_c, histrobe, n1905, 
+            n439_c, n1869, debugInfo_c_c, n1863, _devsel_c, _en245_N_19) /* synthesis syn_module_defined=1 */ ;
+    input n438_c;
+    output debugInfo_c_7;
+    input fclk_c;
+    input histrobe;
+    input n1905;
+    input n439_c;
+    output n1869;
+    input debugInfo_c_c;
+    output n1863;
+    input _devsel_c;
+    output _en245_N_19;
+    
+    wire fclk_c /* synthesis SET_AS_NETWORK=fclk_c, is_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(5[8:12])
+    wire _devsel_c /* synthesis is_clock=1 */ ;   // c:/users/chamberlin/documents/liron/lattice/top.v(11[8:15])
+    
+    wire _iosel_N_24;
+    
+    LUT4 _iosel_I_0_1_lut (.A(n438_c), .Z(_iosel_N_24)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/chamberlin/documents/liron/lattice/addrdecoder.v(35[20:27])
+    defparam _iosel_I_0_1_lut.init = 16'h5555;
+    FD1P3IX romExpansionActive_16 (.D(n1905), .SP(_iosel_N_24), .CD(histrobe), 
+            .CK(fclk_c), .Q(debugInfo_c_7));   // c:/users/chamberlin/documents/liron/lattice/addrdecoder.v(25[9] 33[5])
+    defparam romExpansionActive_16.GSR = "DISABLED";
+    LUT4 _romoe_I_5_3_lut_rep_27 (.A(n438_c), .B(debugInfo_c_7), .C(n439_c), 
+         .Z(n1869)) /* synthesis lut_function=(!(A ((C)+!B))) */ ;   // c:/users/chamberlin/documents/liron/lattice/addrdecoder.v(35[19:66])
+    defparam _romoe_I_5_3_lut_rep_27.init = 16'h5d5d;
+    LUT4 rw_I_0_2_lut_rep_21_4_lut (.A(n438_c), .B(debugInfo_c_7), .C(n439_c), 
+         .D(debugInfo_c_c), .Z(n1863)) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A !(D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/addrdecoder.v(35[19:66])
+    defparam rw_I_0_2_lut_rep_21_4_lut.init = 16'h5d00;
+    LUT4 i1726_2_lut_4_lut (.A(n438_c), .B(debugInfo_c_7), .C(n439_c), 
+         .D(_devsel_c), .Z(_en245_N_19)) /* synthesis lut_function=(A (B (C (D))+!B (D))) */ ;   // c:/users/chamberlin/documents/liron/lattice/addrdecoder.v(35[19:66])
+    defparam i1726_2_lut_4_lut.init = 16'ha200;
+    
+endmodule
diff --git a/lattice/fpgatop/xxx_lse_cp_file_list b/lattice/fpgatop/xxx_lse_cp_file_list
new file mode 100644
index 0000000..0f44e7b
--- /dev/null
+++ b/lattice/fpgatop/xxx_lse_cp_file_list
@@ -0,0 +1,181 @@
+3	 c:/users/chamberlin/documents/liron/lattice/top.v
+3	 c:/users/chamberlin/documents/liron/lattice/top.v
+3	 c:/users/chamberlin/documents/liron/lattice/top.v
+3	 c:/users/chamberlin/documents/liron/lattice/top.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
+5	 c:/users/chamberlin/documents/liron/lattice/iwm.v
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diff --git a/lattice/fpgatop/xxx_lse_sign_file b/lattice/fpgatop/xxx_lse_sign_file
new file mode 100644
index 0000000..91b4f4d
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+LSE_CPS_ID_171 "c:/users/chamberlin/documents/liron/lattice/top.v:91[10] 97[3]"
+LSE_CPS_ID_172 "c:/users/chamberlin/documents/liron/lattice/top.v:91[10] 97[3]"
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+LSE_CPS_ID_174 "c:/users/chamberlin/documents/liron/lattice/top.v:91[10] 97[3]"
+LSE_CPS_ID_175 "c:/users/chamberlin/documents/liron/lattice/top.v:91[10] 97[3]"
+LSE_CPS_ID_176 "c:/users/chamberlin/documents/liron/lattice/top.v:60[14] 68[3]"
+LSE_CPS_ID_177 "c:/users/chamberlin/documents/liron/lattice/addrdecoder.v:35[20:27]"
+LSE_CPS_ID_178 "c:/users/chamberlin/documents/liron/lattice/addrdecoder.v:25[9] 33[5]"
+LSE_CPS_ID_179 "c:/users/chamberlin/documents/liron/lattice/addrdecoder.v:35[19:66]"
+LSE_CPS_ID_180 "c:/users/chamberlin/documents/liron/lattice/addrdecoder.v:35[19:66]"
+LSE_CPS_ID_181 "c:/users/chamberlin/documents/liron/lattice/addrdecoder.v:35[19:66]"
diff --git a/lattice/generate_core.tcl b/lattice/generate_core.tcl
new file mode 100644
index 0000000..77a7ab0
--- /dev/null
+++ b/lattice/generate_core.tcl
@@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "codeROM"
+set lang "verilog"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "xo2c00"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
diff --git a/lattice/generate_ngd.tcl b/lattice/generate_ngd.tcl
new file mode 100644
index 0000000..0127bf9
--- /dev/null
+++ b/lattice/generate_ngd.tcl
@@ -0,0 +1,124 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "codeROM"
+set Para(Module) "ROM"
+set Para(libname) machxo2
+set Para(arch_name) xo2c00
+set Para(PartType) "LCMXO2-1200HC"
+
+set Para(tech_syn) machxo2
+set Para(tech_cae) machxo2
+set Para(Package) "TQFP100"
+set Para(SpeedGrade) "4"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#create LSE project file(*.synproj)
+proc CreateSynprojFile {} {
+	global Para
+
+	if [catch {open $Para(ModuleName).synproj w} synprojFile] {
+		puts "Cannot create LSE project file $Para(ModuleName).synproj."
+		exit -1
+	} else {
+		puts $synprojFile "-a \"$Para(tech_syn)\"
+-d $Para(PartType)
+-t $Para(Package)
+-s $Para(SpeedGrade)
+-frequency 200
+-optimization_goal Balanced
+-bram_utilization 100
+-ramstyle auto
+-romstyle auto
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr auto
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-use_io_insertion 0
+-resolve_mixed_drivers 0
+-use_io_reg 1
+
+-lpf 1
+-p $Para(sbp_path)
+-ver \"$Para(install_dir)/cae_library/synthesis/verilog/$Para(tech_cae).v\"
+\"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\"
+\"$Para(sbp_path)/$Para(ModuleName).v\"
+-top $Para(ModuleName)
+-ngo \"$Para(sbp_path)/$Para(ModuleName).ngo\"
+		"
+		close $synprojFile
+	}
+}
+
+#LSE
+CreateSynprojFile
+set ldcfile "$Para(sbp_path)/$Para(ModuleName).ldc"
+set synthesis "$Para(FPGAPath)/synthesis"
+if {[file exists $ldcfile] == 0} {
+	set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -gui} msg]
+} else {
+	set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -sdc \"$ldcfile\" -gui} msg]
+}
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
diff --git a/lattice/iwm.v b/lattice/iwm.v
new file mode 100644
index 0000000..e7ccc1c
--- /dev/null
+++ b/lattice/iwm.v
@@ -0,0 +1,296 @@
+`timescale 1 ns / 1 ps
+module iwm(
+	// bus interface
+    input [3:0] addr,			// A3-A1 selects one of 8 bits in the state register to be updated. A0 is the new state value. 
+								// A0 is also the /READ input, enables IWM to send the register selected by the state onto the data bus
+    input _devsel,				// Device enable: falling edge latches A3-A0. Rising edge of (Q3 or _devsel) qualifies write register data
+    input fclk, 				// Clock for serial communication, either 7 or 8 MHz (7 MHz on Apple II)
+    input q3, 					// 2 MHz non-symmetrical clock, used to qualify the timing of the serial data being written out for synchronous mode
+	input _reset,				// system reset
+    input [7:0] dataIn,			// Bidirectional data bus on a real IWM. Verilog model has separate input and output data ports.
+	output reg [7:0] dataOut,
+	// disk interface
+    output reg wrdata,			// serial data output - a transition occurs for each 1 bit
+    output reg [3:0] phase,		// programmable output, used in different ways depending on type of disk
+    output _wrreq,				// write request
+    output _enbl1,			   	// disk 1 enable
+    output _enbl2,				// disk 2 enable
+    input sense,				// input from disk, used for write protect or handshake, can be polled via status register
+    input rddata  				// serial data input - falling transition of each pulse is synchronized by IWM
+    );
+
+	// internal private state
+	//reg [4:0] mode; // we're ignoring all these
+	reg [7:0] shifter;
+	reg [7:0] buffer; // when Q6Q7 is 00, functions as read register. When Q7 is 1, write register.
+	reg motorOn;
+	reg driveSelect;
+	reg q6, q7;
+	reg _underrun;
+	reg writeBufferEmpty;
+	
+	// state pseudo-register
+	// the bits in this register are individually addressed by A3-A1
+	// The data on A0 is latched into the addressed state bit by /DEV low [the falling edge of /DEV latches information on A0-A3]
+	// All bits are reset to 0 by _reset low
+	always @(negedge _devsel or negedge _reset) begin
+		if (_reset == 0) begin
+			phase <= 4'b0000;
+			motorOn <= 0;
+			driveSelect <= 0;
+			q6 <= 0;
+			q7 <= 0;
+		end
+		else begin	
+			case (addr[3:1])
+				3'h0: // ph0
+					phase[0] <= addr[0];
+				3'h1: // ph1
+					phase[1] <= addr[0];
+				3'h2: // ph2
+					phase[2] <= addr[0];
+				3'h3: // ph3
+					phase[3] <= addr[0];
+				3'h4: // motor on	
+					motorOn <= addr[0];
+				3'h5: // drive select
+					driveSelect <= addr[0];
+				3'h6: // Q6 
+					q6 <= addr[0];
+				3'h7: // Q7 
+					q7 <= addr[0];
+			endcase
+		end
+	end
+	
+	// drive enable outputs are determined from motorOn and driveSelect
+	// no more than one enable may be low at a time
+	assign _enbl1 = ~(motorOn & ~driveSelect);
+	assign _enbl2 = ~(motorOn & driveSelect);
+	
+	// The combination of Q7 and Motor-On and /undderrun enable /wrreq low
+	assign _wrreq = ~(q7 & _underrun & (_enbl1 == 0 | _enbl2 == 0));
+	
+	/* IWM mode register: S C M H L
+	 (could save some macrocells here by assuming all the Apple II values)
+	 (all mode bits are reset to 0 by _reset low)
+ 	 S	Clock speed:
+			0 = 7 MHz (Apple II)
+			1 = 8 MHz (Macintosh)
+	 C	Bit cell time:
+			0 = 4 usec/bit (for 5.25 drives and Smartport) (Apple II)
+			1 = 2 usec/bit (for 3.5 drives) (Macintosh mode)
+	 M	Motor-off timer:
+			0 = leave drive on for 1 sec after program turns it off (Apple II)
+			1 = no delay (Macintosh mode)
+	 H	Handshake protocol:
+			0 = synchronous (software must supply proper timing for writing data) (Apple II)
+			1 = asynchronous (IWM supplies timing) (Macintosh Mode)
+			*In synchronous mode, the time of the Q7Q6 01 to 11 transition and every 8 Q3 periods (4 us)
+			thereafter, until Q7 is cleared, marks the beginning of a write window. The duration of the
+			write window is 4 periods of the Q3 input (2 us). The data written at the last write access
+			occurring within this write window will load the shift register with the data to be shifted
+			out. If the next write access has not occurred 32 us (64 Q3 period) after a load, the write 
+			will be extended in multiples of 4 us (8 Q3 periods) until another write access, and zeroes
+			will be shifted out. In synchronous mode, Q3 clock input is used internally to generate the
+			32 and 40 us timings, which would then be 64 and 80 Q3 clock periods in duration, respectively,
+			and the bit cell timings, 8 Q3 periods per bit cell time in slow mode.
+			*In asynchronous mode, the write shift register is buffered and, when the buffer is empty, the
+			iwm sets the MSB of the write-handhake register to a one to indicate that the next data nibble
+			can be written to the buffer. The buffer register may be written at any time during the write
+			state. Only the data last written into the buffer register, before the contents of the buffer
+			register is transferred to the write shift register, is used. In asynchronous mode CLK is used
+			to generate the bit cell timings. In fast mode CLK is equivalent to the clock input on FCLK. In 
+			slow mode CLK is equivalent to the clock input on FCLK
+			divided by two. Therefore, in 7M and slow mode the bit cell time will be 28 FCLK periods, in 8M
+			and slow mode the cell time will be 32 periods, and in 8M and
+			fast mode the cell time will be 16 periods. In asynchronous mode the write shift register is loaded
+			every 8 bit cell times starting seven clock periods after the write state begins.
+			*Normally data written to the IWM is sampled by the zero to one transition of the logial OR of
+			Q3 and /DEV. In asynchronous mode the Q3 input may be tied low.
+			*An underrun occurs when data has not been written to the buffer register between the time the
+			write-handshake bit indicates and empty buffer and the time the buffer is transferred to the 
+			write shift register. If an underrun occurs in asynchronous mode /WRREQ will be disabled and 
+			the underrun flag will be set to 0. This occurrance can be detected by reading the write-
+			handshake register before clearing the state bit Q7. Clearing the state bit Q7 will reset the
+			underrun flag.
+	 L	Latch mode (should be set in asynchronous mode):
+			0 = read-data stays valid for about 2 usec (Apple II)
+			1 = read-data stays valid for full byte time (Macintosh mode)
+			In latch mode, the MSB of the read data is latched internally during /DEV low. This internally
+			latched MSB is then used for the determination of a valid data read.
+	*/
+
+	/*    When reading serial data, a falling transition within a bit cell window is considered to be
+			a 1, and no falling transition within a window is a 0. The receive data input on RDDATA is
+			synchronized internally with the CLK clock. The synchronized falling transition is then discriminated
+			to the nearest bit cell window using the 7/8 MHz FCLK signal in fast mode and the FCLK signal
+			divided by two in slow mode. 
+			
+			In read state, data is shifted into the LSB of the shift register, and it shifts from LSB to
+			MSB. A full data nibble is considered to be shifted in when a 1 is shifted into the MSB. When
+			a full nibble is shifted in, the data will be latched by the read data register and the shift
+			register will be cleared to all zeroes.
+			
+			In synchronous mode, the shift register is readable in any intermediate state with this
+			exception: when a 1 is shifted into the MSB, the shift register will appear, to the data bus,
+			to be stalled for a period of two bit times plus four CLK periods. This is to allow the host
+			processor time to poll the MSB to determine when data is valid. In asynchronous mode the data
+			register will latch the shift register when a one is shifted into the MSB and will be cleared
+			14 FCLK periods (about 2 us) after a valid data read takes place (a valid data read being 
+			defined as both /DEV being low and D7 (the MSB) outputting a 1 from the data register for at
+			least one FCLK period.
+	*/
+	
+	// read registers
+	// Q7 Q6 Moton-On   Operation
+	// 0  0  0          read all 1's
+	// 0  0  1          read data register				Read
+	// 0  1  x          read status register			Write-protect sense
+	// 1  0  x          read write-handshake reg 	Write
+	always @(*) begin
+		case ({q7,q6}) 
+			2'b00: // data-in register (from disk drive) - MSB is 1 when data is valid. Reads all 1's if motor is off.
+				dataOut <= buffer;
+			2'b01: // IWM status register 
+				dataOut <= { sense, 1'b0, motorOn, 5'b00111 /*mode*/ }; 
+			default: // 2'b10 handshake register
+				dataOut <= { writeBufferEmpty, _underrun, 6'b000000 };
+		endcase
+	end
+		
+	// Mode and data register writes, disk serial I/O
+	// this assumes the mode register SCMHL is 00111
+	reg [1:0] rddataSync;
+	always @(posedge fclk) begin
+		rddataSync <= { rddataSync[0], rddata };
+	end
+	
+	wire q3orDev = q3 | _devsel;
+	reg [5:0] bitTimer; // max value 42
+	reg [2:0] bitCounter; // max value 7
+	reg [3:0] clearBufferTimer; // max value 14
+	always @(posedge fclk or negedge _reset) begin
+		if (_reset == 0) begin
+			_underrun <= 1'b1;
+			writeBufferEmpty <= 1'b1;
+			bitCounter <= 0;
+			buffer <= 0;
+			clearBufferTimer <= 0;
+			wrdata <= 0;
+			//mode <= 5'b00000;
+		end
+		else begin
+			// READ FROM DISK
+			if (q7 == 0 && q6 == 0) begin
+				
+				if (clearBufferTimer == 0) begin
+					// if the timer isn't already running and there is a valid read from the data buffer?
+					if (_devsel == 0 && addr[0] == 0 && buffer[7] == 1'b1) begin
+						clearBufferTimer <= 1; // start the timer
+					end
+				end
+				else begin
+					// have about 2 us elapsed since the last valid read from the buffer?
+					if (clearBufferTimer == 4'hE /* 14 FCLK periods */) begin
+						buffer[7] <= 0; // only the MSB really needs to be cleared. Saves some CPLD logic vs clearing the whole buffer.
+						clearBufferTimer <= 0; // stop the timer
+					end
+					else begin
+						clearBufferTimer <= clearBufferTimer + 1'b1;
+					end
+				end
+								
+				// was there a falling transition on rddata?
+				if (rddataSync[1] & ~rddataSync[0]) begin
+					// has at least half a bit cell time elpased since the last cell boundary?
+					// don't shift any bits if the clock count was less than half a bit cell time
+					if (bitTimer >= 14) begin 
+						shifter <= { shifter[6:0], 1'b1 }; // shift in a 1 bit				
+					end
+					
+					bitTimer <= 0;
+				end
+				else begin
+					// have one and a half bit cell times elapsed?
+					if (bitTimer >= 42) begin
+						shifter <= { shifter[6:0], 1'b0 }; // shift in a 0 bit				
+						bitTimer <= 14; // reset to half bit cell time
+					end
+					else begin					
+						// has a complete byte been shifted in?
+						if (shifter[7] == 1) begin
+							buffer <= shifter; // latch the byte
+							shifter <= 0; // clear the byte from the shifter
+						end
+													
+						bitTimer <= bitTimer + 1'b1;	
+					end	
+				end
+			end
+			// WRITE TO DISK
+			if (q7 == 1'b1) begin
+				
+				// is it time for a new bit?
+				if (bitTimer == 28) begin
+					bitTimer <= 0;
+					// is the entire byte done?
+					if (bitCounter == 7) begin
+						bitCounter <= 0;
+						// is there a new byte ready?
+						if (writeBufferEmpty == 0) begin
+							// move the next byte into the shifter
+							shifter <= buffer;
+							writeBufferEmpty <= 1'b1;						
+						end
+						else begin
+							_underrun <= 0; // error						
+						end		
+					end
+					else begin
+						// there are still more bits remaining, so shift the next bit
+						bitCounter <= bitCounter + 1'b1;
+						shifter <= { shifter[6:0], 1'b0 }; // left shift
+					end
+				end
+				else begin
+					bitTimer <= bitTimer + 1'b1;
+				end
+				
+				// wrdata transition at start of a bit cell indicates a logical 1 bit
+				if (bitTimer == 1 && shifter[7] == 1) begin
+					wrdata <= ~wrdata;
+				end		
+			end
+			else begin
+				_underrun <= 1; // clear error when Q7 is 0
+			end
+			
+			// WRITE REGISTERS
+			// a register is written when both Q6 and Q7 are set or are being set, and A0 is 1	
+			// Q7 Q6 Moton-On   Operation
+			// 1  1  0          write mode register			Mode Set
+			// 1  1  1          write data register			Write Load
+			// The IWM spec says register writes are qualified by the rising edge of (Q3 or _devsel),
+			// but that's a problem for buffer and writeBufferEmpty, which would then need to be clocked
+			// by both FCLK and (Q3 or _devsel). Instead we'll perform a register write at any FCLK
+			// edge when (Q3 or _devsel) is low, treating it like a load enable. A review of timing 
+			// diagrams looks like this will work.
+			if (q3orDev == 0 && q7 && q6 && addr[0]) begin
+				if (motorOn) begin
+					buffer <= dataIn; // data for disk write
+					writeBufferEmpty <= 0;
+					writeBufferEmpty <= 0;
+				end
+				else begin
+					//mode <= data[4:0];
+				end
+			end
+		end
+	end
+	
+	// TODO: clear read buffer after a valid read
+	
+	// TODO: clear shifter at start of a read operation?
+	// TODO: set writeBufferEmpty at start of a write?
+endmodule
\ No newline at end of file
diff --git a/lattice/liron.ccl b/lattice/liron.ccl
new file mode 100644
index 0000000..dcf391b
--- /dev/null
+++ b/lattice/liron.ccl
@@ -0,0 +1 @@
+VERSION=20110520
diff --git a/lattice/liron.ldf b/lattice/liron.ldf
new file mode 100644
index 0000000..414eac2
--- /dev/null
+++ b/lattice/liron.ldf
@@ -0,0 +1,29 @@
+
+
+    
+    
+        
+        
+            
+        
+        
+            
+        
+        
+            
+        
+        
+            
+        
+        
+            
+        
+        
+            
+        
+        
+            
+        
+    
+    
+
diff --git a/lattice/liron.lpf b/lattice/liron.lpf
new file mode 100644
index 0000000..c983028
--- /dev/null
+++ b/lattice/liron.lpf
@@ -0,0 +1,109 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+IOBUF PORT "_devsel" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
+LOCATE COMP "spi_mosi" SITE "49" ;
+LOCATE COMP "spi_clk" SITE "31" ;
+LOCATE COMP "spi_cs" SITE "27" ;
+PROHIBIT SITE "48" ;
+LOCATE COMP "spi_miso" SITE "32" ;
+IOBUF PORT "fclk" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "_iosel" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "_iostrobe" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "_reset" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[8]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[9]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[10]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "addr[11]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "q3" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "rddata" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "rw" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "sense" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "spi_miso" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "_en245" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "_enbl1" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "_enbl2" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "_wrreq" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "debugInfo[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "debugInfo[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "debugInfo[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "debugInfo[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "debugInfo[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "debugInfo[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "debugInfo[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "debugInfo[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "phase[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "phase[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "phase[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "phase[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "wrdata" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "spi_clk" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "spi_cs" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "spi_mosi" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "data[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=8 ;
+IOBUF PORT "data[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=8 ;
+IOBUF PORT "data[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=8 ;
+IOBUF PORT "data[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=8 ;
+IOBUF PORT "data[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=8 ;
+IOBUF PORT "data[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=8 ;
+IOBUF PORT "data[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=8 ;
+IOBUF PORT "data[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=8 ;
+PROHIBIT SITE "61" ;
+IOBUF PORT "_en35" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "select" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+## IOBUF ALLPORTS ;
+LOCATE COMP "_enbl2" SITE "99" ;
+LOCATE COMP "_en35" SITE "98" ;
+LOCATE COMP "_wrreq" SITE "88" ;
+LOCATE COMP "phase[3]" SITE "87" ;
+LOCATE COMP "phase[2]" SITE "86" ;
+LOCATE COMP "phase[1]" SITE "85" ;
+LOCATE COMP "phase[0]" SITE "84" ;
+LOCATE COMP "wrdata" SITE "83" ;
+LOCATE COMP "_enbl1" SITE "82" ;
+LOCATE COMP "select" SITE "78" ;
+LOCATE COMP "rddata" SITE "96" ;
+LOCATE COMP "sense" SITE "97" ;
+LOCATE COMP "_reset" SITE "75" ;
+LOCATE COMP "_iostrobe" SITE "74" ;
+LOCATE COMP "fclk" SITE "63" ;
+LOCATE COMP "rw" SITE "71" ;
+LOCATE COMP "q3" SITE "70" ;
+LOCATE COMP "addr[11]" SITE "69" ;
+LOCATE COMP "addr[10]" SITE "68" ;
+LOCATE COMP "addr[9]" SITE "67" ;
+LOCATE COMP "addr[8]" SITE "66" ;
+LOCATE COMP "addr[7]" SITE "65" ;
+LOCATE COMP "addr[6]" SITE "64" ;
+LOCATE COMP "addr[5]" SITE "62" ;
+LOCATE COMP "addr[4]" SITE "60" ;
+LOCATE COMP "addr[3]" SITE "59" ;
+LOCATE COMP "addr[2]" SITE "58" ;
+LOCATE COMP "addr[1]" SITE "57" ;
+LOCATE COMP "addr[0]" SITE "54" ;
+LOCATE COMP "_iosel" SITE "53" ;
+LOCATE COMP "data[7]" SITE "52" ;
+LOCATE COMP "data[6]" SITE "51" ;
+LOCATE COMP "data[5]" SITE "47" ;
+LOCATE COMP "data[4]" SITE "39" ;
+LOCATE COMP "data[0]" SITE "35" ;
+LOCATE COMP "data[1]" SITE "36" ;
+LOCATE COMP "data[2]" SITE "37" ;
+LOCATE COMP "data[3]" SITE "38" ;
+LOCATE COMP "_devsel" SITE "34" ;
+LOCATE COMP "_en245" SITE "30" ;
+LOCATE COMP "debugInfo[0]" SITE "12" ;
+LOCATE COMP "debugInfo[1]" SITE "13" ;
+LOCATE COMP "debugInfo[2]" SITE "14" ;
+LOCATE COMP "debugInfo[3]" SITE "15" ;
+LOCATE COMP "debugInfo[4]" SITE "16" ;
+LOCATE COMP "debugInfo[5]" SITE "17" ;
+LOCATE COMP "debugInfo[6]" SITE "24" ;
+LOCATE COMP "debugInfo[7]" SITE "25" ;
diff --git a/lattice/liron1.sty b/lattice/liron1.sty
new file mode 100644
index 0000000..763418b
--- /dev/null
+++ b/lattice/liron1.sty
@@ -0,0 +1,204 @@
+
+
+
+    
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diff --git a/lattice/liron_tcl.html b/lattice/liron_tcl.html
new file mode 100644
index 0000000..64c4356
--- /dev/null
+++ b/lattice/liron_tcl.html
@@ -0,0 +1,226 @@
+
+Lattice TCL Log
+
+
+
    pn170727130134
+#Start recording tcl command: 7/25/2017 21:29:37
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project new -name "liron" -impl "fpgatop" -dev LAMXO256C-3TN100E -synthesis "lse"
+prj_project save
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/top.v"
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v"
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/iwm.v"
+prj_run Synthesis -impl fpgatop
+prj_run Map -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop -task PARTrace
+prj_dev set -part LCMXO2-640HC-4TG100C
+prj_run PAR -impl fpgatop
+prj_dev set -part LAMXO256C-3TN100E
+prj_run PAR -impl fpgatop
+prj_dev set -part LCMXO2-640HC-4SG48C
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_dev set -part LCMXO2-640HC-4TG100C
+prj_src add -exclude "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+prj_src enable "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_project close
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v"
+prj_run PAR -impl fpgatop
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/codeROM.ipx"
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_src remove "C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v"
+prj_run PAR -impl fpgatop
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/spiFlash.ipx"
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_src remove "C:/Users/chamberlin/Documents/Liron/lattice/spiFlash.ipx"
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+#Stop recording: 7/27/2017 13:01:34
+
+
+
+pn170727162731
+#Start recording tcl command: 7/27/2017 13:02:05
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+pwc_command new
+pwc_command save -project "C:/Users/chamberlin/Documents/Liron/lattice/power-estimate.pcf"
+prj_src add -exclude "C:/Users/chamberlin/Documents/Liron/lattice/power-estimate.pcf"
+pwc_command save -project "C:/Users/chamberlin/Documents/Liron/lattice/power-estimate.pcf"
+prj_run PAR -impl fpgatop
+pwc_command exit
+pwc_command new
+prj_project save
+prj_project close
+#Stop recording: 7/27/2017 16:27:31
+
+
+
+pn170808144313
+#Start recording tcl command: 7/28/2017 10:04:36
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+prj_dev set -part LCMXO2-1200HC-4TG100C
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+pgr_project open "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+prj_run PAR -impl fpgatop
+pgr_project close
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+#Stop recording: 8/8/2017 14:43:13
+
+
+
+pn171208101159
+#Start recording tcl command: 12/7/2017 14:57:57
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+#Stop recording: 12/8/2017 10:11:59
+
+
+
+pn180117140835
+#Start recording tcl command: 1/17/2018 14:08:10
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+prj_project close
+#Stop recording: 1/17/2018 14:08:35
+
+
+
+pn180208150255
+#Start recording tcl command: 2/8/2018 14:57:30
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+pgr_project open "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_project save "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+prj_project close
+#Stop recording: 2/8/2018 15:02:55
+
+
+
+pn180214123353
+#Start recording tcl command: 2/8/2018 15:05:17
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+C:/Users/chamberlin/Documents/Liron
+yellowstone_blink
+#Start recording tcl command: 2/14/2018 12:33:53
+#Project Location: C:/Users/chamberlin/Documents/Liron; Project name: yellowstone_blink
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+pgr_project open "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pwc_command new
+pwc_command exit
+prj_run Export -impl fpgatop
+pgr_program run
+pgr_program run
+prj_run Export -impl fpgatop
+prj_run Export -impl fpgatop
+pgr_project save "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_project close
+pgr_project open "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_program run
+prj_run Export -impl fpgatop
+pgr_program run
+prj_run Export -impl fpgatop
+prj_run Export -impl fpgatop
+prj_run Export -impl fpgatop
+pgr_program run
+prj_run Export -impl fpgatop
+pgr_program run
+prj_run Export -impl fpgatop
+pgr_program run
+pgr_project save "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+prj_project save
+prj_project close
+prj_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink.ldf"
+#Stop recording: 2/14/2018 12:33:53
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
+
diff --git a/lattice/liron_tcr.dir/pn170727130134.tcr b/lattice/liron_tcr.dir/pn170727130134.tcr
new file mode 100644
index 0000000..3adfb64
--- /dev/null
+++ b/lattice/liron_tcr.dir/pn170727130134.tcr
@@ -0,0 +1,40 @@
+#Start recording tcl command: 7/25/2017 21:29:37
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project new -name "liron" -impl "fpgatop" -dev LAMXO256C-3TN100E -synthesis "lse"
+prj_project save
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/top.v"
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v"
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/iwm.v"
+prj_run Synthesis -impl fpgatop
+prj_run Map -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop -task PARTrace
+prj_dev set -part LCMXO2-640HC-4TG100C
+prj_run PAR -impl fpgatop
+prj_dev set -part LAMXO256C-3TN100E
+prj_run PAR -impl fpgatop
+prj_dev set -part LCMXO2-640HC-4SG48C
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_dev set -part LCMXO2-640HC-4TG100C
+prj_src add -exclude "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+prj_src enable "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_project close
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v"
+prj_run PAR -impl fpgatop
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/codeROM.ipx"
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_src remove "C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v"
+prj_run PAR -impl fpgatop
+prj_src add "C:/Users/chamberlin/Documents/Liron/lattice/spiFlash.ipx"
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_src remove "C:/Users/chamberlin/Documents/Liron/lattice/spiFlash.ipx"
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+#Stop recording: 7/27/2017 13:01:34
diff --git a/lattice/liron_tcr.dir/pn170727162731.tcr b/lattice/liron_tcr.dir/pn170727162731.tcr
new file mode 100644
index 0000000..422775d
--- /dev/null
+++ b/lattice/liron_tcr.dir/pn170727162731.tcr
@@ -0,0 +1,21 @@
+#Start recording tcl command: 7/27/2017 13:02:05
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+pwc_command new
+pwc_command save -project "C:/Users/chamberlin/Documents/Liron/lattice/power-estimate.pcf"
+prj_src add -exclude "C:/Users/chamberlin/Documents/Liron/lattice/power-estimate.pcf"
+pwc_command save -project "C:/Users/chamberlin/Documents/Liron/lattice/power-estimate.pcf"
+prj_run PAR -impl fpgatop
+pwc_command exit
+pwc_command new
+prj_project save
+prj_project close
+#Stop recording: 7/27/2017 16:27:31
diff --git a/lattice/liron_tcr.dir/pn170808144313.tcr b/lattice/liron_tcr.dir/pn170808144313.tcr
new file mode 100644
index 0000000..87ea51e
--- /dev/null
+++ b/lattice/liron_tcr.dir/pn170808144313.tcr
@@ -0,0 +1,16 @@
+#Start recording tcl command: 7/28/2017 10:04:36
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+prj_dev set -part LCMXO2-1200HC-4TG100C
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+pgr_project open "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+prj_run PAR -impl fpgatop
+pgr_project close
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+prj_run PAR -impl fpgatop
+#Stop recording: 8/8/2017 14:43:13
diff --git a/lattice/liron_tcr.dir/pn171208101159.tcr b/lattice/liron_tcr.dir/pn171208101159.tcr
new file mode 100644
index 0000000..de5f225
--- /dev/null
+++ b/lattice/liron_tcr.dir/pn171208101159.tcr
@@ -0,0 +1,4 @@
+#Start recording tcl command: 12/7/2017 14:57:57
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+#Stop recording: 12/8/2017 10:11:59
diff --git a/lattice/liron_tcr.dir/pn180117140835.tcr b/lattice/liron_tcr.dir/pn180117140835.tcr
new file mode 100644
index 0000000..6735c71
--- /dev/null
+++ b/lattice/liron_tcr.dir/pn180117140835.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 1/17/2018 14:08:10
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+prj_project close
+#Stop recording: 1/17/2018 14:08:35
diff --git a/lattice/liron_tcr.dir/pn180208150255.tcr b/lattice/liron_tcr.dir/pn180208150255.tcr
new file mode 100644
index 0000000..fc88266
--- /dev/null
+++ b/lattice/liron_tcr.dir/pn180208150255.tcr
@@ -0,0 +1,12 @@
+#Start recording tcl command: 2/8/2018 14:57:30
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+pgr_project open "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_project save "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+prj_project close
+#Stop recording: 2/8/2018 15:02:55
diff --git a/lattice/liron_tcr.dir/pn180214123353.tcr b/lattice/liron_tcr.dir/pn180214123353.tcr
new file mode 100644
index 0000000..04252f4
--- /dev/null
+++ b/lattice/liron_tcr.dir/pn180214123353.tcr
@@ -0,0 +1,39 @@
+#Start recording tcl command: 2/8/2018 15:05:17
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+C:/Users/chamberlin/Documents/Liron
+yellowstone_blink
+#Start recording tcl command: 2/14/2018 12:33:53
+#Project Location: C:/Users/chamberlin/Documents/Liron; Project name: yellowstone_blink
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+pgr_project open "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pwc_command new
+pwc_command exit
+prj_run Export -impl fpgatop
+pgr_program run
+pgr_program run
+prj_run Export -impl fpgatop
+prj_run Export -impl fpgatop
+pgr_project save "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_project close
+pgr_project open "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+pgr_program run
+prj_run Export -impl fpgatop
+pgr_program run
+prj_run Export -impl fpgatop
+prj_run Export -impl fpgatop
+prj_run Export -impl fpgatop
+pgr_program run
+prj_run Export -impl fpgatop
+pgr_program run
+prj_run Export -impl fpgatop
+pgr_program run
+pgr_project save "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/fpgatop.xcf"
+prj_project save
+prj_project close
+prj_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink.ldf"
+#Stop recording: 2/14/2018 12:33:53
diff --git a/lattice/power-estimate.pcf b/lattice/power-estimate.pcf
new file mode 100644
index 0000000..0ed9b2e
--- /dev/null
+++ b/lattice/power-estimate.pcf
@@ -0,0 +1,470 @@
+[[Info]]
+_PARENT: none
+_FAMILY: xo2c00
+_FILE_FORMAT: 1.00
+_DATA_VALUES: 1.00
+_STATUS: Advanced
+
+[[Project]]
+DesignName: top
+Family: MachXO2
+Device: LCMXO2-640HC
+Package: TQFP100
+Operating: Commercial
+Version: 8.0
+Performance: -4
+PartName: LCMXO2-640HC-4TG100C
+
+[[Settings]]
+EstimationMode: Medium
+ProcessType: Typical
+SoftwareMode: Calculation
+TempAmbX: Ambient Temperature
+SectionY: Total Power
+SectionX: Vcc
+SectionLowerLimit: 0.0000
+SectionUpperLimit: 0.0000
+SectionResolution: 0.0000
+TempAmbY: Ambient Temperature
+TempAmbLowerLimit: -30.0000
+TempAmbUpperLimit: 115.0000
+TempAmbResolution: 29.0000
+FreqY: Total Power
+FreqX: No Clocks Found!
+FreqLowerLimit: 10.0000
+FreqUpperLimit: 100.0000
+FreqAmbResolution: 20.0000
+PowerMode: Normal
+DisableBandgap: false
+DisablePor: false
+DisableDll: false
+DisableOsc: false
+DisablePLL0: false
+DisablePLL1: false
+DisableInRd0: false
+DisableInRd1: false
+DisableInRd2: false
+DisableInRd3: false
+DisableInRd4: false
+DisableInRd5: false
+DisableInRd6: false
+DisableInRd7: false
+EnablePg0: false
+EnablePg1: false
+EnablePg2: false
+EnablePg3: false
+EnablePg4: false
+EnablePg5: false
+EnablePg6: false
+EnablePg7: false
+DisableLVDS: false
+DisableLVDS1: false
+DisableLVDS2: false
+DisableLVDS3: false
+DisableLVDS4: false
+DisableLVDS5: false
+DisableLVDS6: false
+DisableLVDS7: false
+
+[[Thermal]]
+Airflow: 200 LFM
+AmbientTemperature: 25
+CustomThetaSA: -1
+JunctionTemperature: 25.19
+MaxSafeAmbient: 84.67
+ThetaBA: 10.0
+ThetaCS: 0
+ThetaEffective: 16.65
+ThetaJA: 20.59
+ThetaJB: 12.88
+ThetaJC: 0
+ThetaSA: -1
+UserThetaBA: No
+UserThetaCS: No
+UserThetaEffective: No
+UserThetaJA: No
+UserThetaJB: No
+UserThetaJC: No
+UserThetaSA: No
+thetaBoard: Medium Board
+thetaHeatSink: No Heat Sink
+thetaOption: ThermalModels
+
+[[VDPM]]
+Supply = Voltage, DPM
+Vcc = 3.300, 1.00
+Vccio 3.3 = 3.300, 1.00
+Vccio 2.5 = 2.500, 1.00
+Vccio 1.8 = 1.800, 1.00
+Vccio 1.5 = 1.500, 1.00
+Vccio 1.2 = 1.200, 1.00
+
+[[Logic]]
+Clk = F, AF, LUT, RAM, RIPPLE, REG, X0, X1, X2, X6, ISB, ISBLUT, ISBCE, ISBLSR, ISBM, ISBCLK
+COMBINATORIAL = 7.0000, 10.0000^d^, 56, 0, 0, 0, 59, 23, 123, 31, 119, 70, 16, 6, 9, 2
+_devsel_c = 1.0000, 10.0000^d^, 15, 0, 0, 8, 18, 18, 55, 9, 61, 49, 8, 3, 1, 8
+fclk_c = 7.0000, 10.0000^d^, 43, 0, 0, 35, 50, 25, 66, 18, 301, 290, 5, 5, 1, 23
+
+[[Clocks]]
+Clk = F, Duty, Pfeed, Ptrunk, Pspine, Ptap, Pbranch, Strunk, Sspine, Stap, Sbranch, Etb, Ebg, Elr
+_devsel_c = 1.0000, 50.0000, 0, 0, 0, 0, 0, t4_1, c13_1, r4_2, b_10, 0, 0, 0
+fclk_c = 7.0000, 50.0000, 0, t3_1, s13_1, p13_1_p17_1, c14_4_c17_4, 0, 0, 0, b_0, 0, 0, 0
+
+[[Input Output]]
+Clk = _Type, _Mode, F, AF, IP, OP, PG, Cload, Bank, _ActualMode, _Pull, X0, X1, X2, X6, ISB
+COMBINATORIAL = LVCMOS25, none, 7.0000, 10.0000^d^, 4, 0, OFF, 5, 2, none, DOWN, 0, 0, 0, 0, 0
+COMBINATORIAL = LVCMOS25, none, 7.0000, 10.0000^d^, 11, 0, OFF, 5, 1, none, DOWN, 0, 0, 0, 0, 0
+COMBINATORIAL = LVCMOS25, none, 7.0000, 10.0000^d^, 5, 0, OFF, 5, 0, none, DOWN, 0, 0, 0, 0, 0
+COMBINATORIAL = LVCMOS25-8mA-SLEW:SLOW, none, 7.0000, 10.0000^d^, 0, 2, N/A, 5, 2, none, DOWN, 0, 0, 0, 0, 0
+_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 0, 1, N/A, 5, 1, none, DOWN, 0, 0, 0, 0, 0
+_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 0, 2, N/A, 5, 0, none, DOWN, 0, 0, 0, 0, 0
+_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 0, 4, N/A, 5, 3, none, DOWN, 0, 0, 0, 0, 0
+_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 0, 10, N/A, 5, 2, none, DOWN, 0, 0, 0, 0, 0
+_devsel_c = LVCMOS25, none, 1.0000, 10.0000^d^, 1, 0, OFF, 5, 3, none, UP, 0, 0, 0, 0, 0
+fclk_c = LVCMOS25-8mA-SLEW:SLOW, none, 7.0000, 10.0000^d^, 0, 1, N/A, 5, 0, none, DOWN, 0, 0, 0, 0, 0
+fclk_c = LVCMOS25, none, 7.0000, 10.0000^d^, 1, 0, OFF, 5, 2, none, DOWN, 0, 0, 0, 0, 0
+
+[[Bidi]]
+ClkInpName = _Type, _Mode, InpF, InpAF, Bidi, PG, ClkOutName, OutF, OutAF, Duty, Cload, Bank, _ActualMode, _Pull, X0, X1, X2, X6, ISB
+COMBINATORIAL = LVCMOS25-8mA-SLEW:SLOW, none, 7.0000, 10.0000^d^, 5, OFF, N/A, 0.0000^d^, 10.0000^d^, 50, 5, 1, none, DOWN, 0, 0, 0, 0, 0
+_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 3, OFF, N/A, 0.0000^d^, 10.0000^d^, 50, 5, 1, none, DOWN, 0, 0, 0, 0, 0
+
+[[Bank Voltage]]
+Bank = Voltage, InRD, LVDSO, PG
+0 = Vccio 2.5, No, No, OFF
+1 = Vccio 2.5, No, N/A, OFF
+2 = Vccio 2.5, No, N/A, OFF
+3 = Vccio 2.5, No, N/A, OFF
+
+[[Termination]]
+_Type = IP, OP, Bidi, Duty, Bank, Rth, Vth
+LVCMOS25 = 5, 0, 0, 0.0, 2, 1.0E12, 0
+LVCMOS25 = 11, 0, 0, 0.0, 1, 1.0E12, 0
+LVCMOS25 = 5, 0, 0, 0.0, 0, 1.0E12, 0
+LVCMOS25-8mA-SLEW:SLOW = 0, 12, 0, 0.0, 2, 1.0E12, 0
+LVCMOS25-8mA-SLEW:SLOW = 0, 1, 8, 31.8, 1, 1.0E12, 0
+LVCMOS25-8mA-SLEW:SLOW = 0, 3, 0, 0.0, 0, 1.0E12, 0
+LVCMOS25-8mA-SLEW:SLOW = 0, 4, 0, 0.0, 3, 1.0E12, 0
+LVCMOS25 = 1, 0, 0, 0.0, 3, 1.0E12, 0
+
+[[SP RAM]]
+Clk = EBR, F, AF, _Type, X0, X1, X2, X6, ISB
+
+[[DP RAM]]
+RdClk = RdF, RdAF, EBR, WrClk, WrF, WrAF, _TypeA, _TypeB, X0, X1, X2, X6, ISB
+
+[[DP RAM True]]
+ClkA = aF, aAF, EBR, ClkB, bF, bAF, _TypeA, _TypeB, X0, X1, X2, X6, ISB
+fclk_c = 7.0000, 10.0000^d^, 2, NoNe, 0.0000^d^, 10.0000^d^, DP8KC_NORM_PORTA, DP8KC_NORM_PORTB, 0, 0, 0, 0, 0
+
+[[FIFO DC]]
+RdClk = RdF, RdAF, EBR, WrClk, WrF, WrAF, _TypeA, _TypeB, X0, X1, X2, X6, ISB
+
+[[I2C1]]
+Clk = F, AF, I2C1
+
+[[I2C2]]
+Clk = F, AF, I2C2
+
+[[SPI]]
+Clk = F, AF, SPI
+
+[[TC]]
+Clk = F, AF, TC, WBUSED
+
+[[UFM]]
+Clk = F, AF, UFM
+
+[[WISHBONE]]
+Clk = F, AF, WISHBONE
+
+[[CLKDIV]]
+Clk = F, AF, CLKDIV
+
+[[CIBTEST]]
+CIBTEST = 
+0 = 
+
+[[MCLK]]
+STANDBY = Clk, F, AF, MCLK, MCLKF, SEDF
+No = _CLKNAME, 266.0000, 100.0000, 1, 2.0800, 2.0800
+
+[[POR]]
+STANDBY = 
+No = 
+
+[[BANDGAP]]
+STANDBY = 
+No = 
+
+[[JTAG]]
+Clk = F, AF, Input, Output
+COMBINATORIAL = 7.0000, 100.0000, 3, 1
+
+[[SED]]
+_Mode = SED, STATUS
+SEDFA = 0, Disabled
+
+[[PLL Clock]]
+Out = In
+
+[[Connections]]
+Clock = Comp, Type
+COMBINATORIAL = myIwm/SLICE_31, 0
+COMBINATORIAL = data[5], 1
+COMBINATORIAL = data[3], 1
+COMBINATORIAL = data[2], 1
+COMBINATORIAL = data[1], 1
+COMBINATORIAL = data[0], 1
+COMBINATORIAL = _wrreq, 1
+COMBINATORIAL = debugInfo[0], 1
+_devsel_c = _devsel, 1
+_devsel_c = spi_clk, 1
+_devsel_c = spi_mosi, 1
+_devsel_c = spi_cs, 1
+_devsel_c = debugInfo[7], 1
+_devsel_c = debugInfo[6], 1
+_devsel_c = debugInfo[5], 1
+_devsel_c = debugInfo[4], 1
+_devsel_c = debugInfo[3], 1
+_devsel_c = debugInfo[2], 1
+_devsel_c = debugInfo[1], 1
+_devsel_c = _en245, 1
+_devsel_c = phase[0], 1
+_devsel_c = data[7], 1
+_devsel_c = data[6], 1
+_devsel_c = data[4], 1
+_devsel_c = phase[2], 1
+_devsel_c = phase[3], 1
+_devsel_c = _enbl1, 1
+_devsel_c = _enbl2, 1
+_devsel_c = phase[1], 1
+fclk_c = fclk, 1
+fclk_c = wrdata, 1
+
+[[Hierarchical Connections]]
+Key = Name, Type
+SIGNAL = COMBINATORIAL, DUMMY
+INPUT = myIwm/SLICE_31, SLICE
+INPUT = myIwm/SLICE_32, SLICE
+INPUT = myIwm/SLICE_34, SLICE
+INPUT = myIwm/SLICE_35, SLICE
+INPUT = SLICE_36, SLICE
+INPUT = myIwm/SLICE_37, SLICE
+INPUT = myIwm/SLICE_38, SLICE
+INPUT = myIwm/SLICE_40, SLICE
+INPUT = myIwm/SLICE_41, SLICE
+INPUT = myIwm/SLICE_42, SLICE
+INPUT = myIwm/SLICE_44, SLICE
+INPUT = myIwm/SLICE_45, SLICE
+INPUT = myIwm/SLICE_46, SLICE
+INPUT = myIwm/SLICE_47, SLICE
+INPUT = myIwm/SLICE_48, SLICE
+INPUT = SLICE_49, SLICE
+INPUT = myIwm/SLICE_50, SLICE
+INPUT = myIwm/SLICE_52, SLICE
+INPUT = myIwm/SLICE_54, SLICE
+INPUT = myIwm/SLICE_55, SLICE
+INPUT = myIwm/SLICE_56, SLICE
+INPUT = myIwm/SLICE_59, SLICE
+INPUT = myIwm/SLICE_60, SLICE
+INPUT = myIwm/SLICE_61, SLICE
+INPUT = myIwm/SLICE_62, SLICE
+INPUT = myIwm/SLICE_63, SLICE
+INPUT = myIwm/SLICE_64, SLICE
+INPUT = SLICE_65, SLICE
+INPUT = data[5], PIO
+INPUT = data[3], PIO
+INPUT = data[2], PIO
+INPUT = data[1], PIO
+INPUT = data[0], PIO
+INPUT = _wrreq, PIO
+INPUT = debugInfo[0], PIO
+INPUT = addr[11], PIO
+INPUT = addr[10], PIO
+INPUT = addr[9], PIO
+INPUT = addr[8], PIO
+INPUT = addr[7], PIO
+INPUT = addr[6], PIO
+INPUT = addr[5], PIO
+INPUT = addr[4], PIO
+INPUT = addr[3], PIO
+INPUT = addr[2], PIO
+INPUT = addr[1], PIO
+INPUT = addr[0], PIO
+INPUT = q3, PIO
+INPUT = rw, PIO
+INPUT = _iostrobe, PIO
+INPUT = _iosel, PIO
+INPUT = _reset, PIO
+INPUT = sense, PIO
+INPUT = rddata, PIO
+INPUT = spi_miso, PIO
+INPUT = GSR_INST, GSR
+SIGNAL = _devsel_c, DUMMY
+INPUT = _devsel, PIO
+OUTPUT = SLICE_27, SLICE
+OUTPORT = GND_net, F0
+OUTPORT = q6, Q0
+OUTPUT = spi_clk, PIO
+OUTPUT = spi_mosi, PIO
+OUTPUT = spi_cs, PIO
+OUTPUT = debugInfo[7], PIO
+OUTPUT = debugInfo[6], PIO
+OUTPUT = debugInfo[5], PIO
+OUTPUT = debugInfo[4], PIO
+OUTPUT = debugInfo[3], PIO
+OUTPUT = debugInfo[2], PIO
+OUTPUT = debugInfo[1], PIO
+OUTPUT = SLICE_28, SLICE
+OUTPORT = n1748, F0
+OUTPORT = q7, Q0
+OUTPORT = VCC_net, F1
+OUTPUT = _en245, PIO
+OUTPUT = SLICE_33, SLICE
+OUTPORT = n1717, F0
+OUTPORT = phase_c_0, Q0
+OUTPORT = data_7_N_1_7, F1
+OUTPUT = phase[0], PIO
+OUTPUT = data[7], PIO
+OUTPUT = SLICE_39, SLICE
+OUTPORT = iwmDataOut_6, F0
+OUTPORT = myIwm/motorOn, Q0
+OUTPORT = data_7_N_1_6, F1
+OUTPUT = data[6], PIO
+OUTPUT = SLICE_51, SLICE
+OUTPORT = data_7_N_1_4, F0
+OUTPORT = phase_c_2, Q0
+OUTPORT = n1740, F1
+OUTPUT = data[4], PIO
+OUTPUT = phase[2], PIO
+OUTPUT = myIwm/SLICE_57, SLICE
+OUTPORT = myIwm/fclk_c_enable_27, F0
+OUTPORT = phase_c_3, Q0
+OUTPORT = myIwm/fclk_c_enable_21, F1
+OUTPUT = phase[3], PIO
+OUTPUT = myIwm/SLICE_58, SLICE
+OUTPORT = _enbl1_N_121, F0
+OUTPORT = myIwm/driveSelect, Q0
+OUTPORT = _enbl2_N_125, F1
+OUTPUT = _enbl1, PIO
+OUTPUT = _enbl2, PIO
+OUTPUT = SLICE_66, SLICE
+OUTPORT = n1716, F0
+OUTPORT = phase_c_1, Q0
+OUTPORT = myIwm/n1733, F1
+OUTPUT = phase[1], PIO
+SIGNAL = fclk_c, DUMMY
+INPUT = fclk, PIO
+OUTPUT = myIwm/SLICE_0, SLICE
+OUTPORT = myIwm/buffer_7_N_46_3, F0
+OUTPORT = buffer_3, Q0
+OUTPORT = myIwm/buffer_7_N_46_4, F1
+OUTPORT = buffer_4, Q1
+OUTPUT = myIwm/SLICE_1, SLICE
+OUTPORT = myIwm/buffer_7_N_46_7, F0
+OUTPORT = buffer_7, Q0
+OUTPORT = myIwm/n11, F1
+OUTPUT = SLICE_2, SLICE
+OUTPORT = n1783, F0
+OUTPORT = myAddrDecoder/romActive, Q0
+OUTPUT = myIwm/SLICE_4, SLICE
+OUTPORT = myIwm/n20_adj_144, F0
+OUTPORT = myIwm/bitCounter_0, Q0
+OUTPORT = myIwm/n19, F1
+OUTPORT = myIwm/bitCounter_1, Q1
+OUTPUT = myIwm/SLICE_5, SLICE
+OUTPORT = myIwm/n18, F0
+OUTPORT = myIwm/bitCounter_2, Q0
+OUTPUT = myIwm/SLICE_6, SLICE
+OUTPORT = myIwm/n1598, F0
+OUTPORT = myIwm/bitTimer_0, Q0
+OUTPORT = myIwm/n1586, F1
+OUTPORT = myIwm/bitTimer_1, Q1
+OUTPUT = myIwm/SLICE_7, SLICE
+OUTPORT = myIwm/n258, F0
+OUTPORT = myIwm/bitTimer_2, Q0
+OUTPORT = myIwm/n259, F1
+OUTPORT = myIwm/bitTimer_3, Q1
+OUTPUT = myIwm/SLICE_8, SLICE
+OUTPORT = myIwm/n260, F0
+OUTPORT = myIwm/bitTimer_4, Q0
+OUTPORT = myIwm/n261, F1
+OUTPORT = myIwm/bitTimer_5, Q1
+OUTPUT = myIwm/SLICE_9, SLICE
+OUTPORT = myIwm/buffer_7_N_46_0, F0
+OUTPORT = myIwm/buffer_0, Q0
+OUTPORT = myIwm/buffer_7_N_46_1, F1
+OUTPORT = myIwm/buffer_1, Q1
+OUTPUT = myIwm/SLICE_10, SLICE
+OUTPORT = myIwm/buffer_7_N_46_2, F0
+OUTPORT = myIwm/buffer_2, Q0
+OUTPORT = myIwm/buffer_7_N_46_5, F1
+OUTPORT = myIwm/buffer_5, Q1
+OUTPUT = myIwm/SLICE_11, SLICE
+OUTPORT = myIwm/buffer_7_N_46_6, F0
+OUTPORT = myIwm/buffer_6, Q0
+OUTPUT = myIwm/SLICE_12, SLICE
+OUTPORT = myIwm/clearBufferTimer_3_N_67_0, F0
+OUTPORT = myIwm/clearBufferTimer_0, Q0
+OUTPORT = myIwm/n7, F1
+OUTPUT = myIwm/SLICE_13, SLICE
+OUTPORT = myIwm/n71, F0
+OUTPORT = myIwm/clearBufferTimer_1, Q0
+OUTPORT = myIwm/n70, F1
+OUTPORT = myIwm/clearBufferTimer_2, Q1
+OUTPUT = myIwm/SLICE_14, SLICE
+OUTPORT = myIwm/n69, F0
+OUTPORT = myIwm/clearBufferTimer_3, Q0
+OUTPORT = myIwm/n1750, F1
+OUTPUT = myIwm/SLICE_18, SLICE
+OUTPORT = myIwm/shifter_7_N_97_0, OFX0
+OUTPORT = myIwm/shifter_0, Q0
+OUTPUT = myIwm/SLICE_19, SLICE
+OUTPORT = myIwm/shifter_7_N_97_1, F0
+OUTPORT = myIwm/shifter_1, Q0
+OUTPORT = myIwm/shifter_7_N_97_2, F1
+OUTPORT = myIwm/shifter_2, Q1
+OUTPUT = myIwm/SLICE_20, SLICE
+OUTPORT = myIwm/shifter_7_N_97_3, F0
+OUTPORT = myIwm/shifter_3, Q0
+OUTPORT = myIwm/shifter_7_N_97_4, F1
+OUTPORT = myIwm/shifter_4, Q1
+OUTPUT = myIwm/SLICE_21, SLICE
+OUTPORT = myIwm/shifter_7_N_97_5, F0
+OUTPORT = myIwm/shifter_5, Q0
+OUTPORT = myIwm/shifter_7_N_97_6, F1
+OUTPORT = myIwm/shifter_6, Q1
+OUTPUT = myIwm/SLICE_22, SLICE
+OUTPORT = myIwm/shifter_7_N_97_7, F0
+OUTPORT = myIwm/shifter_7, Q0
+OUTPORT = myIwm/n230, F1
+OUTPUT = myIwm/SLICE_29, SLICE
+OUTPORT = myIwm/wrdata_N_112, F0
+OUTPORT = wrdata_c, Q0
+OUTPORT = myIwm/n8, F1
+OUTPUT = wrdata, PIO
+OUTPUT = myIwm/SLICE_30, SLICE
+OUTPORT = myIwm/writeBufferEmpty_N_136, F0
+OUTPORT = writeBufferEmpty, Q0
+OUTPORT = myIwm/n1735, F1
+OUTPUT = myIwm/SLICE_43, SLICE
+OUTPORT = myIwm/fclk_c_enable_30, F0
+OUTPORT = myIwm/rddataSync_0, Q0
+OUTPORT = n1744, F1
+OUTPORT = myIwm/rddataSync_1, Q1
+OUTPUT = myIwm/SLICE_53, SLICE
+OUTPORT = myIwm/_devsel_N_37_enable_3, F0
+OUTPORT = myIwm/_underrun, Q0
+OUTPORT = myIwm/_devsel_N_37_enable_4, F1
+OUTPUT = myROM/codeROM_0_0_1_0, EBR
+OUTPORT = romOutput_7, DOA3
+OUTPORT = romOutput_6, DOA2
+OUTPORT = romOutput_5, DOA1
+OUTPORT = romOutput_4, DOA0
+OUTPUT = myROM/codeROM_0_0_0_1, EBR
+OUTPORT = romOutput_3, DOA3
+OUTPORT = romOutput_2, DOA2
+OUTPORT = romOutput_1, DOA1
+OUTPORT = romOutput_0, DOA0
+
diff --git a/lattice/promote.xml b/lattice/promote.xml
new file mode 100644
index 0000000..2fec8f2
--- /dev/null
+++ b/lattice/promote.xml
@@ -0,0 +1,5 @@
+
+
+  
+  
+
diff --git a/lattice/reportview.xml b/lattice/reportview.xml
new file mode 100644
index 0000000..88eef79
--- /dev/null
+++ b/lattice/reportview.xml
@@ -0,0 +1,10 @@
+
+
+
+    
+        
+        
+        
+        
+    
+
diff --git a/lattice/spiFlash.edn b/lattice/spiFlash.edn
new file mode 100644
index 0000000..9ec9699
--- /dev/null
+++ b/lattice/spiFlash.edn
@@ -0,0 +1,628 @@
+(edif spiFlash
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2017 7 27 11 56 36)
+      (program "SCUBA" (version "Diamond (64-bit) 3.9.0.99.2"))))
+      (comment "C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n spiFlash -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -spi -spi_mode Both -spi_freq 16.6 -spi_cs 1 -wb -dev 640 ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell BB
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port I
+            (direction INPUT))
+          (port T
+            (direction INPUT))
+          (port O
+            (direction OUTPUT))
+          (port B
+            (direction INOUT)))))
+    (cell EFB
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port WBCLKI
+            (direction INPUT))
+          (port WBRSTI
+            (direction INPUT))
+          (port WBCYCI
+            (direction INPUT))
+          (port WBSTBI
+            (direction INPUT))
+          (port WBWEI
+            (direction INPUT))
+          (port WBADRI7
+            (direction INPUT))
+          (port WBADRI6
+            (direction INPUT))
+          (port WBADRI5
+            (direction INPUT))
+          (port WBADRI4
+            (direction INPUT))
+          (port WBADRI3
+            (direction INPUT))
+          (port WBADRI2
+            (direction INPUT))
+          (port WBADRI1
+            (direction INPUT))
+          (port WBADRI0
+            (direction INPUT))
+          (port WBDATI7
+            (direction INPUT))
+          (port WBDATI6
+            (direction INPUT))
+          (port WBDATI5
+            (direction INPUT))
+          (port WBDATI4
+            (direction INPUT))
+          (port WBDATI3
+            (direction INPUT))
+          (port WBDATI2
+            (direction INPUT))
+          (port WBDATI1
+            (direction INPUT))
+          (port WBDATI0
+            (direction INPUT))
+          (port PLL0DATI7
+            (direction INPUT))
+          (port PLL0DATI6
+            (direction INPUT))
+          (port PLL0DATI5
+            (direction INPUT))
+          (port PLL0DATI4
+            (direction INPUT))
+          (port PLL0DATI3
+            (direction INPUT))
+          (port PLL0DATI2
+            (direction INPUT))
+          (port PLL0DATI1
+            (direction INPUT))
+          (port PLL0DATI0
+            (direction INPUT))
+          (port PLL0ACKI
+            (direction INPUT))
+          (port PLL1DATI7
+            (direction INPUT))
+          (port PLL1DATI6
+            (direction INPUT))
+          (port PLL1DATI5
+            (direction INPUT))
+          (port PLL1DATI4
+            (direction INPUT))
+          (port PLL1DATI3
+            (direction INPUT))
+          (port PLL1DATI2
+            (direction INPUT))
+          (port PLL1DATI1
+            (direction INPUT))
+          (port PLL1DATI0
+            (direction INPUT))
+          (port PLL1ACKI
+            (direction INPUT))
+          (port I2C1SCLI
+            (direction INPUT))
+          (port I2C1SDAI
+            (direction INPUT))
+          (port I2C2SCLI
+            (direction INPUT))
+          (port I2C2SDAI
+            (direction INPUT))
+          (port SPISCKI
+            (direction INPUT))
+          (port SPIMISOI
+            (direction INPUT))
+          (port SPIMOSII
+            (direction INPUT))
+          (port SPISCSN
+            (direction INPUT))
+          (port TCCLKI
+            (direction INPUT))
+          (port TCRSTN
+            (direction INPUT))
+          (port TCIC
+            (direction INPUT))
+          (port UFMSN
+            (direction INPUT))
+          (port WBDATO7
+            (direction OUTPUT))
+          (port WBDATO6
+            (direction OUTPUT))
+          (port WBDATO5
+            (direction OUTPUT))
+          (port WBDATO4
+            (direction OUTPUT))
+          (port WBDATO3
+            (direction OUTPUT))
+          (port WBDATO2
+            (direction OUTPUT))
+          (port WBDATO1
+            (direction OUTPUT))
+          (port WBDATO0
+            (direction OUTPUT))
+          (port WBACKO
+            (direction OUTPUT))
+          (port PLLCLKO
+            (direction OUTPUT))
+          (port PLLRSTO
+            (direction OUTPUT))
+          (port PLL0STBO
+            (direction OUTPUT))
+          (port PLL1STBO
+            (direction OUTPUT))
+          (port PLLWEO
+            (direction OUTPUT))
+          (port PLLADRO4
+            (direction OUTPUT))
+          (port PLLADRO3
+            (direction OUTPUT))
+          (port PLLADRO2
+            (direction OUTPUT))
+          (port PLLADRO1
+            (direction OUTPUT))
+          (port PLLADRO0
+            (direction OUTPUT))
+          (port PLLDATO7
+            (direction OUTPUT))
+          (port PLLDATO6
+            (direction OUTPUT))
+          (port PLLDATO5
+            (direction OUTPUT))
+          (port PLLDATO4
+            (direction OUTPUT))
+          (port PLLDATO3
+            (direction OUTPUT))
+          (port PLLDATO2
+            (direction OUTPUT))
+          (port PLLDATO1
+            (direction OUTPUT))
+          (port PLLDATO0
+            (direction OUTPUT))
+          (port I2C1SCLO
+            (direction OUTPUT))
+          (port I2C1SCLOEN
+            (direction OUTPUT))
+          (port I2C1SDAO
+            (direction OUTPUT))
+          (port I2C1SDAOEN
+            (direction OUTPUT))
+          (port I2C2SCLO
+            (direction OUTPUT))
+          (port I2C2SCLOEN
+            (direction OUTPUT))
+          (port I2C2SDAO
+            (direction OUTPUT))
+          (port I2C2SDAOEN
+            (direction OUTPUT))
+          (port I2C1IRQO
+            (direction OUTPUT))
+          (port I2C2IRQO
+            (direction OUTPUT))
+          (port SPISCKO
+            (direction OUTPUT))
+          (port SPISCKEN
+            (direction OUTPUT))
+          (port SPIMISOO
+            (direction OUTPUT))
+          (port SPIMISOEN
+            (direction OUTPUT))
+          (port SPIMOSIO
+            (direction OUTPUT))
+          (port SPIMOSIEN
+            (direction OUTPUT))
+          (port SPIMCSN7
+            (direction OUTPUT))
+          (port SPIMCSN6
+            (direction OUTPUT))
+          (port SPIMCSN5
+            (direction OUTPUT))
+          (port SPIMCSN4
+            (direction OUTPUT))
+          (port SPIMCSN3
+            (direction OUTPUT))
+          (port SPIMCSN2
+            (direction OUTPUT))
+          (port SPIMCSN1
+            (direction OUTPUT))
+          (port SPIMCSN0
+            (direction OUTPUT))
+          (port SPICSNEN
+            (direction OUTPUT))
+          (port SPIIRQO
+            (direction OUTPUT))
+          (port TCINT
+            (direction OUTPUT))
+          (port TCOC
+            (direction OUTPUT))
+          (port WBCUFMIRQ
+            (direction OUTPUT))
+          (port CFGWAKE
+            (direction OUTPUT))
+          (port CFGSTDBY
+            (direction OUTPUT)))))
+    (cell spiFlash
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port wb_clk_i
+            (direction INPUT))
+          (port wb_rst_i
+            (direction INPUT))
+          (port wb_cyc_i
+            (direction INPUT))
+          (port wb_stb_i
+            (direction INPUT))
+          (port wb_we_i
+            (direction INPUT))
+          (port (array (rename wb_adr_i "wb_adr_i(7:0)") 8)
+            (direction INPUT))
+          (port (array (rename wb_dat_i "wb_dat_i(7:0)") 8)
+            (direction INPUT))
+          (port (array (rename wb_dat_o "wb_dat_o(7:0)") 8)
+            (direction OUTPUT))
+          (port wb_ack_o
+            (direction OUTPUT))
+          (port spi_clk
+            (direction INOUT))
+          (port spi_miso
+            (direction INOUT))
+          (port spi_mosi
+            (direction INOUT))
+          (port spi_scsn
+            (direction INPUT))
+          (port (array (rename spi_csn "spi_csn(0:0)") 1)
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance BBspi_mosi
+            (viewRef view1 
+              (cellRef BB)))
+          (instance BBspi_miso
+            (viewRef view1 
+              (cellRef BB)))
+          (instance BBspi_clk
+            (viewRef view1 
+              (cellRef BB)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance EFBInst_0
+            (viewRef view1 
+              (cellRef EFB))
+            (property UFM_INIT_FILE_FORMAT
+              (string "HEX"))
+            (property UFM_INIT_FILE_NAME
+              (string "NONE"))
+            (property UFM_INIT_ALL_ZEROS
+              (string "ENABLED"))
+            (property UFM_INIT_START_PAGE
+              (string "0"))
+            (property UFM_INIT_PAGES
+              (string "0"))
+            (property DEV_DENSITY
+              (string "640L"))
+            (property EFB_UFM
+              (string "DISABLED"))
+            (property TC_ICAPTURE
+              (string "DISABLED"))
+            (property TC_OVERFLOW
+              (string "DISABLED"))
+            (property TC_ICR_INT
+              (string "OFF"))
+            (property TC_OCR_INT
+              (string "OFF"))
+            (property TC_OV_INT
+              (string "OFF"))
+            (property TC_TOP_SEL
+              (string "OFF"))
+            (property TC_RESETN
+              (string "ENABLED"))
+            (property TC_OC_MODE
+              (string "TOGGLE"))
+            (property TC_OCR_SET
+              (string "32767"))
+            (property TC_TOP_SET
+              (string "65535"))
+            (property GSR
+              (string "ENABLED"))
+            (property TC_CCLK_SEL
+              (string "1"))
+            (property TC_MODE
+              (string "CTCM"))
+            (property TC_SCLK_SEL
+              (string "PCLOCK"))
+            (property EFB_TC_PORTMODE
+              (string "WB"))
+            (property EFB_TC
+              (string "DISABLED"))
+            (property SPI_WAKEUP
+              (string "DISABLED"))
+            (property SPI_INTR_RXOVR
+              (string "DISABLED"))
+            (property SPI_INTR_TXOVR
+              (string "DISABLED"))
+            (property SPI_INTR_RXRDY
+              (string "DISABLED"))
+            (property SPI_INTR_TXRDY
+              (string "DISABLED"))
+            (property SPI_SLAVE_HANDSHAKE
+              (string "DISABLED"))
+            (property SPI_PHASE_ADJ
+              (string "DISABLED"))
+            (property SPI_CLK_INV
+              (string "DISABLED"))
+            (property SPI_LSB_FIRST
+              (string "DISABLED"))
+            (property SPI_CLK_DIVIDER
+              (string "3"))
+            (property SPI_MODE
+              (string "BOTH"))
+            (property EFB_SPI
+              (string "ENABLED"))
+            (property I2C2_WAKEUP
+              (string "DISABLED"))
+            (property I2C2_GEN_CALL
+              (string "DISABLED"))
+            (property I2C2_CLK_DIVIDER
+              (string "1"))
+            (property I2C2_BUS_PERF
+              (string "100kHz"))
+            (property I2C2_SLAVE_ADDR
+              (string "0b1000010"))
+            (property I2C2_ADDRESSING
+              (string "7BIT"))
+            (property EFB_I2C2
+              (string "DISABLED"))
+            (property I2C1_WAKEUP
+              (string "DISABLED"))
+            (property I2C1_GEN_CALL
+              (string "DISABLED"))
+            (property I2C1_CLK_DIVIDER
+              (string "1"))
+            (property I2C1_BUS_PERF
+              (string "100kHz"))
+            (property I2C1_SLAVE_ADDR
+              (string "0b1000001"))
+            (property I2C1_ADDRESSING
+              (string "7BIT"))
+            (property EFB_I2C1
+              (string "DISABLED"))
+            (property EFB_WB_CLK_FREQ
+              (string "50.0")))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef UFMSN (instanceRef EFBInst_0))))
+          (net spi_mosi_oe
+            (joined
+              (portRef SPIMOSIEN (instanceRef EFBInst_0))
+              (portRef T (instanceRef BBspi_mosi))))
+          (net spi_mosi_o
+            (joined
+              (portRef SPIMOSIO (instanceRef EFBInst_0))
+              (portRef I (instanceRef BBspi_mosi))))
+          (net spi_miso_oe
+            (joined
+              (portRef SPIMISOEN (instanceRef EFBInst_0))
+              (portRef T (instanceRef BBspi_miso))))
+          (net spi_miso_o
+            (joined
+              (portRef SPIMISOO (instanceRef EFBInst_0))
+              (portRef I (instanceRef BBspi_miso))))
+          (net spi_clk_oe
+            (joined
+              (portRef SPISCKEN (instanceRef EFBInst_0))
+              (portRef T (instanceRef BBspi_clk))))
+          (net spi_clk_o
+            (joined
+              (portRef SPISCKO (instanceRef EFBInst_0))
+              (portRef I (instanceRef BBspi_clk))))
+          (net spi_mosi_i
+            (joined
+              (portRef SPIMOSII (instanceRef EFBInst_0))
+              (portRef O (instanceRef BBspi_mosi))))
+          (net spi_miso_i
+            (joined
+              (portRef SPIMISOI (instanceRef EFBInst_0))
+              (portRef O (instanceRef BBspi_miso))))
+          (net spi_clk_i
+            (joined
+              (portRef SPISCKI (instanceRef EFBInst_0))
+              (portRef O (instanceRef BBspi_clk))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef PLL1DATI7 (instanceRef EFBInst_0))
+              (portRef PLL1DATI6 (instanceRef EFBInst_0))
+              (portRef PLL1DATI5 (instanceRef EFBInst_0))
+              (portRef PLL1DATI4 (instanceRef EFBInst_0))
+              (portRef PLL1DATI3 (instanceRef EFBInst_0))
+              (portRef PLL1DATI2 (instanceRef EFBInst_0))
+              (portRef PLL1DATI1 (instanceRef EFBInst_0))
+              (portRef PLL1DATI0 (instanceRef EFBInst_0))
+              (portRef PLL1ACKI (instanceRef EFBInst_0))
+              (portRef PLL0DATI7 (instanceRef EFBInst_0))
+              (portRef PLL0DATI6 (instanceRef EFBInst_0))
+              (portRef PLL0DATI5 (instanceRef EFBInst_0))
+              (portRef PLL0DATI4 (instanceRef EFBInst_0))
+              (portRef PLL0DATI3 (instanceRef EFBInst_0))
+              (portRef PLL0DATI2 (instanceRef EFBInst_0))
+              (portRef PLL0DATI1 (instanceRef EFBInst_0))
+              (portRef PLL0DATI0 (instanceRef EFBInst_0))
+              (portRef PLL0ACKI (instanceRef EFBInst_0))
+              (portRef TCIC (instanceRef EFBInst_0))
+              (portRef TCRSTN (instanceRef EFBInst_0))
+              (portRef TCCLKI (instanceRef EFBInst_0))
+              (portRef I2C2SDAI (instanceRef EFBInst_0))
+              (portRef I2C2SCLI (instanceRef EFBInst_0))
+              (portRef I2C1SDAI (instanceRef EFBInst_0))
+              (portRef I2C1SCLI (instanceRef EFBInst_0))))
+          (net spi_csn0
+            (joined
+              (portRef (member spi_csn 0))
+              (portRef SPIMCSN0 (instanceRef EFBInst_0))))
+          (net spi_scsn
+            (joined
+              (portRef spi_scsn)
+              (portRef SPISCSN (instanceRef EFBInst_0))))
+          (net spi_mosi
+            (joined
+              (portRef spi_mosi)
+              (portRef B (instanceRef BBspi_mosi))))
+          (net spi_miso
+            (joined
+              (portRef spi_miso)
+              (portRef B (instanceRef BBspi_miso))))
+          (net spi_clk
+            (joined
+              (portRef spi_clk)
+              (portRef B (instanceRef BBspi_clk))))
+          (net wb_ack_o
+            (joined
+              (portRef wb_ack_o)
+              (portRef WBACKO (instanceRef EFBInst_0))))
+          (net wb_dat_o7
+            (joined
+              (portRef (member wb_dat_o 0))
+              (portRef WBDATO7 (instanceRef EFBInst_0))))
+          (net wb_dat_o6
+            (joined
+              (portRef (member wb_dat_o 1))
+              (portRef WBDATO6 (instanceRef EFBInst_0))))
+          (net wb_dat_o5
+            (joined
+              (portRef (member wb_dat_o 2))
+              (portRef WBDATO5 (instanceRef EFBInst_0))))
+          (net wb_dat_o4
+            (joined
+              (portRef (member wb_dat_o 3))
+              (portRef WBDATO4 (instanceRef EFBInst_0))))
+          (net wb_dat_o3
+            (joined
+              (portRef (member wb_dat_o 4))
+              (portRef WBDATO3 (instanceRef EFBInst_0))))
+          (net wb_dat_o2
+            (joined
+              (portRef (member wb_dat_o 5))
+              (portRef WBDATO2 (instanceRef EFBInst_0))))
+          (net wb_dat_o1
+            (joined
+              (portRef (member wb_dat_o 6))
+              (portRef WBDATO1 (instanceRef EFBInst_0))))
+          (net wb_dat_o0
+            (joined
+              (portRef (member wb_dat_o 7))
+              (portRef WBDATO0 (instanceRef EFBInst_0))))
+          (net wb_dat_i7
+            (joined
+              (portRef (member wb_dat_i 0))
+              (portRef WBDATI7 (instanceRef EFBInst_0))))
+          (net wb_dat_i6
+            (joined
+              (portRef (member wb_dat_i 1))
+              (portRef WBDATI6 (instanceRef EFBInst_0))))
+          (net wb_dat_i5
+            (joined
+              (portRef (member wb_dat_i 2))
+              (portRef WBDATI5 (instanceRef EFBInst_0))))
+          (net wb_dat_i4
+            (joined
+              (portRef (member wb_dat_i 3))
+              (portRef WBDATI4 (instanceRef EFBInst_0))))
+          (net wb_dat_i3
+            (joined
+              (portRef (member wb_dat_i 4))
+              (portRef WBDATI3 (instanceRef EFBInst_0))))
+          (net wb_dat_i2
+            (joined
+              (portRef (member wb_dat_i 5))
+              (portRef WBDATI2 (instanceRef EFBInst_0))))
+          (net wb_dat_i1
+            (joined
+              (portRef (member wb_dat_i 6))
+              (portRef WBDATI1 (instanceRef EFBInst_0))))
+          (net wb_dat_i0
+            (joined
+              (portRef (member wb_dat_i 7))
+              (portRef WBDATI0 (instanceRef EFBInst_0))))
+          (net wb_adr_i7
+            (joined
+              (portRef (member wb_adr_i 0))
+              (portRef WBADRI7 (instanceRef EFBInst_0))))
+          (net wb_adr_i6
+            (joined
+              (portRef (member wb_adr_i 1))
+              (portRef WBADRI6 (instanceRef EFBInst_0))))
+          (net wb_adr_i5
+            (joined
+              (portRef (member wb_adr_i 2))
+              (portRef WBADRI5 (instanceRef EFBInst_0))))
+          (net wb_adr_i4
+            (joined
+              (portRef (member wb_adr_i 3))
+              (portRef WBADRI4 (instanceRef EFBInst_0))))
+          (net wb_adr_i3
+            (joined
+              (portRef (member wb_adr_i 4))
+              (portRef WBADRI3 (instanceRef EFBInst_0))))
+          (net wb_adr_i2
+            (joined
+              (portRef (member wb_adr_i 5))
+              (portRef WBADRI2 (instanceRef EFBInst_0))))
+          (net wb_adr_i1
+            (joined
+              (portRef (member wb_adr_i 6))
+              (portRef WBADRI1 (instanceRef EFBInst_0))))
+          (net wb_adr_i0
+            (joined
+              (portRef (member wb_adr_i 7))
+              (portRef WBADRI0 (instanceRef EFBInst_0))))
+          (net wb_we_i
+            (joined
+              (portRef wb_we_i)
+              (portRef WBWEI (instanceRef EFBInst_0))))
+          (net wb_stb_i
+            (joined
+              (portRef wb_stb_i)
+              (portRef WBSTBI (instanceRef EFBInst_0))))
+          (net wb_cyc_i
+            (joined
+              (portRef wb_cyc_i)
+              (portRef WBCYCI (instanceRef EFBInst_0))))
+          (net wb_rst_i
+            (joined
+              (portRef wb_rst_i)
+              (portRef WBRSTI (instanceRef EFBInst_0))))
+          (net wb_clk_i
+            (joined
+              (portRef wb_clk_i)
+              (portRef WBCLKI (instanceRef EFBInst_0))))))))
+  (design spiFlash
+    (cellRef spiFlash
+      (libraryRef ORCLIB)))
+)
diff --git a/lattice/spiFlash.ipx b/lattice/spiFlash.ipx
new file mode 100644
index 0000000..c0c08a8
--- /dev/null
+++ b/lattice/spiFlash.ipx
@@ -0,0 +1,8 @@
+
+
+  
+		
+		
+		
+  
+
diff --git a/lattice/spiFlash.lpc b/lattice/spiFlash.lpc
new file mode 100644
index 0000000..409b3a0
--- /dev/null
+++ b/lattice/spiFlash.lpc
@@ -0,0 +1,90 @@
+[Device]
+Family=machxo2
+PartType=LCMXO2-640HC
+PartName=LCMXO2-640HC-4TG100C
+SpeedGrade=4
+Package=TQFP100
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=EFB
+CoreRevision=1.2
+ModuleName=spiFlash
+SourceFormat=Verilog HDL
+ParameterFileVersion=1.0
+Date=07/27/2017
+Time=11:56:35
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+freq=
+i2c1=0
+i2c1config=0
+i2c1_addr=7-Bit Addressing
+i2c1_ce=0
+i2c1_freq=100
+i2c1_sa=10000
+i2c1_we=0
+i2c2=0
+i2c2_addr=7-Bit Addressing
+i2c2_ce=0
+i2c2_freq=100
+i2c2_sa=10000
+i2c2_we=0
+ufm_addr=7-Bit Addressing
+ufm_sa=10000
+pll=0
+pll_cnt=1
+spi=1
+spi_clkinv=0
+spi_cs=1
+spi_en=0
+spi_freq=16.6
+spi_lsb=0
+spi_mode=Both
+spi_ib=0
+spi_ph=0
+spi_hs=0
+spi_rxo=0
+spi_rxr=0
+spi_txo=0
+spi_txr=0
+spi_we=0
+static_tc=Static
+tc=0
+tc_clkinv=Positive
+tc_ctr=1
+tc_div=1
+tc_ipcap=0
+tc_mode=CTCM
+tc_ocr=32767
+tc_oflow=1
+tc_o=TOGGLE
+tc_opcomp=0
+tc_osc=0
+tc_sa_oflow=0
+tc_top=65535
+ufm=0
+wb_clk_freq=50
+ufm_usage=SHARED_EBR_TAG
+ufm_ebr=
+ufm_remain=
+mem_size=1
+ufm_start=
+ufm_init=0
+memfile=
+ufm_dt=hex
+wb=1
+
+[Command]
+cmd_line= -w -n spiFlash -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -spi -spi_mode Both -spi_freq 16.6 -spi_cs 1 -wb -dev 640
diff --git a/lattice/spiFlash.naf b/lattice/spiFlash.naf
new file mode 100644
index 0000000..45a818c
--- /dev/null
+++ b/lattice/spiFlash.naf
@@ -0,0 +1,35 @@
+wb_clk_i  i
+wb_rst_i  i
+wb_cyc_i  i
+wb_stb_i  i
+wb_we_i  i
+wb_adr_i[7]  i
+wb_adr_i[6]  i
+wb_adr_i[5]  i
+wb_adr_i[4]  i
+wb_adr_i[3]  i
+wb_adr_i[2]  i
+wb_adr_i[1]  i
+wb_adr_i[0]  i
+wb_dat_i[7]  i
+wb_dat_i[6]  i
+wb_dat_i[5]  i
+wb_dat_i[4]  i
+wb_dat_i[3]  i
+wb_dat_i[2]  i
+wb_dat_i[1]  i
+wb_dat_i[0]  i
+wb_dat_o[7]  o
+wb_dat_o[6]  o
+wb_dat_o[5]  o
+wb_dat_o[4]  o
+wb_dat_o[3]  o
+wb_dat_o[2]  o
+wb_dat_o[1]  o
+wb_dat_o[0]  o
+wb_ack_o  o
+spi_clk  b
+spi_miso  b
+spi_mosi  b
+spi_scsn  i
+spi_csn[0]  o
diff --git a/lattice/spiFlash.sort b/lattice/spiFlash.sort
new file mode 100644
index 0000000..f4668de
--- /dev/null
+++ b/lattice/spiFlash.sort
@@ -0,0 +1 @@
+spiFlash.v
diff --git a/lattice/spiFlash.srp b/lattice/spiFlash.srp
new file mode 100644
index 0000000..f1a6d19
--- /dev/null
+++ b/lattice/spiFlash.srp
@@ -0,0 +1,28 @@
+SCUBA, Version Diamond (64-bit) 3.9.0.99.2
+Thu Jul 27 11:56:36 2017
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n spiFlash -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -spi -spi_mode Both -spi_freq 16.6 -spi_cs 1 -wb -dev 640 
+    Circuit name     : spiFlash
+    Module type      : efb
+    Module Version   : 1.2
+    Ports            : 
+	Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0], spi_scsn
+	Outputs      : wb_dat_o[7:0], wb_ack_o, spi_csn[0:0]
+	Inouts       : spi_clk, spi_miso, spi_mosi
+    I/O buffer       : not inserted
+    EDIF output      : spiFlash.edn
+    Verilog output   : spiFlash.v
+    Verilog template : spiFlash_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : spiFlash.srp
+    Element Usage    :
+             BB : 3
+            EFB : 1
+    Estimated Resource Usage:
diff --git a/lattice/spiFlash.sym b/lattice/spiFlash.sym
new file mode 100644
index 0000000..d32a261
Binary files /dev/null and b/lattice/spiFlash.sym differ
diff --git a/lattice/spiFlash.v b/lattice/spiFlash.v
new file mode 100644
index 0000000..e215dc8
--- /dev/null
+++ b/lattice/spiFlash.v
@@ -0,0 +1,134 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.9.0.99.2 */
+/* Module Version: 1.2 */
+/* C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n spiFlash -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -spi -spi_mode Both -spi_freq 16.6 -spi_cs 1 -wb -dev 640  */
+/* Thu Jul 27 11:56:36 2017 */
+
+
+`timescale 1 ns / 1 ps
+module spiFlash (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, 
+    wb_adr_i, wb_dat_i, wb_dat_o, wb_ack_o, spi_clk, spi_miso, spi_mosi, 
+    spi_scsn, spi_csn)/* synthesis NGD_DRC_MASK=1 */;
+    input wire wb_clk_i;
+    input wire wb_rst_i;
+    input wire wb_cyc_i;
+    input wire wb_stb_i;
+    input wire wb_we_i;
+    input wire [7:0] wb_adr_i;
+    input wire [7:0] wb_dat_i;
+    input wire spi_scsn;
+    output wire [7:0] wb_dat_o;
+    output wire wb_ack_o;
+    output wire [0:0] spi_csn;
+    inout wire spi_clk;
+    inout wire spi_miso;
+    inout wire spi_mosi;
+
+    wire scuba_vhi;
+    wire spi_mosi_oe;
+    wire spi_mosi_o;
+    wire spi_miso_oe;
+    wire spi_miso_o;
+    wire spi_clk_oe;
+    wire spi_clk_o;
+    wire spi_mosi_i;
+    wire spi_miso_i;
+    wire spi_clk_i;
+    wire scuba_vlo;
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    BB BBspi_mosi (.I(spi_mosi_o), .T(spi_mosi_oe), .O(spi_mosi_i), .B(spi_mosi));
+
+    BB BBspi_miso (.I(spi_miso_o), .T(spi_miso_oe), .O(spi_miso_i), .B(spi_miso));
+
+    BB BBspi_clk (.I(spi_clk_o), .T(spi_clk_oe), .O(spi_clk_i), .B(spi_clk));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
+    defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ;
+    defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ;
+    defparam EFBInst_0.UFM_INIT_START_PAGE = 0 ;
+    defparam EFBInst_0.UFM_INIT_PAGES = 0 ;
+    defparam EFBInst_0.DEV_DENSITY = "640L" ;
+    defparam EFBInst_0.EFB_UFM = "DISABLED" ;
+    defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
+    defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
+    defparam EFBInst_0.TC_ICR_INT = "OFF" ;
+    defparam EFBInst_0.TC_OCR_INT = "OFF" ;
+    defparam EFBInst_0.TC_OV_INT = "OFF" ;
+    defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
+    defparam EFBInst_0.TC_RESETN = "ENABLED" ;
+    defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
+    defparam EFBInst_0.TC_OCR_SET = 32767 ;
+    defparam EFBInst_0.TC_TOP_SET = 65535 ;
+    defparam EFBInst_0.GSR = "ENABLED" ;
+    defparam EFBInst_0.TC_CCLK_SEL = 1 ;
+    defparam EFBInst_0.TC_MODE = "CTCM" ;
+    defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
+    defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
+    defparam EFBInst_0.EFB_TC = "DISABLED" ;
+    defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
+    defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
+    defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
+    defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
+    defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
+    defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
+    defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
+    defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
+    defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
+    defparam EFBInst_0.SPI_CLK_DIVIDER = 3 ;
+    defparam EFBInst_0.SPI_MODE = "BOTH" ;
+    defparam EFBInst_0.EFB_SPI = "ENABLED" ;
+    defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
+    defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
+    defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
+    defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
+    defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
+    defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
+    defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
+    defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
+    defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
+    defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
+    defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
+    defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
+    defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
+    defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
+    defparam EFBInst_0.EFB_WB_CLK_FREQ = "50.0" ;
+    EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i), 
+        .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]), 
+        .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]), 
+        .WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]), 
+        .WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]), 
+        .WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]), 
+        .WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo), 
+        .PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo), 
+        .PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo), 
+        .PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo), 
+        .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo), 
+        .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo), 
+        .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo), 
+        .I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo), 
+        .SPISCKI(spi_clk_i), .SPIMISOI(spi_miso_i), .SPIMOSII(spi_mosi_i), 
+        .SPISCSN(spi_scsn), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo), 
+        .UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]), 
+        .WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]), 
+        .WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]), 
+        .WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), 
+        .PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(), 
+        .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), 
+        .PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(), 
+        .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(), 
+        .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(spi_clk_o), .SPISCKEN(spi_clk_oe), 
+        .SPIMISOO(spi_miso_o), .SPIMISOEN(spi_miso_oe), .SPIMOSIO(spi_mosi_o), 
+        .SPIMOSIEN(spi_mosi_oe), .SPIMCSN7(), .SPIMCSN6(), .SPIMCSN5(), 
+        .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(), .SPIMCSN1(), .SPIMCSN0(spi_csn[0]), 
+        .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(), .WBCUFMIRQ(), .CFGWAKE(), 
+        .CFGSTDBY());
+
+
+
+    // exemplar begin
+    // exemplar end
+
+endmodule
diff --git a/lattice/spiFlash_tmpl.v b/lattice/spiFlash_tmpl.v
new file mode 100644
index 0000000..c916005
--- /dev/null
+++ b/lattice/spiFlash_tmpl.v
@@ -0,0 +1,8 @@
+/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.0.99.2 */
+/* Module Version: 1.2 */
+/* Thu Jul 27 11:56:36 2017 */
+
+/* parameterized module instance */
+spiFlash __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), 
+    .wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ), 
+    .spi_clk( ), .spi_miso( ), .spi_mosi( ), .spi_scsn( ), .spi_csn( ));
diff --git a/lattice/sso_rpt.htm b/lattice/sso_rpt.htm
new file mode 100644
index 0000000..54acba2
--- /dev/null
+++ b/lattice/sso_rpt.htm
@@ -0,0 +1,184 @@
+
+
+SSO Report
+
+
+
+
+
+
+
+
+
+
+
+
    I/O SSO Analysis Report
    
+
    +ssoana:  version Diamond (64-bit) 3.9.0.99.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Jul 27 12:31:02 2017
+
    
+
    Report Information
    
+
    +Target Vendor         : Lattice
+Target Device         : LCMXO2-640HC
+Target Package        : TQFP100
+Target Performance    : 4
+SSO Data Revision     : Final	Version 2.2
+
    
+
    About SSO Analysis Results: SSO analysis results are based on a specific lab environment and should be used for estimating SSO switching noise.  The user environment may yield a different result from this analysis tool.
+
    Note: N/S means SSO tool does not support the IO preference setting.
+
+
+
    Bank SSO Results
    
+
     SSO Information of each Bank(Bounce)
    
+
    The table lists SSO information of each bank(Bounce SSO).
+ If any pin in the bank are not assigned, Bank SSO calculation will consider the worst pin assignments which lead to the largest device SSO noise. It may be larger than that of real pin assignments.
+
    
+
+
+
+
+
+
    BankSIDDevice SSO(mV)Board SSO(mV)Total SSO(mV)Criteria(mV)AllowancePercentageStatus
    0 0.000.000.000.00100.00%0.00%PASS
    1 0.000.000.000.00100.00%0.00%PASS
    2 0.000.000.000.00100.00%0.00%PASS
    3 0.000.000.000.00100.00%0.00%PASS
    
+
     Device SSO Information of each SwitchingID(Bounce)
    
+
    The table lists Device SSO information of each switching ID. Pins in the same standard have same attribuites, such as IO type, drive, load, etc.  Pins in the same group have same switching ID.
+
    
+
+
+
    SwitchingIDBankDevice SSO of Group(mV)#PinsIO TypeDrive(mA)SlewLoad(pF)Device SSO of Standard(mV)
    
+
     SSO Information of each Bank(Drop)
    
+
    The table lists SSO information of each bank(Drop SSO).
+If any pin in the bank are not assigned, Bank SSO calculation will consider the worst pin assignments which lead to the largest device SSO noise. It may be larger than that of real pin assignments.
+
    
+
+
+
+
+
+
    BankSIDDevice SSO(mV)Board SSO(mV)Total SSO(mV)Criteria(mV)AllowancePercentageStatus
    0 0.000.000.000.00100.00%0.00%PASS
    1 0.000.000.000.00100.00%0.00%PASS
    2 0.000.000.000.00100.00%0.00%PASS
    3 0.000.000.000.00100.00%0.00%PASS
    
+
     Device SSO Information of each SwitchingID(Drop)
    
+
    The table lists Device SSO information of each switching ID. Pins in the same standard have same attribuites, such as IO type, drive, load, etc.  Pins in the same group have same switching ID.
+
    
+
+
+
    SwitchingIDBankDevice SSO of Group(mV)#PinsIO TypeDrive(mA)SlewLoad(pF)Device SSO of Standard(mV)
    
+
    Pin SSO Results
    Worst Bounce SSO of each Bank
    
+
    The table lists the worst bounce SSO information of each bank. The information comes from the pin which has the worst bounce SSO status in the bank. Please click bank index to view information of all pins in the bank. Note that pin SSO calculation requires all pins in the bank are assigned. If not, please refer to bank SSO results.
+
    
+
+
+
+
+
+
+
    BankDevice SSO(mV)Board SSO(mV)Total SSO(mV)Criteria(mV)AllowancePercentageStatus
    00.000.000.000.00100.00%0.00%PASS
    10.000.000.000.00100.00%0.00%PASS
    20.000.000.000.00100.00%0.00%PASS
    30.000.000.000.00100.00%0.00%PASS
    
+
    Worst Drop SSO of each Bank
    
+
    The table lists the worst drop SSO information of each bank. The information comes from the pin which has the worst drop SSO status in the bank. Please click bank index to view information of all pins in the bank. Note that pin SSO calculation requires all pins in the bank are assigned. If not, please refer to bank SSO results.
+
    
+
+
+
+
+
+
+
    BankDevice SSO(mV)Board SSO(mV)Total SSO(mV)Criteria(mV)AllowancePercentageStatus
    00.000.000.000.00100.00%0.00%PASS
    10.000.000.000.00100.00%0.00%PASS
    20.000.000.000.00100.00%0.00%PASS
    30.000.000.000.00100.00%0.00%PASS
    
+
    Bounce SSO Information of Pins of each Bank
    
+
    Following tables list bounce SSO information of pins bank by bank. Please click pin names to view where the noise originates.
+
    Drop SSO Information of Pins of each Bank
    
+
    Following tables list drop SSO information of pins bank by bank. Please click pin names to view where the noise originates.
+
    Detailed SSO Report of Pins
    
+
    Following tables list where each pin's noise originates
+
    
+
+
diff --git a/lattice/tb_codeROM_tmpl.v b/lattice/tb_codeROM_tmpl.v
new file mode 100644
index 0000000..d8d3145
--- /dev/null
+++ b/lattice/tb_codeROM_tmpl.v
@@ -0,0 +1,45 @@
+//Verilog testbench template generated by SCUBA Diamond (64-bit) 3.9.0.99.2
+`timescale 1 ns / 1 ps
+module tb;
+    reg [11:0] Address = 12'b0;
+    reg OutClock = 0;
+    reg OutClockEn = 0;
+    reg Reset = 0;
+    wire [7:0] Q;
+
+    integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0;
+
+    GSR GSR_INST (.GSR(1'b1));
+    PUR PUR_INST (.PUR(1'b1));
+
+    codeROM u1 (.Address(Address), .OutClock(OutClock), .OutClockEn(OutClockEn), 
+        .Reset(Reset), .Q(Q)
+    );
+
+    initial
+    begin
+       Address <= 0;
+      #100;
+      @(Reset == 1'b0);
+      for (i1 = 0; i1 < 4099; i1 = i1 + 1) begin
+        @(posedge OutClock);
+        #1  Address <= Address + 1'b1;
+      end
+    end
+    always
+    #5.00 OutClock <= ~ OutClock;
+
+    initial
+    begin
+       OutClockEn <= 1'b0;
+      #100;
+      @(Reset == 1'b0);
+       OutClockEn <= 1'b1;
+    end
+    initial
+    begin
+       Reset <= 1'b1;
+      #100;
+       Reset <= 1'b0;
+    end
+endmodule
\ No newline at end of file
diff --git a/lattice/top.v b/lattice/top.v
new file mode 100644
index 0000000..a1258e9
--- /dev/null
+++ b/lattice/top.v
@@ -0,0 +1,112 @@
+`timescale 1 ns / 1 ps
+module top(
+	// bus interface
+	input [11:0] addr,	
+	input fclk, // Clock for serial communication, either 7 or 8 MHz (7 MHz on Apple II)					
+	input q3, // 2 MHz non-symmetric timing signal										
+	inout [7:0] data,	
+	input rw, // 1 means read, 0 means write
+	input _iostrobe, // goes low during read or write to any address $C800-$CFFF
+	input _iosel, // goes low during read or write to $CX00-$CXFF, where X is slot number
+	input _devsel, // goes low during read or write to $C0(X+8)0-$C0(X+8)F, where X is slot number. IWM: Falling edge latches A3-A0. Rising edge of (Q3 or _devsel) qualifies write register data
+	input _reset,
+	// disk interface
+	output wrdata,			
+	output [3:0] phase,	
+	output _wrreq,				
+	output _enbl1,			   																
+	inout _enbl2, // output that may be hardwired to ground when connected to a drive 
+	inout select, // output that may be hardwired to ground when connected to a drive 
+	inout _en35,  // output that may be hardwired to ground when connected to a drive 
+	input sense,					
+	input rddata,  				
+	// SPI
+	output spi_clk,
+	output spi_mosi,
+	input spi_miso,
+	output spi_cs,
+	// level-shifting buffers
+	output _en245, // bidirectional connection of data bus to FPGA
+	// debugging: LEDs or switches or misc stuff
+	output [7:0] debugInfo
+    );
+
+	wire isOutputting;
+	wire romExpansionActive; // 1 if the Yellowstone card's ROM is the currently selected slot ROM	
+	assign debugInfo = { romExpansionActive, rw, q3, isOutputting/*_devsel*/, _iosel, _iostrobe, _reset, spi_miso }; //{ romActive, 6'b000000, spi_miso };
+
+	
+	
	wire _romoe;
+	
+	//reg [1:0] en245Delay;
+	//always @(posedge fclk) begin
+	//	en245Delay <= { en245Delay[0], (~_devsel || ~_romoe) };
+	//end
+	
+	assign _en245 = ~(/*~q3 &&*//*(en245Delay == 2'b11) &&*/ (~_devsel || ~_romoe)); // IWM selected or ROM outputting
+
+
+	// IMPORTANT! TO-DO
+	// for select, _enbl2, _en35, these outputs may be driven externally to ground!
+	// never drive these actively high. configure as inout, enable the internal pull-up, and set output value to 0 or hi-Z
+	// may need to pause a few microseconds after setting these to hi-Z to let the pull-up work. It's around 50Kohm equivalent.
+	// RC time constant assuming 10 pF trace capacitance is 0.5 microseconds
+	
+	wire _enbl2_from_iwm;
+	assign _enbl2 = 1'bZ;
+	assign select = 1'bZ;
+	assign _en35 = 1'bZ;
+	
+	addrDecoder myAddrDecoder(
+		.addr(addr),
+		.fclk(fclk),
+		._iostrobe(_iostrobe),
+		._iosel(_iosel),
+		._reset(_reset),
+		._romoe(_romoe),
+		.romExpansionActive(romExpansionActive)
+	);
+	
+	wire [7:0] iwmDataOut;
+	
+	iwm myIwm(
+		.addr(addr[3:0]),		
+		._devsel(_devsel),
+		.fclk(fclk),
+		.q3(q3),
+		._reset(_reset),
+		.dataIn(data),
+		.dataOut(iwmDataOut),
+		.wrdata(wrdata),
+		.phase(phase),
+		._wrreq(_wrreq),
+		._enbl1(_enbl1),
+		._enbl2(_enbl2_from_iwm),
+		.sense(sense),
+		.rddata(rddata)  	
+	);
+	 
+	wire [7:0] romOutput;
+	
+	codeROM myROM(
+		.Address(addr[11:0]),
+		.OutClock(fclk), // use internal clock? 
+		.OutClockEn(1'b1),
+		.Reset(1'b0), 
+		.Q(romOutput)
+	);
+	
+	//reg [1:0] lastDataEnable;
+	
+	//always @(posedge fclk) begin
+	//	lastDataEnable <= { lastDataEnable[0], (rw == 1 && _romoe == 0) || (rw == 1 && _devsel == 0 && addr[0] == 0) };
+	//end
+	
+	// provide data from the card's ROM, or the IWM?
+	// IWM registers are read during any operation in which A0 is 0
+	assign isOutputting = (rw && ~_romoe) /*|| (rw == 1 && _devsel == 0 && addr[0] == 0)*/;
+	assign data = (/*lastDataEnable == 2'b11 &&*/ rw == 1 && _romoe == 0) ? romOutput :
+				  (/*lastDataEnable == 2'b11 &&*/ rw == 1 && _devsel == 0 && addr[0] == 0) ? iwmDataOut : 
+				  8'bZZZZZZZZ;
+	
+endmodule
diff --git a/liron.asm b/liron.asm
new file mode 100644
index 0000000..b4b794a
--- /dev/null
+++ b/liron.asm
@@ -0,0 +1,1300 @@
+                  * = C700
+C700   A2 20      LDX #$20
+C702   A2 00      LDX #$00
+C704   A2 03      LDX #$03
+C706   C9 00      CMP #$00
+C708   B0 0A      BCS $C714
+C70A   38         SEC
+C70B   B0 01      BCS $C70E
+C70D   18         CLC
+C70E   A2 07      LDX #$07
+C710   7E 78 04   ROR $0478,X
+C713   18         CLC
+C714   A2 C7      LDX #$C7
+C716   8E F8 07   STX $07F8
+C719   A2 07      LDX #$07
+C71B   AD FF CF   LDA $CFFF
+C71E   4C E1 CB   JMP $CBE1
+C721   A0 00      LDY #$00
+C723   A5 4B      LDA $4B
+C725   48         PHA
+C726   D0 03      BNE $C72B
+C728   4C B8 C7   JMP $C7B8
+C72B   AD FC C0   LDA $C0FC
+C72E   10 FB      BPL $C72B
+C730   85 59      STA $59
+C732   4A         LSR A
+C733   4A         LSR A
+C734   4A         LSR A
+C735   29 0F      AND #$0F
+C737   AA         TAX
+C738   A5 59      LDA $59
+C73A   29 07      AND #$07
+C73C   85 59      STA $59
+C73E   AD FC C0   LDA $C0FC
+C741   10 FB      BPL $C73E
+C743   5D 27 CA   EOR $CA27,X
+C746   91 56      STA ($56),Y
+C748   45 40      EOR $40
+C74A   85 40      STA $40
+C74C   C8         INY
+C74D   D0 02      BNE $C751
+C74F   E6 57      INC $57
+C751   AD FC C0   LDA $C0FC
+C754   10 FB      BPL $C751
+C756   5D 37 CA   EOR $CA37,X
+C759   91 56      STA ($56),Y
+C75B   45 40      EOR $40
+C75D   85 40      STA $40
+C75F   C8         INY
+C760   AD FC C0   LDA $C0FC
+C763   10 FB      BPL $C760
+C765   5D 47 CA   EOR $CA47,X
+C768   91 56      STA ($56),Y
+C76A   45 40      EOR $40
+C76C   85 40      STA $40
+C76E   C8         INY
+C76F   AD FC C0   LDA $C0FC
+C772   10 FB      BPL $C76F
+C774   5D 57 CA   EOR $CA57,X
+C777   91 56      STA ($56),Y
+C779   45 40      EOR $40
+C77B   85 40      STA $40
+C77D   C8         INY
+C77E   D0 02      BNE $C782
+C780   E6 57      INC $57
+C782   A6 59      LDX $59
+C784   AD FC C0   LDA $C0FC
+C787   10 FB      BPL $C784
+C789   5D 37 CA   EOR $CA37,X
+C78C   91 56      STA ($56),Y
+C78E   45 40      EOR $40
+C790   85 40      STA $40
+C792   C8         INY
+C793   AD FC C0   LDA $C0FC
+C796   10 FB      BPL $C793
+C798   5D 47 CA   EOR $CA47,X
+C79B   91 56      STA ($56),Y
+C79D   45 40      EOR $40
+C79F   85 40      STA $40
+C7A1   C8         INY
+C7A2   AD FC C0   LDA $C0FC
+C7A5   10 FB      BPL $C7A2
+C7A7   5D 57 CA   EOR $CA57,X
+C7AA   91 56      STA ($56),Y
+C7AC   45 40      EOR $40
+C7AE   85 40      STA $40
+C7B0   C8         INY
+C7B1   C6 4B      DEC $4B
+C7B3   F0 03      BEQ $C7B8
+C7B5   4C 2B C7   JMP $C72B
+C7B8   AD FC C0   LDA $C0FC
+C7BB   10 FB      BPL $C7B8
+C7BD   85 59      STA $59
+C7BF   68         PLA
+C7C0   85 4B      STA $4B
+C7C2   AD FC C0   LDA $C0FC
+C7C5   10 FB      BPL $C7C2
+C7C7   38         SEC
+C7C8   2A         ROL A
+C7C9   25 59      AND $59
+C7CB   45 40      EOR $40
+C7CD   AC FC C0   LDY $C0FC
+C7D0   10 FB      BPL $C7CD
+C7D2   C0 C8      CPY #$C8
+C7D4   D0 1C      BNE $C7F2
+C7D6   A6 4C      LDX $4C
+C7D8   F0 08      BEQ $C7E2
+C7DA   A0 00      LDY #$00
+C7DC   51 54      EOR ($54),Y
+C7DE   C8         INY
+C7DF   CA         DEX
+C7E0   D0 FA      BNE $C7DC
+C7E2   AA         TAX
+C7E3   D0 11      BNE $C7F6
+C7E5   AD FD C0   LDA $C0FD
+C7E8   AD FE C0   LDA $C0FE
+C7EB   30 FB      BMI $C7E8
+C7ED   AD F0 C0   LDA $C0F0
+C7F0   18         CLC
+C7F1   60         RTS
+C7F2   A9 20      LDA #$20
+C7F4   D0 02      BNE $C7F8
+C7F6   A9 10      LDA #$10
+C7F8   38         SEC
+C7F9   60         RTS
+C7FA   FF         ???
+C7FB   00         BRK
+C7FC   00         BRK
+C7FD   00         BRK
+C7FE   BF         ???
+C7FF   0A         ASL A
+C800   20 EE CA   JSR $CAEE
+C803   20 05 CA   JSR $CA05
+C806   A0 07      LDY #$07
+C808   20 A9 CB   JSR $CBA9
+C80B   BD 8B C0   LDA $C08B,X
+C80E   BD 89 C0   LDA $C089,X
+C811   A0 32      LDY #$32
+C813   BD 8E C0   LDA $C08E,X
+C816   30 07      BMI $C81F
+C818   88         DEY
+C819   D0 F8      BNE $C813
+C81B   38         SEC
+C81C   4C 49 C9   JMP $C949
+C81F   BD 81 C0   LDA $C081,X
+C822   A0 05      LDY #$05
+C824   A9 FF      LDA #$FF
+C826   9D 8F C0   STA $C08F,X
+C829   B9 50 C9   LDA $C950,Y
+C82C   1E 8C C0   ASL $C08C,X
+C82F   90 FB      BCC $C82C
+C831   9D 8D C0   STA $C08D,X
+C834   88         DEY
+C835   10 F2      BPL $C829
+C837   A5 5A      LDA $5A
+C839   09 80      ORA #$80
+C83B   20 D8 C9   JSR $C9D8
+C83E   20 D6 C9   JSR $C9D6
+C841   A5 5B      LDA $5B
+C843   20 D8 C9   JSR $C9D8
+C846   20 D6 C9   JSR $C9D6
+C849   20 D6 C9   JSR $C9D6
+C84C   A5 4C      LDA $4C
+C84E   09 80      ORA #$80
+C850   20 D8 C9   JSR $C9D8
+C853   A5 4B      LDA $4B
+C855   09 80      ORA #$80
+C857   20 D8 C9   JSR $C9D8
+C85A   A5 4C      LDA $4C
+C85C   F0 15      BEQ $C873
+C85E   A0 FF      LDY #$FF
+C860   A5 59      LDA $59
+C862   1E 8C C0   ASL $C08C,X
+C865   90 FB      BCC $C862
+C867   9D 8D C0   STA $C08D,X
+C86A   C8         INY
+C86B   B1 54      LDA ($54),Y
+C86D   09 80      ORA #$80
+C86F   C4 4C      CPY $4C
+C871   90 EF      BCC $C862
+C873   A5 4B      LDA $4B
+C875   D0 03      BNE $C87A
+C877   4C 13 C9   JMP $C913
+C87A   EA         NOP
+C87B   A0 00      LDY #$00
+C87D   A5 41      LDA $41
+C87F   9D 8D C0   STA $C08D,X
+C882   A5 4D      LDA $4D
+C884   09 80      ORA #$80
+C886   84 59      STY $59
+C888   BC 8C C0   LDY $C08C,X
+C88B   10 FB      BPL $C888
+C88D   9D 8D C0   STA $C08D,X
+C890   A4 59      LDY $59
+C892   B1 56      LDA ($56),Y
+C894   85 4D      STA $4D
+C896   0A         ASL A
+C897   26 41      ROL $41
+C899   C8         INY
+C89A   D0 05      BNE $C8A1
+C89C   E6 57      INC $57
+C89E   4C A3 C8   JMP $C8A3
+C8A1   48         PHA
+C8A2   68         PLA
+C8A3   A9 02      LDA #$02
+C8A5   05 41      ORA $41
+C8A7   85 41      STA $41
+C8A9   A5 4E      LDA $4E
+C8AB   09 80      ORA #$80
+C8AD   9D 8D C0   STA $C08D,X
+C8B0   B1 56      LDA ($56),Y
+C8B2   85 4E      STA $4E
+C8B4   0A         ASL A
+C8B5   26 41      ROL $41
+C8B7   C8         INY
+C8B8   A5 4F      LDA $4F
+C8BA   09 80      ORA #$80
+C8BC   9D 8D C0   STA $C08D,X
+C8BF   B1 56      LDA ($56),Y
+C8C1   85 4F      STA $4F
+C8C3   0A         ASL A
+C8C4   26 41      ROL $41
+C8C6   C8         INY
+C8C7   A5 50      LDA $50
+C8C9   09 80      ORA #$80
+C8CB   9D 8D C0   STA $C08D,X
+C8CE   B1 56      LDA ($56),Y
+C8D0   85 50      STA $50
+C8D2   0A         ASL A
+C8D3   26 41      ROL $41
+C8D5   C8         INY
+C8D6   D0 05      BNE $C8DD
+C8D8   E6 57      INC $57
+C8DA   4C DF C8   JMP $C8DF
+C8DD   48         PHA
+C8DE   68         PLA
+C8DF   A5 51      LDA $51
+C8E1   09 80      ORA #$80
+C8E3   9D 8D C0   STA $C08D,X
+C8E6   B1 56      LDA ($56),Y
+C8E8   85 51      STA $51
+C8EA   0A         ASL A
+C8EB   26 41      ROL $41
+C8ED   C8         INY
+C8EE   A5 52      LDA $52
+C8F0   09 80      ORA #$80
+C8F2   9D 8D C0   STA $C08D,X
+C8F5   B1 56      LDA ($56),Y
+C8F7   85 52      STA $52
+C8F9   0A         ASL A
+C8FA   26 41      ROL $41
+C8FC   C8         INY
+C8FD   A5 53      LDA $53
+C8FF   09 80      ORA #$80
+C901   9D 8D C0   STA $C08D,X
+C904   B1 56      LDA ($56),Y
+C906   85 53      STA $53
+C908   0A         ASL A
+C909   26 41      ROL $41
+C90B   C8         INY
+C90C   C6 4B      DEC $4B
+C90E   F0 03      BEQ $C913
+C910   4C 7D C8   JMP $C87D
+C913   A5 40      LDA $40
+C915   09 AA      ORA #$AA
+C917   BC 8C C0   LDY $C08C,X
+C91A   10 FB      BPL $C917
+C91C   9D 8D C0   STA $C08D,X
+C91F   A5 40      LDA $40
+C921   4A         LSR A
+C922   09 AA      ORA #$AA
+C924   20 D8 C9   JSR $C9D8
+C927   A9 C8      LDA #$C8
+C929   20 D8 C9   JSR $C9D8
+C92C   BD 8C C0   LDA $C08C,X
+C92F   29 40      AND #$40
+C931   D0 F9      BNE $C92C
+C933   9D 8D C0   STA $C08D,X
+C936   A0 0A      LDY #$0A
+C938   88         DEY
+C939   D0 08      BNE $C943
+C93B   A9 01      LDA #$01
+C93D   20 1F CA   JSR $CA1F
+C940   38         SEC
+C941   B0 06      BCS $C949
+C943   BD 8E C0   LDA $C08E,X
+C946   30 F0      BMI $C938
+C948   18         CLC
+C949   BD 80 C0   LDA $C080,X
+C94C   BD 8C C0   LDA $C08C,X
+C94F   60         RTS
+C950   C3         ???
+C951   FF         ???
+C952   FC         ???
+C953   F3         ???
+C954   CF         ???
+C955   3F         ???
+C956   20 5B C9   JSR $C95B
+C959   EA         NOP
+C95A   EA         NOP
+C95B   EA         NOP
+C95C   60         RTS
+C95D   4C 3D C9   JMP $C93D
+C960   A9 00      LDA #$00
+C962   85 40      STA $40
+C964   A5 54      LDA $54
+C966   85 56      STA $56
+C968   A5 55      LDA $55
+C96A   85 57      STA $57
+C96C   A9 21      LDA #$21
+C96E   85 52      STA $52
+C970   A5 58      LDA $58
+C972   18         CLC
+C973   69 C0      ADC #$C0
+C975   85 53      STA $53
+C977   20 05 CA   JSR $CA05
+C97A   BD 8D C0   LDA $C08D,X
+C97D   BD 8E C0   LDA $C08E,X
+C980   10 FB      BPL $C97D
+C982   BD 81 C0   LDA $C081,X
+C985   A0 1E      LDY #$1E
+C987   BD 8C C0   LDA $C08C,X
+C98A   10 FB      BPL $C987
+C98C   88         DEY
+C98D   30 CE      BMI $C95D
+C98F   C9 C3      CMP #$C3
+C991   D0 F4      BNE $C987
+C993   A0 06      LDY #$06
+C995   BD 8C C0   LDA $C08C,X
+C998   10 FB      BPL $C995
+C99A   29 7F      AND #$7F
+C99C   99 4B 00   STA $004B,Y
+C99F   49 80      EOR #$80
+C9A1   45 40      EOR $40
+C9A3   85 40      STA $40
+C9A5   88         DEY
+C9A6   10 ED      BPL $C995
+C9A8   A5 4C      LDA $4C
+C9AA   F0 27      BEQ $C9D3
+C9AC   18         CLC
+C9AD   65 54      ADC $54
+C9AF   85 56      STA $56
+C9B1   A5 55      LDA $55
+C9B3   69 00      ADC #$00
+C9B5   85 57      STA $57
+C9B7   A0 00      LDY #$00
+C9B9   BD 8C C0   LDA $C08C,X
+C9BC   10 FB      BPL $C9B9
+C9BE   0A         ASL A
+C9BF   85 41      STA $41
+C9C1   BD 8C C0   LDA $C08C,X
+C9C4   10 FB      BPL $C9C1
+C9C6   06 41      ASL $41
+C9C8   B0 02      BCS $C9CC
+C9CA   49 80      EOR #$80
+C9CC   91 54      STA ($54),Y
+C9CE   C8         INY
+C9CF   C4 4C      CPY $4C
+C9D1   90 EE      BCC $C9C1
+C9D3   6C 52 00   JMP ($0052)
+C9D6   A9 80      LDA #$80
+C9D8   BC 8C C0   LDY $C08C,X
+C9DB   10 FB      BPL $C9D8
+C9DD   9D 8D C0   STA $C08D,X
+C9E0   45 40      EOR $40
+C9E2   85 40      STA $40
+C9E4   60         RTS
+C9E5   20 0F CA   JSR $CA0F
+C9E8   BD 81 C0   LDA $C081,X
+C9EB   BD 85 C0   LDA $C085,X
+C9EE   A0 50      LDY #$50
+C9F0   20 F8 C9   JSR $C9F8
+C9F3   20 0F CA   JSR $CA0F
+C9F6   A0 0A      LDY #$0A
+C9F8   20 FF C9   JSR $C9FF
+C9FB   88         DEY
+C9FC   D0 FA      BNE $C9F8
+C9FE   60         RTS
+C9FF   A2 C8      LDX #$C8
+CA01   CA         DEX
+CA02   D0 FD      BNE $CA01
+CA04   60         RTS
+CA05   20 1F CA   JSR $CA1F
+CA08   BD 83 C0   LDA $C083,X
+CA0B   BD 87 C0   LDA $C087,X
+CA0E   60         RTS
+CA0F   20 1F CA   JSR $CA1F
+CA12   BD 80 C0   LDA $C080,X
+CA15   BD 82 C0   LDA $C082,X
+CA18   BD 84 C0   LDA $C084,X
+CA1B   BD 86 C0   LDA $C086,X
+CA1E   60         RTS
+CA1F   A5 58      LDA $58
+CA21   0A         ASL A
+CA22   0A         ASL A
+CA23   0A         ASL A
+CA24   0A         ASL A
+CA25   AA         TAX
+CA26   60         RTS
+CA27   80         ???
+CA28   80         ???
+CA29   80         ???
+CA2A   80         ???
+CA2B   80         ???
+CA2C   80         ???
+CA2D   80         ???
+CA2E   80         ???
+CA2F   00         BRK
+CA30   00         BRK
+CA31   00         BRK
+CA32   00         BRK
+CA33   00         BRK
+CA34   00         BRK
+CA35   00         BRK
+CA36   00         BRK
+CA37   80         ???
+CA38   80         ???
+CA39   80         ???
+CA3A   80         ???
+CA3B   00         BRK
+CA3C   00         BRK
+CA3D   00         BRK
+CA3E   00         BRK
+CA3F   80         ???
+CA40   80         ???
+CA41   80         ???
+CA42   80         ???
+CA43   00         BRK
+CA44   00         BRK
+CA45   00         BRK
+CA46   00         BRK
+CA47   80         ???
+CA48   80         ???
+CA49   00         BRK
+CA4A   00         BRK
+CA4B   80         ???
+CA4C   80         ???
+CA4D   00         BRK
+CA4E   00         BRK
+CA4F   80         ???
+CA50   80         ???
+CA51   00         BRK
+CA52   00         BRK
+CA53   80         ???
+CA54   80         ???
+CA55   00         BRK
+CA56   00         BRK
+CA57   80         ???
+CA58   00         BRK
+CA59   80         ???
+CA5A   00         BRK
+CA5B   80         ???
+CA5C   00         BRK
+CA5D   80         ???
+CA5E   00         BRK
+CA5F   80         ???
+CA60   00         BRK
+CA61   80         ???
+CA62   00         BRK
+CA63   80         ???
+CA64   00         BRK
+CA65   80         ???
+CA66   00         BRK
+CA67   A9 05      LDA #$05
+CA69   A0 00      LDY #$00
+CA6B   20 8A CA   JSR $CA8A
+CA6E   90 05      BCC $CA75
+CA70   A9 80      LDA #$80
+CA72   20 ED CD   JSR $CDED
+CA75   60         RTS
+CA76   20 8A CA   JSR $CA8A
+CA79   90 FA      BCC $CA75
+CA7B   A9 80      LDA #$80
+CA7D   20 ED CD   JSR $CDED
+CA80   AD F8 06   LDA $06F8
+CA83   85 4D      STA $4D
+CA85   AD 78 07   LDA $0778
+CA88   85 4E      STA $4E
+CA8A   A9 B8      LDA #$B8
+CA8C   A0 0B      LDY #$0B
+CA8E   A6 58      LDX $58
+CA90   9D F8 04   STA $04F8,X
+CA93   98         TYA
+CA94   9D 78 05   STA $0578,X
+CA97   A5 4D      LDA $4D
+CA99   8D F8 06   STA $06F8
+CA9C   A5 4E      LDA $4E
+CA9E   8D 78 07   STA $0778
+CAA1   20 00 C8   JSR $C800
+CAA4   AD F8 06   LDA $06F8
+CAA7   85 4D      STA $4D
+CAA9   AD 78 07   LDA $0778
+CAAC   85 4E      STA $4E
+CAAE   90 0C      BCC $CABC
+CAB0   A6 58      LDX $58
+CAB2   DE F8 04   DEC $04F8,X
+CAB5   D0 E0      BNE $CA97
+CAB7   DE 78 05   DEC $0578,X
+CABA   10 DB      BPL $CA97
+CABC   60         RTS
+CABD   A4 58      LDY $58
+CABF   A9 05      LDA #$05
+CAC1   99 F8 04   STA $04F8,Y
+CAC4   20 60 C9   JSR $C960
+CAC7   90 0F      BCC $CAD8
+CAC9   A0 01      LDY #$01
+CACB   20 F8 C9   JSR $C9F8
+CACE   20 3D C9   JSR $C93D
+CAD1   A6 58      LDX $58
+CAD3   DE F8 04   DEC $04F8,X
+CAD6   D0 EC      BNE $CAC4
+CAD8   60         RTS
+CAD9   00         BRK
+CADA   24 49      BIT $49
+CADC   00         BRK
+CADD   04         ???
+CADE   01 00      ORA ($00,X)
+CAE0   01 02      ORA ($02,X)
+CAE2   04         ???
+CAE3   09 12      ORA #$12
+CAE5   00         BRK
+CAE6   01 02      ORA ($02,X)
+CAE8   04         ???
+CAE9   01 02      ORA ($02,X)
+CAEB   00         BRK
+CAEC   7F         ???
+CAED   FF         ???
+CAEE   A6 4E      LDX $4E
+CAF0   F0 13      BEQ $CB05
+CAF2   A5 55      LDA $55
+CAF4   85 57      STA $57
+CAF6   A9 80      LDA #$80
+CAF8   E0 01      CPX #$01
+CAFA   F0 04      BEQ $CB00
+CAFC   E6 57      INC $57
+CAFE   A9 00      LDA #$00
+CB00   18         CLC
+CB01   65 54      ADC $54
+CB03   85 56      STA $56
+CB05   BD D9 CA   LDA $CAD9,X
+CB08   85 4B      STA $4B
+CB0A   BD DC CA   LDA $CADC,X
+CB0D   85 4C      STA $4C
+CB0F   A2 05      LDX #$05
+CB11   A5 4D      LDA $4D
+CB13   85 59      STA $59
+CB15   29 07      AND #$07
+CB17   A8         TAY
+CB18   06 59      ASL $59
+CB1A   90 15      BCC $CB31
+CB1C   BD E5 CA   LDA $CAE5,X
+CB1F   18         CLC
+CB20   65 4C      ADC $4C
+CB22   C9 07      CMP #$07
+CB24   90 02      BCC $CB28
+CB26   E9 07      SBC #$07
+CB28   85 4C      STA $4C
+CB2A   BD DF CA   LDA $CADF,X
+CB2D   65 4B      ADC $4B
+CB2F   85 4B      STA $4B
+CB31   CA         DEX
+CB32   30 06      BMI $CB3A
+CB34   D0 E2      BNE $CB18
+CB36   98         TYA
+CB37   4C 1F CB   JMP $CB1F
+CB3A   A5 55      LDA $55
+CB3C   48         PHA
+CB3D   A9 00      LDA #$00
+CB3F   A6 4E      LDX $4E
+CB41   F0 16      BEQ $CB59
+CB43   BC EB CA   LDY $CAEB,X
+CB46   51 54      EOR ($54),Y
+CB48   51 56      EOR ($56),Y
+CB4A   88         DEY
+CB4B   D0 F9      BNE $CB46
+CB4D   51 54      EOR ($54),Y
+CB4F   51 56      EOR ($56),Y
+CB51   E0 01      CPX #$01
+CB53   F0 02      BEQ $CB57
+CB55   E6 55      INC $55
+CB57   E6 55      INC $55
+CB59   A4 4D      LDY $4D
+CB5B   F0 09      BEQ $CB66
+CB5D   51 54      EOR ($54),Y
+CB5F   51 54      EOR ($54),Y
+CB61   88         DEY
+CB62   D0 FB      BNE $CB5F
+CB64   51 54      EOR ($54),Y
+CB66   85 40      STA $40
+CB68   68         PLA
+CB69   85 55      STA $55
+CB6B   A4 4C      LDY $4C
+CB6D   88         DEY
+CB6E   A9 00      LDA #$00
+CB70   85 59      STA $59
+CB72   B1 54      LDA ($54),Y
+CB74   0A         ASL A
+CB75   66 59      ROR $59
+CB77   88         DEY
+CB78   10 F8      BPL $CB72
+CB7A   38         SEC
+CB7B   66 59      ROR $59
+CB7D   A5 4C      LDA $4C
+CB7F   18         CLC
+CB80   65 54      ADC $54
+CB82   85 56      STA $56
+CB84   A5 55      LDA $55
+CB86   69 00      ADC #$00
+CB88   85 57      STA $57
+CB8A   A0 06      LDY #$06
+CB8C   38         SEC
+CB8D   B1 56      LDA ($56),Y
+CB8F   99 4D 00   STA $004D,Y
+CB92   30 01      BMI $CB95
+CB94   18         CLC
+CB95   66 41      ROR $41
+CB97   88         DEY
+CB98   10 F2      BPL $CB8C
+CB9A   38         SEC
+CB9B   66 41      ROR $41
+CB9D   A5 56      LDA $56
+CB9F   18         CLC
+CBA0   69 07      ADC #$07
+CBA2   85 56      STA $56
+CBA4   90 02      BCC $CBA8
+CBA6   E6 57      INC $57
+CBA8   60         RTS
+CBA9   BD 88 C0   LDA $C088,X
+CBAC   BD 8D C0   LDA $C08D,X
+CBAF   4C B6 CB   JMP $CBB6
+CBB2   98         TYA
+CBB3   9D 8F C0   STA $C08F,X
+CBB6   98         TYA
+CBB7   5D 8E C0   EOR $C08E,X
+CBBA   29 1F      AND #$1F
+CBBC   D0 F4      BNE $CBB2
+CBBE   60         RTS
+CBBF   A5 4B      LDA $4B
+CBC1   A8         TAY
+CBC2   A2 00      LDX #$00
+CBC4   86 4B      STX $4B
+CBC6   A2 03      LDX #$03
+CBC8   0A         ASL A
+CBC9   26 4B      ROL $4B
+CBCB   CA         DEX
+CBCC   D0 FA      BNE $CBC8
+CBCE   18         CLC
+CBCF   65 4C      ADC $4C
+CBD1   90 02      BCC $CBD5
+CBD3   E6 4B      INC $4B
+CBD5   84 4C      STY $4C
+CBD7   38         SEC
+CBD8   E5 4C      SBC $4C
+CBDA   B0 02      BCS $CBDE
+CBDC   C6 4B      DEC $4B
+CBDE   A4 4B      LDY $4B
+CBE0   60         RTS
+CBE1   90 03      BCC $CBE6
+CBE3   4C 59 CE   JMP $CE59
+CBE6   D8         CLD
+CBE7   8A         TXA
+CBE8   A8         TAY
+CBE9   B9 78 04   LDA $0478,Y
+CBEC   30 11      BMI $CBFF
+CBEE   68         PLA
+CBEF   99 F8 05   STA $05F8,Y
+CBF2   18         CLC
+CBF3   69 03      ADC #$03
+CBF5   AA         TAX
+CBF6   68         PLA
+CBF7   99 78 06   STA $0678,Y
+CBFA   69 00      ADC #$00
+CBFC   48         PHA
+CBFD   8A         TXA
+CBFE   48         PHA
+CBFF   08         PHP
+CC00   78         SEI
+CC01   A2 1B      LDX #$1B
+CC03   B5 40      LDA $40,X
+CC05   48         PHA
+CC06   CA         DEX
+CC07   10 FA      BPL $CC03
+CC09   84 58      STY $58
+CC0B   B9 F8 06   LDA $06F8,Y
+CC0E   C9 A5      CMP #$A5
+CC10   D0 07      BNE $CC19
+CC12   49 FF      EOR #$FF
+CC14   59 78 07   EOR $0778,Y
+CC17   F0 05      BEQ $CC1E
+CC19   A9 00      LDA #$00
+CC1B   20 ED CD   JSR $CDED
+CC1E   A5 43      LDA $43
+CC20   2A         ROL A
+CC21   08         PHP
+CC22   2A         ROL A
+CC23   2A         ROL A
+CC24   28         PLP
+CC25   2A         ROL A
+CC26   29 03      AND #$03
+CC28   49 02      EOR #$02
+CC2A   C0 04      CPY #$04
+CC2C   B0 02      BCS $CC30
+CC2E   49 02      EOR #$02
+CC30   AA         TAX
+CC31   E8         INX
+CC32   86 43      STX $43
+CC34   B9 78 04   LDA $0478,Y
+CC37   10 03      BPL $CC3C
+CC39   4C CF CC   JMP $CCCF
+CC3C   B9 F8 05   LDA $05F8,Y
+CC3F   85 54      STA $54
+CC41   B9 78 06   LDA $0678,Y
+CC44   85 55      STA $55
+CC46   A0 01      LDY #$01
+CC48   B1 54      LDA ($54),Y
+CC4A   85 42      STA $42
+CC4C   C8         INY
+CC4D   B1 54      LDA ($54),Y
+CC4F   AA         TAX
+CC50   C8         INY
+CC51   B1 54      LDA ($54),Y
+CC53   85 55      STA $55
+CC55   86 54      STX $54
+CC57   A9 01      LDA #$01
+CC59   A6 42      LDX $42
+CC5B   E0 0A      CPX #$0A
+CC5D   90 03      BCC $CC62
+CC5F   4C 9F CD   JMP $CD9F
+CC62   A0 00      LDY #$00
+CC64   B1 54      LDA ($54),Y
+CC66   85 5A      STA $5A
+CC68   A0 08      LDY #$08
+CC6A   B1 54      LDA ($54),Y
+CC6C   99 42 00   STA $0042,Y
+CC6F   88         DEY
+CC70   D0 F8      BNE $CC6A
+CC72   A5 43      LDA $43
+CC74   D0 59      BNE $CCCF
+CC76   A6 42      LDX $42
+CC78   BD E3 CD   LDA $CDE3,X
+CC7B   29 7F      AND #$7F
+CC7D   A8         TAY
+CC7E   A9 04      LDA #$04
+CC80   C4 5A      CPY $5A
+CC82   D0 DB      BNE $CC5F
+CC84   E0 05      CPX #$05
+CC86   D0 0A      BNE $CC92
+CC88   A9 00      LDA #$00
+CC8A   20 ED CD   JSR $CDED
+CC8D   A9 00      LDA #$00
+CC8F   4C C1 CD   JMP $CDC1
+CC92   8A         TXA
+CC93   D0 23      BNE $CCB8
+CC95   A9 21      LDA #$21
+CC97   A6 46      LDX $46
+CC99   D0 C4      BNE $CC5F
+CC9B   8A         TXA
+CC9C   A6 58      LDX $58
+CC9E   A0 07      LDY #$07
+CCA0   91 44      STA ($44),Y
+CCA2   88         DEY
+CCA3   D0 FB      BNE $CCA0
+CCA5   BD F8 07   LDA $07F8,X
+CCA8   91 44      STA ($44),Y
+CCAA   C8         INY
+CCAB   A9 00      LDA #$00
+CCAD   91 44      STA ($44),Y
+CCAF   A9 08      LDA #$08
+CCB1   88         DEY
+CCB2   20 4F CE   JSR $CE4F
+CCB5   4C 8D CC   JMP $CC8D
+CCB8   C9 04      CMP #$04
+CCBA   D0 0B      BNE $CCC7
+CCBC   A6 46      LDX $46
+CCBE   F0 0B      BEQ $CCCB
+CCC0   CA         DEX
+CCC1   F0 08      BEQ $CCCB
+CCC3   A9 21      LDA #$21
+CCC5   D0 98      BNE $CC5F
+CCC7   A9 11      LDA #$11
+CCC9   D0 94      BNE $CC5F
+CCCB   A9 1F      LDA #$1F
+CCCD   D0 90      BNE $CC5F
+CCCF   A9 28      LDA #$28
+CCD1   A4 58      LDY $58
+CCD3   BE F8 07   LDX $07F8,Y
+CCD6   E4 43      CPX $43
+CCD8   90 EB      BCC $CCC5
+CCDA   A9 09      LDA #$09
+CCDC   85 4D      STA $4D
+CCDE   A9 00      LDA #$00
+CCE0   85 4E      STA $4E
+CCE2   85 55      STA $55
+CCE4   A9 42      LDA #$42
+CCE6   85 54      STA $54
+CCE8   A6 58      LDX $58
+CCEA   BD 78 04   LDA $0478,X
+CCED   10 13      BPL $CD02
+CCEF   A6 42      LDX $42
+CCF1   BD E3 CD   LDA $CDE3,X
+CCF4   29 7F      AND #$7F
+CCF6   85 5A      STA $5A
+CCF8   A9 00      LDA #$00
+CCFA   85 48      STA $48
+CCFC   A5 42      LDA $42
+CCFE   D0 02      BNE $CD02
+CD00   85 46      STA $46
+CD02   A5 5A      LDA $5A
+CD04   A6 43      LDX $43
+CD06   86 5A      STX $5A
+CD08   85 43      STA $43
+CD0A   A9 80      LDA #$80
+CD0C   85 5B      STA $5B
+CD0E   20 0F CA   JSR $CA0F
+CD11   20 76 CA   JSR $CA76
+CD14   B0 46      BCS $CD5C
+CD16   A5 44      LDA $44
+CD18   85 54      STA $54
+CD1A   A5 45      LDA $45
+CD1C   85 55      STA $55
+CD1E   A6 42      LDX $42
+CD20   BD E3 CD   LDA $CDE3,X
+CD23   10 3B      BPL $CD60
+CD25   E0 04      CPX #$04
+CD27   D0 18      BNE $CD41
+CD29   A0 01      LDY #$01
+CD2B   B1 54      LDA ($54),Y
+CD2D   AA         TAX
+CD2E   88         DEY
+CD2F   B1 54      LDA ($54),Y
+CD31   48         PHA
+CD32   18         CLC
+CD33   A9 02      LDA #$02
+CD35   65 54      ADC $54
+CD37   85 54      STA $54
+CD39   68         PLA
+CD3A   90 13      BCC $CD4F
+CD3C   E6 55      INC $55
+CD3E   4C 4F CD   JMP $CD4F
+CD41   E0 02      CPX #$02
+CD43   D0 06      BNE $CD4B
+CD45   A9 00      LDA #$00
+CD47   A2 02      LDX #$02
+CD49   D0 04      BNE $CD4F
+CD4B   A6 47      LDX $47
+CD4D   A5 46      LDA $46
+CD4F   86 4E      STX $4E
+CD51   85 4D      STA $4D
+CD53   A9 82      LDA #$82
+CD55   85 5B      STA $5B
+CD57   20 67 CA   JSR $CA67
+CD5A   90 04      BCC $CD60
+CD5C   A9 06      LDA #$06
+CD5E   D0 3F      BNE $CD9F
+CD60   A4 58      LDY $58
+CD62   B9 78 04   LDA $0478,Y
+CD65   10 0C      BPL $CD73
+CD67   A5 42      LDA $42
+CD69   D0 08      BNE $CD73
+CD6B   A9 45      LDA #$45
+CD6D   A2 00      LDX #$00
+CD6F   85 54      STA $54
+CD71   86 55      STX $55
+CD73   20 BD CA   JSR $CABD
+CD76   B0 E4      BCS $CD5C
+CD78   20 BF CB   JSR $CBBF
+CD7B   20 4F CE   JSR $CE4F
+CD7E   A5 42      LDA $42
+CD80   D0 1B      BNE $CD9D
+CD82   A6 58      LDX $58
+CD84   BD 78 04   LDA $0478,X
+CD87   10 14      BPL $CD9D
+CD89   A5 46      LDA $46
+CD8B   9D F8 05   STA $05F8,X
+CD8E   A5 47      LDA $47
+CD90   9D 78 06   STA $0678,X
+CD93   A5 45      LDA $45
+CD95   29 10      AND #$10
+CD97   D0 04      BNE $CD9D
+CD99   A9 2F      LDA #$2F
+CD9B   D0 02      BNE $CD9F
+CD9D   A5 4D      LDA $4D
+CD9F   A4 58      LDY $58
+CDA1   99 F8 04   STA $04F8,Y
+CDA4   AA         TAX
+CDA5   F0 1A      BEQ $CDC1
+CDA7   BE 78 04   LDX $0478,Y
+CDAA   10 15      BPL $CDC1
+CDAC   A2 00      LDX #$00
+CDAE   C9 40      CMP #$40
+CDB0   B0 0E      BCS $CDC0
+CDB2   A2 27      LDX #$27
+CDB4   C9 2B      CMP #$2B
+CDB6   F0 09      BEQ $CDC1
+CDB8   C9 28      CMP #$28
+CDBA   F0 05      BEQ $CDC1
+CDBC   C9 2F      CMP #$2F
+CDBE   F0 01      BEQ $CDC1
+CDC0   8A         TXA
+CDC1   A4 58      LDY $58
+CDC3   99 78 05   STA $0578,Y
+CDC6   A2 00      LDX #$00
+CDC8   68         PLA
+CDC9   95 40      STA $40,X
+CDCB   E8         INX
+CDCC   E0 1C      CPX #$1C
+CDCE   90 F8      BCC $CDC8
+CDD0   28         PLP
+CDD1   B9 F8 05   LDA $05F8,Y
+CDD4   AA         TAX
+CDD5   B9 78 05   LDA $0578,Y
+CDD8   48         PHA
+CDD9   B9 78 06   LDA $0678,Y
+CDDC   A8         TAY
+CDDD   18         CLC
+CDDE   68         PLA
+CDDF   F0 01      BEQ $CDE2
+CDE1   38         SEC
+CDE2   60         RTS
+CDE3   03         ???
+CDE4   03         ???
+CDE5   83         ???
+CDE6   01 83      ORA ($83,X)
+CDE8   01 01      ORA ($01,X)
+CDEA   01 03      ORA ($03,X)
+CDEC   83         ???
+CDED   48         PHA
+CDEE   20 E5 C9   JSR $C9E5
+CDF1   68         PLA
+CDF2   AA         TAX
+CDF3   A5 42      LDA $42
+CDF5   48         PHA
+CDF6   A5 43      LDA $43
+CDF8   48         PHA
+CDF9   A5 46      LDA $46
+CDFB   48         PHA
+CDFC   86 46      STX $46
+CDFE   A9 05      LDA #$05
+CE00   85 42      STA $42
+CE02   A9 00      LDA #$00
+CE04   85 5A      STA $5A
+CE06   A9 02      LDA #$02
+CE08   85 43      STA $43
+CE0A   A9 42      LDA #$42
+CE0C   85 54      STA $54
+CE0E   A9 00      LDA #$00
+CE10   85 55      STA $55
+CE12   A9 80      LDA #$80
+CE14   85 5B      STA $5B
+CE16   20 0F CA   JSR $CA0F
+CE19   E6 5A      INC $5A
+CE1B   A9 09      LDA #$09
+CE1D   85 4D      STA $4D
+CE1F   A9 00      LDA #$00
+CE21   85 4E      STA $4E
+CE23   20 00 C8   JSR $C800
+CE26   90 05      BCC $CE2D
+CE28   C6 5A      DEC $5A
+CE2A   4C 34 CE   JMP $CE34
+CE2D   20 60 C9   JSR $C960
+CE30   A5 4D      LDA $4D
+CE32   F0 E5      BEQ $CE19
+CE34   A5 5A      LDA $5A
+CE36   A4 58      LDY $58
+CE38   99 F8 07   STA $07F8,Y
+CE3B   68         PLA
+CE3C   85 46      STA $46
+CE3E   68         PLA
+CE3F   85 43      STA $43
+CE41   68         PLA
+CE42   85 42      STA $42
+CE44   A9 A5      LDA #$A5
+CE46   99 F8 06   STA $06F8,Y
+CE49   49 FF      EOR #$FF
+CE4B   99 78 07   STA $0778,Y
+CE4E   60         RTS
+CE4F   A6 58      LDX $58
+CE51   9D F8 05   STA $05F8,X
+CE54   98         TYA
+CE55   9D 78 06   STA $0678,X
+CE58   60         RTS
+CE59   86 58      STX $58
+CE5B   A9 AA      LDA #$AA
+CE5D   9D 78 04   STA $0478,X
+CE60   9D F8 06   STA $06F8,X
+CE63   A0 05      LDY #$05
+CE65   B9 16 CF   LDA $CF16,Y
+CE68   99 42 00   STA $0042,Y
+CE6B   88         DEY
+CE6C   10 F7      BPL $CE65
+CE6E   A5 58      LDA $58
+CE70   0A         ASL A
+CE71   0A         ASL A
+CE72   0A         ASL A
+CE73   0A         ASL A
+CE74   85 43      STA $43
+CE76   20 E6 CB   JSR $CBE6
+CE79   B0 15      BCS $CE90
+CE7B   AE 00 08   LDX $0800
+CE7E   CA         DEX
+CE7F   D0 0F      BNE $CE90
+CE81   AE 01 08   LDX $0801
+CE84   F0 0A      BEQ $CE90
+CE86   A5 58      LDA $58
+CE88   0A         ASL A
+CE89   0A         ASL A
+CE8A   0A         ASL A
+CE8B   0A         ASL A
+CE8C   AA         TAX
+CE8D   4C 01 08   JMP $0801
+CE90   20 93 FE   JSR $FE93
+CE93   20 89 FE   JSR $FE89
+CE96   A6 00      LDX $00
+CE98   D0 0A      BNE $CEA4
+CE9A   A6 01      LDX $01
+CE9C   EC F8 07   CPX $07F8
+CE9F   D0 03      BNE $CEA4
+CEA1   4C BA FA   JMP $FABA
+CEA4   A2 17      LDX #$17
+CEA6   86 25      STX $25
+CEA8   20 22 FC   JSR $FC22
+CEAB   A9 00      LDA #$00
+CEAD   85 24      STA $24
+CEAF   A2 00      LDX #$00
+CEB1   A4 58      LDY $58
+CEB3   B9 F8 04   LDA $04F8,Y
+CEB6   D0 02      BNE $CEBA
+CEB8   A2 0A      LDX #$0A
+CEBA   C9 28      CMP #$28
+CEBC   D0 02      BNE $CEC0
+CEBE   A2 1E      LDX #$1E
+CEC0   C9 2F      CMP #$2F
+CEC2   D0 02      BNE $CEC6
+CEC4   A2 32      LDX #$32
+CEC6   BD D4 CE   LDA $CED4,X
+CEC9   F0 06      BEQ $CED1
+CECB   20 ED FD   JSR $FDED
+CECE   E8         INX
+CECF   D0 F5      BNE $CEC6
+CED1   4C 00 E0   JMP $E000
+CED4   C9 AF      CMP #$AF
+CED6   CF         ???
+CED7   A0 C5      LDY #$C5
+CED9   D2         ???
+CEDA   D2         ???
+CEDB   CF         ???
+CEDC   D2         ???
+CEDD   00         BRK
+CEDE   CE CF D4   DEC $D4CF
+CEE1   A0 C1      LDY #$C1
+CEE3   A0 C2      LDY #$C2
+CEE5   CF         ???
+CEE6   CF         ???
+CEE7   D4         ???
+CEE8   C1 C2      CMP ($C2,X)
+CEEA   CC C5 A0   CPY $A0C5
+CEED   C4 C9      CPY $C9
+CEEF   D3         ???
+CEF0   CB         ???
+CEF1   00         BRK
+CEF2   CE CF A0   DEC $A0CF
+CEF5   C4 C5      CPY $C5
+CEF7   D6 C9      DEC $C9,X
+CEF9   C3         ???
+CEFA   C5 A0      CMP $A0
+CEFC   C3         ???
+CEFD   CF         ???
+CEFE   CE CE C5   DEC $C5CE
+CF01   C3         ???
+CF02   D4         ???
+CF03   C5 C4      CMP $C4
+CF05   00         BRK
+CF06   CE CF A0   DEC $A0CF
+CF09   C4 C9      CPY $C9
+CF0B   D3         ???
+CF0C   CB         ???
+CF0D   A0 D4      LDY #$D4
+CF0F   CF         ???
+CF10   A0 C2      LDY #$C2
+CF12   CF         ???
+CF13   CF         ???
+CF14   D4         ???
+CF15   00         BRK
+CF16   01 50      ORA ($50,X)
+CF18   00         BRK
+CF19   08         PHP
+CF1A   00         BRK
+CF1B   00         BRK
+CF1C   FF         ???
+CF1D   FF         ???
+CF1E   FF         ???
+CF1F   FF         ???
+CF20   FF         ???
+CF21   FF         ???
+CF22   FF         ???
+CF23   FF         ???
+CF24   FF         ???
+CF25   FF         ???
+CF26   FF         ???
+CF27   FF         ???
+CF28   FF         ???
+CF29   FF         ???
+CF2A   FF         ???
+CF2B   FF         ???
+CF2C   FF         ???
+CF2D   FF         ???
+CF2E   FF         ???
+CF2F   FF         ???
+CF30   FF         ???
+CF31   FF         ???
+CF32   FF         ???
+CF33   FF         ???
+CF34   FF         ???
+CF35   FF         ???
+CF36   FF         ???
+CF37   FF         ???
+CF38   FF         ???
+CF39   FF         ???
+CF3A   FF         ???
+CF3B   FF         ???
+CF3C   FF         ???
+CF3D   FF         ???
+CF3E   FF         ???
+CF3F   FF         ???
+CF40   FF         ???
+CF41   FF         ???
+CF42   FF         ???
+CF43   FF         ???
+CF44   FF         ???
+CF45   FF         ???
+CF46   FF         ???
+CF47   FF         ???
+CF48   FF         ???
+CF49   FF         ???
+CF4A   FF         ???
+CF4B   FF         ???
+CF4C   FF         ???
+CF4D   FF         ???
+CF4E   FF         ???
+CF4F   FF         ???
+CF50   FF         ???
+CF51   FF         ???
+CF52   FF         ???
+CF53   FF         ???
+CF54   FF         ???
+CF55   FF         ???
+CF56   FF         ???
+CF57   FF         ???
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+CF59   FF         ???
+CF5A   FF         ???
+CF5B   FF         ???
+CF5C   FF         ???
+CF5D   FF         ???
+CF5E   FF         ???
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+CF60   FF         ???
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+CF90   FF         ???
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+CF99   FF         ???
+CF9A   FF         ???
+CF9B   FF         ???
+CF9C   FF         ???
+CF9D   FF         ???
+CF9E   FF         ???
+CF9F   FF         ???
+CFA0   FF         ???
+CFA1   FF         ???
+CFA2   FF         ???
+CFA3   FF         ???
+CFA4   FF         ???
+CFA5   FF         ???
+CFA6   FF         ???
+CFA7   FF         ???
+CFA8   FF         ???
+CFA9   FF         ???
+CFAA   FF         ???
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+CFAD   FF         ???
+CFAE   FF         ???
+CFAF   FF         ???
+CFB0   FF         ???
+CFB1   FF         ???
+CFB2   FF         ???
+CFB3   FF         ???
+CFB4   FF         ???
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+CFC2   FF         ???
+CFC3   FF         ???
+CFC4   FF         ???
+CFC5   FF         ???
+CFC6   FF         ???
+CFC7   FF         ???
+CFC8   FF         ???
+CFC9   FF         ???
+CFCA   FF         ???
+CFCB   FF         ???
+CFCC   FF         ???
+CFCD   FF         ???
+CFCE   FF         ???
+CFCF   FF         ???
+CFD0   FF         ???
+CFD1   FF         ???
+CFD2   FF         ???
+CFD3   FF         ???
+CFD4   FF         ???
+CFD5   FF         ???
+CFD6   FF         ???
+CFD7   FF         ???
+CFD8   FF         ???
+CFD9   FF         ???
+CFDA   FF         ???
+CFDB   A8         TAY
+CFDC   C3         ???
+CFDD   A9 A0      LDA #$A0
+CFDF   B1 B9      LDA ($B9),Y
+CFE1   B8         CLV
+CFE2   B5 A0      LDA $A0,X
+CFE4   C1 F0      CMP ($F0,X)
+CFE6   F0 EC      BEQ $CFD4
+CFE8   E5 A0      SBC $A0
+CFEA   C3         ???
+CFEB   EF         ???
+CFEC   ED F0 F5   SBC $F5F0
+CFEF   F4         ???
+CFF0   E5 F2      SBC $F2
+CFF2   AC A0 C9   LDY $C9A0
+CFF5   EE E3 AE   INC $AEE3
+CFF8   A0 CD      LDY #$CD
+CFFA   D3         ???
+CFFB   C1 00      CMP ($00,X)
+CFFD   10 FF      BPL $CFFE
+CFFF              .END
diff --git a/liron.wrk b/liron.wrk
new file mode 100644
index 0000000..6af34fd
Binary files /dev/null and b/liron.wrk differ
diff --git a/promote.xml b/promote.xml
new file mode 100644
index 0000000..894cb95
--- /dev/null
+++ b/promote.xml
@@ -0,0 +1,4 @@
+
+
+  
+
diff --git a/reportview.xml b/reportview.xml
new file mode 100644
index 0000000..1d65835
--- /dev/null
+++ b/reportview.xml
@@ -0,0 +1,10 @@
+
+
+
+    
+        
+        
+        
+        
+    
+
diff --git a/rom-full-4k.mem b/rom-full-4k.mem
new file mode 100644
index 0000000..686ff37
--- /dev/null
+++ b/rom-full-4k.mem
@@ -0,0 +1,4102 @@
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+#Depth=4096
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+C5
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+00
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+D4
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+00
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+00
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+FF
+FF
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+FF
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+FF
+FF
+FF
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+FF
+FF
+FF
+FF
+FF
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+FF
+FF
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+FF
+FF
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+FF
+FF
+FF
+FF
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+FF
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+FF
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+FF
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+FF
+FF
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+FF
+FF
+FF
+FF
+FF
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+FF
+FF
+FF
+FF
+FF
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+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
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+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
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+FF
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+FF
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+FF
+FF
+FF
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+FF
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+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+FF
+A8
+C3
+A9
+A0
+B1
+B9
+B8
+B5
+A0
+C1
+F0
+F0
+EC
+E5
+A0
+C3
+EF
+ED
+F0
+F5
+F4
+E5
+F2
+AC
+A0
+C9
+EE
+E3
+AE
+A0
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+D3
+C1
+00
+10
+FF
+FF
\ No newline at end of file
diff --git a/top.v b/top.v
new file mode 100644
index 0000000..c76ce5e
--- /dev/null
+++ b/top.v
@@ -0,0 +1,27 @@
+module blink (
+  output pin_led,
+  output en_245
+);
+
+  wire clk;
+  
+  OSCH #(
+    .NOM_FREQ("2.08")
+  ) internal_oscillator_inst (
+    .STDBY(1'b0), 
+    .OSC(clk)
+  ); 
+  
+  reg [23:0] led_timer;
+  
+  always @(posedge clk) begin
+    led_timer <= led_timer + 1; 
+  end
+  
+  //assign pin_led = led_timer[23];
+  //assign pin_led = led_timer[22];
+  assign pin_led = led_timer[20];
+  
+  assign en_245 = 1'b1;
+  
+endmodule
\ No newline at end of file
diff --git a/yellowstone_blink.ccl b/yellowstone_blink.ccl
new file mode 100644
index 0000000..dcf391b
--- /dev/null
+++ b/yellowstone_blink.ccl
@@ -0,0 +1 @@
+VERSION=20110520
diff --git a/yellowstone_blink.ldf b/yellowstone_blink.ldf
new file mode 100644
index 0000000..c1ccdcc
--- /dev/null
+++ b/yellowstone_blink.ldf
@@ -0,0 +1,17 @@
+
+
+    
+    
+        
+        
+            
+        
+        
+            
+        
+        
+            
+        
+    
+    
+
diff --git a/yellowstone_blink.lpf b/yellowstone_blink.lpf
new file mode 100644
index 0000000..0ba2c4a
--- /dev/null
+++ b/yellowstone_blink.lpf
@@ -0,0 +1,6 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+IOBUF PORT "pin_led" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+LOCATE COMP "pin_led" SITE "25" ;
+IOBUF PORT "en_245" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+LOCATE COMP "en_245" SITE "30" ;
diff --git a/yellowstone_blink/.build_status b/yellowstone_blink/.build_status
new file mode 100644
index 0000000..431031b
--- /dev/null
+++ b/yellowstone_blink/.build_status
@@ -0,0 +1,40 @@
+
+
+    
+        
+            
+            
+            
+            
+            
+        
+        
+            
+            
+            
+            
+        
+        
+            
+            
+            
+        
+        
+            
+            
+        
+        
+            
+            
+            
+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+
diff --git a/yellowstone_blink/.vdbs/blink_rtl.vdb b/yellowstone_blink/.vdbs/blink_rtl.vdb
new file mode 100644
index 0000000..fae551e
Binary files /dev/null and b/yellowstone_blink/.vdbs/blink_rtl.vdb differ
diff --git a/yellowstone_blink/.vdbs/blink_tech.vdb b/yellowstone_blink/.vdbs/blink_tech.vdb
new file mode 100644
index 0000000..722a608
Binary files /dev/null and b/yellowstone_blink/.vdbs/blink_tech.vdb differ
diff --git a/yellowstone_blink/.vdbs/dbStat.txt b/yellowstone_blink/.vdbs/dbStat.txt
new file mode 100644
index 0000000..cc71bb1
--- /dev/null
+++ b/yellowstone_blink/.vdbs/dbStat.txt
@@ -0,0 +1 @@
+blink_rtl.vdb
diff --git a/yellowstone_blink/.vdbs/yellowstone_blink_yellowstone_blink_map.vdb b/yellowstone_blink/.vdbs/yellowstone_blink_yellowstone_blink_map.vdb
new file mode 100644
index 0000000..a5e944f
Binary files /dev/null and b/yellowstone_blink/.vdbs/yellowstone_blink_yellowstone_blink_map.vdb differ
diff --git a/yellowstone_blink/blink_lse.twr b/yellowstone_blink/blink_lse.twr
new file mode 100644
index 0000000..1513c1a
--- /dev/null
+++ b/yellowstone_blink/blink_lse.twr
@@ -0,0 +1,189 @@
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Thu Oct 05 12:19:47 2017
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     blink
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 1000.000000 -name clk0 [get_nets clk]
+            241 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 994.476ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             led_timer_9_10__i0  (from clk +)
+   Destination:    FD1S3AX    D              led_timer_9_10__i19  (to clk +)
+
+   Delay:                   5.364ns  (61.2% logic, 38.8% route), 12 logic levels.
+
+ Constraint Details:
+
+      5.364ns data_path led_timer_9_10__i0 to led_timer_9_10__i19 meets
+    1000.000ns delay constraint less
+      0.160ns L_S requirement (totaling 999.840ns) by 994.476ns
+
+ Path Details: led_timer_9_10__i0 to led_timer_9_10__i19
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              led_timer_9_10__i0 (from clk)
+Route         1   e 0.941                                  n21
+A1_TO_FCO   ---     0.827           A[2] to COUT           led_timer_9_10_add_4_1
+Route         1   e 0.020                                  n135
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_3
+Route         1   e 0.020                                  n136
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_5
+Route         1   e 0.020                                  n137
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_7
+Route         1   e 0.020                                  n138
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_9
+Route         1   e 0.020                                  n139
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_11
+Route         1   e 0.020                                  n140
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_13
+Route         1   e 0.020                                  n141
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_15
+Route         1   e 0.020                                  n142
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_17
+Route         1   e 0.020                                  n143
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_19
+Route         1   e 0.020                                  n144
+FCI_TO_F    ---     0.598            CIN to S[2]           led_timer_9_10_add_4_21
+Route         1   e 0.941                                  n91
+                  --------
+                    5.364  (61.2% logic, 38.8% route), 12 logic levels.
+
+
+Passed:  The following path meets requirements by 994.476ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             led_timer_9_10__i0  (from clk +)
+   Destination:    FD1S3AX    D              led_timer_9_10__i20  (to clk +)
+
+   Delay:                   5.364ns  (61.2% logic, 38.8% route), 12 logic levels.
+
+ Constraint Details:
+
+      5.364ns data_path led_timer_9_10__i0 to led_timer_9_10__i20 meets
+    1000.000ns delay constraint less
+      0.160ns L_S requirement (totaling 999.840ns) by 994.476ns
+
+ Path Details: led_timer_9_10__i0 to led_timer_9_10__i20
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              led_timer_9_10__i0 (from clk)
+Route         1   e 0.941                                  n21
+A1_TO_FCO   ---     0.827           A[2] to COUT           led_timer_9_10_add_4_1
+Route         1   e 0.020                                  n135
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_3
+Route         1   e 0.020                                  n136
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_5
+Route         1   e 0.020                                  n137
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_7
+Route         1   e 0.020                                  n138
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_9
+Route         1   e 0.020                                  n139
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_11
+Route         1   e 0.020                                  n140
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_13
+Route         1   e 0.020                                  n141
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_15
+Route         1   e 0.020                                  n142
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_17
+Route         1   e 0.020                                  n143
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_19
+Route         1   e 0.020                                  n144
+FCI_TO_F    ---     0.598            CIN to S[2]           led_timer_9_10_add_4_21
+Route         1   e 0.941                                  n90
+                  --------
+                    5.364  (61.2% logic, 38.8% route), 12 logic levels.
+
+
+Passed:  The following path meets requirements by 994.653ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             led_timer_9_10__i0  (from clk +)
+   Destination:    FD1S3AX    D              led_timer_9_10__i17  (to clk +)
+
+   Delay:                   5.187ns  (60.2% logic, 39.8% route), 11 logic levels.
+
+ Constraint Details:
+
+      5.187ns data_path led_timer_9_10__i0 to led_timer_9_10__i17 meets
+    1000.000ns delay constraint less
+      0.160ns L_S requirement (totaling 999.840ns) by 994.653ns
+
+ Path Details: led_timer_9_10__i0 to led_timer_9_10__i17
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              led_timer_9_10__i0 (from clk)
+Route         1   e 0.941                                  n21
+A1_TO_FCO   ---     0.827           A[2] to COUT           led_timer_9_10_add_4_1
+Route         1   e 0.020                                  n135
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_3
+Route         1   e 0.020                                  n136
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_5
+Route         1   e 0.020                                  n137
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_7
+Route         1   e 0.020                                  n138
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_9
+Route         1   e 0.020                                  n139
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_11
+Route         1   e 0.020                                  n140
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_13
+Route         1   e 0.020                                  n141
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_15
+Route         1   e 0.020                                  n142
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_17
+Route         1   e 0.020                                  n143
+FCI_TO_F    ---     0.598            CIN to S[2]           led_timer_9_10_add_4_19
+Route         1   e 0.941                                  n93
+                  --------
+                    5.187  (60.2% logic, 39.8% route), 11 logic levels.
+
+Report: 5.524 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk0 [get_nets clk]                     |  1000.000 ns|     5.524 ns|    12  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+
+Timing summary:
+---------------
+
+Timing errors: 0  Score: 0
+
+Constraints cover  241 paths, 53 nets, and 73 connections (98.6% coverage)
+
+
+Peak memory: 51392512 bytes, TRCE: 1622016 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
diff --git a/yellowstone_blink/blink_lse_lsetwr.html b/yellowstone_blink/blink_lse_lsetwr.html
new file mode 100644
index 0000000..a061975
--- /dev/null
+++ b/yellowstone_blink/blink_lse_lsetwr.html
@@ -0,0 +1,254 @@
+
+Lattice Synthesis Timing Report
+
+
+
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Thu Oct 05 12:19:47 2017
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     blink
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 1000.000000 -name clk0 [get_nets clk]
+            241 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 994.476ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             led_timer_9_10__i0  (from clk +)
+   Destination:    FD1S3AX    D              led_timer_9_10__i19  (to clk +)
+
+   Delay:                   5.364ns  (61.2% logic, 38.8% route), 12 logic levels.
+
+ Constraint Details:
+
+      5.364ns data_path led_timer_9_10__i0 to led_timer_9_10__i19 meets
+    1000.000ns delay constraint less
+      0.160ns L_S requirement (totaling 999.840ns) by 994.476ns
+
+ Path Details: led_timer_9_10__i0 to led_timer_9_10__i19
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              led_timer_9_10__i0 (from clk)
+Route         1   e 0.941                                  n21
+A1_TO_FCO   ---     0.827           A[2] to COUT           led_timer_9_10_add_4_1
+Route         1   e 0.020                                  n135
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_3
+Route         1   e 0.020                                  n136
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_5
+Route         1   e 0.020                                  n137
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_7
+Route         1   e 0.020                                  n138
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_9
+Route         1   e 0.020                                  n139
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_11
+Route         1   e 0.020                                  n140
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_13
+Route         1   e 0.020                                  n141
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_15
+Route         1   e 0.020                                  n142
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_17
+Route         1   e 0.020                                  n143
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_19
+Route         1   e 0.020                                  n144
+FCI_TO_F    ---     0.598            CIN to S[2]           led_timer_9_10_add_4_21
+Route         1   e 0.941                                  n91
+                  --------
+                    5.364  (61.2% logic, 38.8% route), 12 logic levels.
+
+
+Passed:  The following path meets requirements by 994.476ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             led_timer_9_10__i0  (from clk +)
+   Destination:    FD1S3AX    D              led_timer_9_10__i20  (to clk +)
+
+   Delay:                   5.364ns  (61.2% logic, 38.8% route), 12 logic levels.
+
+ Constraint Details:
+
+      5.364ns data_path led_timer_9_10__i0 to led_timer_9_10__i20 meets
+    1000.000ns delay constraint less
+      0.160ns L_S requirement (totaling 999.840ns) by 994.476ns
+
+ Path Details: led_timer_9_10__i0 to led_timer_9_10__i20
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              led_timer_9_10__i0 (from clk)
+Route         1   e 0.941                                  n21
+A1_TO_FCO   ---     0.827           A[2] to COUT           led_timer_9_10_add_4_1
+Route         1   e 0.020                                  n135
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_3
+Route         1   e 0.020                                  n136
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_5
+Route         1   e 0.020                                  n137
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_7
+Route         1   e 0.020                                  n138
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_9
+Route         1   e 0.020                                  n139
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_11
+Route         1   e 0.020                                  n140
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_13
+Route         1   e 0.020                                  n141
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_15
+Route         1   e 0.020                                  n142
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_17
+Route         1   e 0.020                                  n143
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_19
+Route         1   e 0.020                                  n144
+FCI_TO_F    ---     0.598            CIN to S[2]           led_timer_9_10_add_4_21
+Route         1   e 0.941                                  n90
+                  --------
+                    5.364  (61.2% logic, 38.8% route), 12 logic levels.
+
+
+Passed:  The following path meets requirements by 994.653ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             led_timer_9_10__i0  (from clk +)
+   Destination:    FD1S3AX    D              led_timer_9_10__i17  (to clk +)
+
+   Delay:                   5.187ns  (60.2% logic, 39.8% route), 11 logic levels.
+
+ Constraint Details:
+
+      5.187ns data_path led_timer_9_10__i0 to led_timer_9_10__i17 meets
+    1000.000ns delay constraint less
+      0.160ns L_S requirement (totaling 999.840ns) by 994.653ns
+
+ Path Details: led_timer_9_10__i0 to led_timer_9_10__i17
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              led_timer_9_10__i0 (from clk)
+Route         1   e 0.941                                  n21
+A1_TO_FCO   ---     0.827           A[2] to COUT           led_timer_9_10_add_4_1
+Route         1   e 0.020                                  n135
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_3
+Route         1   e 0.020                                  n136
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_5
+Route         1   e 0.020                                  n137
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_7
+Route         1   e 0.020                                  n138
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_9
+Route         1   e 0.020                                  n139
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_11
+Route         1   e 0.020                                  n140
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_13
+Route         1   e 0.020                                  n141
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_15
+Route         1   e 0.020                                  n142
+FCI_TO_FCO  ---     0.157            CIN to COUT           led_timer_9_10_add_4_17
+Route         1   e 0.020                                  n143
+FCI_TO_F    ---     0.598            CIN to S[2]           led_timer_9_10_add_4_19
+Route         1   e 0.941                                  n93
+                  --------
+                    5.187  (60.2% logic, 39.8% route), 11 logic levels.
+
+Report: 5.524 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk0 [get_nets clk]                     |  1000.000 ns|     5.524 ns|    12  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+
+Timing summary:
+---------------
+
+Timing errors: 0  Score: 0
+
+Constraints cover  241 paths, 53 nets, and 73 connections (98.6% coverage)
+
+
+Peak memory: 51392512 bytes, TRCE: 1622016 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
+
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diff --git a/yellowstone_blink/blink_prim.v b/yellowstone_blink/blink_prim.v
new file mode 100644
index 0000000..7dc448a
--- /dev/null
+++ b/yellowstone_blink/blink_prim.v
@@ -0,0 +1,160 @@
+// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.9.0.99.2
+// Netlist written on Thu Oct 05 12:19:47 2017
+//
+// Verilog Description of module blink
+//
+
+module blink (pin_led, en_245) /* synthesis syn_module_defined=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(1[8:13])
+    output pin_led;   // c:/users/chamberlin/documents/liron/top.v(2[10:17])
+    output en_245;   // c:/users/chamberlin/documents/liron/top.v(3[10:16])
+    
+    wire clk /* synthesis SET_AS_NETWORK=clk, is_clock=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(6[8:11])
+    
+    wire GND_net, VCC_net, pin_led_c_20, n21, n20, n19, n18, n17, 
+        n16, n15, n14, n13, n12, n11, n10, n9, n8, n7, n6, 
+        n5, n4, n3, n2, n90, n91, n92, n93, n94, n95, n96, 
+        n97, n98, n99, n100, n101, n102, n103, n104, n105, 
+        n106, n107, n108, n109, n110, n135, n136, n137, n138, 
+        n139, n140, n141, n142, n143, n144;
+    
+    VHI i2 (.Z(VCC_net));
+    OSCH internal_oscillator_inst (.STDBY(GND_net), .OSC(clk)) /* synthesis syn_instantiated=1 */ ;
+    defparam internal_oscillator_inst.NOM_FREQ = "2.08";
+    OB pin_led_pad (.I(pin_led_c_20), .O(pin_led));   // c:/users/chamberlin/documents/liron/top.v(2[10:17])
+    TSALL TSALL_INST (.TSALL(GND_net));
+    OB en_245_pad (.I(VCC_net), .O(en_245));   // c:/users/chamberlin/documents/liron/top.v(3[10:16])
+    GSR GSR_INST (.GSR(VCC_net));
+    VLO i1 (.Z(GND_net));
+    PUR PUR_INST (.PUR(VCC_net));
+    defparam PUR_INST.RST_PULSE = 1;
+    CCU2D led_timer_9_10_add_4_21 (.A0(n2), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(pin_led_c_20), .B1(GND_net), .C1(GND_net), 
+          .D1(GND_net), .CIN(n144), .S0(n91), .S1(n90));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_21.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_21.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_21.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_21.INJECT1_1 = "NO";
+    CCU2D led_timer_9_10_add_4_19 (.A0(n4), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n3), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .CIN(n143), .COUT(n144), .S0(n93), .S1(n92));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_19.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_19.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_19.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_19.INJECT1_1 = "NO";
+    CCU2D led_timer_9_10_add_4_17 (.A0(n6), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n5), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .CIN(n142), .COUT(n143), .S0(n95), .S1(n94));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_17.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_17.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_17.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_17.INJECT1_1 = "NO";
+    CCU2D led_timer_9_10_add_4_15 (.A0(n8), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n7), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .CIN(n141), .COUT(n142), .S0(n97), .S1(n96));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_15.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_15.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_15.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_15.INJECT1_1 = "NO";
+    CCU2D led_timer_9_10_add_4_13 (.A0(n10), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n9), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .CIN(n140), .COUT(n141), .S0(n99), .S1(n98));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_13.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_13.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_13.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_13.INJECT1_1 = "NO";
+    CCU2D led_timer_9_10_add_4_11 (.A0(n12), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n11), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .CIN(n139), .COUT(n140), .S0(n101), .S1(n100));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_11.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_11.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_11.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_11.INJECT1_1 = "NO";
+    CCU2D led_timer_9_10_add_4_9 (.A0(n14), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n13), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .CIN(n138), .COUT(n139), .S0(n103), .S1(n102));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_9.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_9.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_9.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_9.INJECT1_1 = "NO";
+    CCU2D led_timer_9_10_add_4_7 (.A0(n16), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n15), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .CIN(n137), .COUT(n138), .S0(n105), .S1(n104));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_7.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_7.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_7.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_7.INJECT1_1 = "NO";
+    CCU2D led_timer_9_10_add_4_5 (.A0(n18), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n17), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .CIN(n136), .COUT(n137), .S0(n107), .S1(n106));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_5.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_5.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_5.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_5.INJECT1_1 = "NO";
+    CCU2D led_timer_9_10_add_4_3 (.A0(n20), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n19), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .CIN(n135), .COUT(n136), .S0(n109), .S1(n108));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_3.INIT0 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_3.INIT1 = 16'hfaaa;
+    defparam led_timer_9_10_add_4_3.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_3.INJECT1_1 = "NO";
+    FD1S3AX led_timer_9_10__i20 (.D(n90), .CK(clk), .Q(pin_led_c_20)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i20.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i19 (.D(n91), .CK(clk), .Q(n2)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i19.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i18 (.D(n92), .CK(clk), .Q(n3)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i18.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i17 (.D(n93), .CK(clk), .Q(n4)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i17.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i16 (.D(n94), .CK(clk), .Q(n5)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i16.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i15 (.D(n95), .CK(clk), .Q(n6)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i15.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i14 (.D(n96), .CK(clk), .Q(n7)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i14.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i13 (.D(n97), .CK(clk), .Q(n8)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i13.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i12 (.D(n98), .CK(clk), .Q(n9)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i12.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i11 (.D(n99), .CK(clk), .Q(n10)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i11.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i10 (.D(n100), .CK(clk), .Q(n11)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i10.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i9 (.D(n101), .CK(clk), .Q(n12)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i9.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i8 (.D(n102), .CK(clk), .Q(n13)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i8.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i7 (.D(n103), .CK(clk), .Q(n14)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i7.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i6 (.D(n104), .CK(clk), .Q(n15)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i6.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i5 (.D(n105), .CK(clk), .Q(n16)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i5.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i4 (.D(n106), .CK(clk), .Q(n17)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i4.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i3 (.D(n107), .CK(clk), .Q(n18)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i3.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i2 (.D(n108), .CK(clk), .Q(n19)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i2.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i1 (.D(n109), .CK(clk), .Q(n20)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i1.GSR = "ENABLED";
+    FD1S3AX led_timer_9_10__i0 (.D(n110), .CK(clk), .Q(n21)) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10__i0.GSR = "ENABLED";
+    CCU2D led_timer_9_10_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
+          .D0(GND_net), .A1(n21), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
+          .COUT(n135), .S1(n110));   // c:/users/chamberlin/documents/liron/top.v(18[18:31])
+    defparam led_timer_9_10_add_4_1.INIT0 = 16'hF000;
+    defparam led_timer_9_10_add_4_1.INIT1 = 16'h0555;
+    defparam led_timer_9_10_add_4_1.INJECT1_0 = "NO";
+    defparam led_timer_9_10_add_4_1.INJECT1_1 = "NO";
+    
+endmodule
+//
+// Verilog Description of module TSALL
+// module not written out since it is a black-box. 
+//
+
+//
+// Verilog Description of module PUR
+// module not written out since it is a black-box. 
+//
+
diff --git a/yellowstone_blink/hdla_gen_hierarchy.html b/yellowstone_blink/hdla_gen_hierarchy.html
new file mode 100644
index 0000000..160d610
--- /dev/null
+++ b/yellowstone_blink/hdla_gen_hierarchy.html
@@ -0,0 +1,11 @@
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'C:/Users/chamberlin/Documents/Liron/yellowstone_blink/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/top.v
+INFO - C:/Users/chamberlin/Documents/Liron/top.v(1,8-1,13) (VERI-1018) compiling module blink
+INFO - C:/Users/chamberlin/Documents/Liron/top.v(1,1-27,10) (VERI-9000) elaborating module 'blink'
+INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
+WARNING - C:/Users/chamberlin/Documents/Liron/top.v(8,3-13,5) (VERI-1927) port SEDSTDBY remains unconnected for this instance
+Done: design load finished with (0) errors, and (1) warnings
+
+
    
\ No newline at end of file
diff --git a/yellowstone_blink/message.xml b/yellowstone_blink/message.xml
new file mode 100644
index 0000000..6dcb638
--- /dev/null
+++ b/yellowstone_blink/message.xml
@@ -0,0 +1,42 @@
+
+
+    
+        
+            35002000
+            Info
+        
+        
+            35001781
+            Info
+        
+        
+            35901018
+            Info
+            c:/users/chamberlin/documents/liron/top.v(1): 
+            blink
+            c:/users/chamberlin/documents/liron/top.v
+            1
+        
+        
+            35901018
+            Info
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): 
+            OSCH
+            C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+            1793
+        
+        
+            35901209
+            Warning
+            c:/users/chamberlin/documents/liron/top.v(18): 
+            32
+            24
+            c:/users/chamberlin/documents/liron/top.v
+            18
+        
+        
+            35001611
+            Warning
+        
+    
+
\ No newline at end of file
diff --git a/yellowstone_blink/synthesis_lse.html b/yellowstone_blink/synthesis_lse.html
new file mode 100644
index 0000000..da453c7
--- /dev/null
+++ b/yellowstone_blink/synthesis_lse.html
@@ -0,0 +1,225 @@
+
+Synthesis and Ngdbuild Report
+
+
+
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.9.0.99.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Oct 05 12:19:47 2017
+
+
+Command Line:  synthesis -f yellowstone_blink_yellowstone_blink_lattice.synproj -gui 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-1200HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-1200HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = blink.
+Target frequency = 1.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/chamberlin/Documents/Liron (searchpath added)
+-p C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data (searchpath added)
+-p C:/Users/chamberlin/Documents/Liron/yellowstone_blink (searchpath added)
+-p C:/Users/chamberlin/Documents/Liron (searchpath added)
+Verilog design file = C:/Users/chamberlin/Documents/Liron/top.v
+NGD file = yellowstone_blink_yellowstone_blink.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/chamberlin/documents/liron/top.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): blink
+INFO - synthesis: c:/users/chamberlin/documents/liron/top.v(1): compiling module blink. VERI-1018
+INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH. VERI-1018
+WARNING - synthesis: c:/users/chamberlin/documents/liron/top.v(18): expression size 32 truncated to fit in target size 24. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Top-level module name = blink.
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+Applying 1.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in blink_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file yellowstone_blink_yellowstone_blink.ngd.
+
+################### Begin Area Report (blink)######################
+Number of register bits => 21 of 1520 (1 % )
+CCU2D => 11
+FD1S3AX => 21
+GSR => 1
+OB => 2
+OSCH => 1
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 1
+  Net : clk, loads : 21
+Clock Enable Nets
+Number of Clock Enables: 0
+Top 0 highest fanout Clock Enables:
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : pin_led_c_20, loads : 2
+  Net : n21, loads : 1
+  Net : n20, loads : 1
+  Net : n19, loads : 1
+  Net : n18, loads : 1
+  Net : n17, loads : 1
+  Net : n16, loads : 1
+  Net : n15, loads : 1
+  Net : n14, loads : 1
+  Net : n13, loads : 1
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 1000.000000 -name  |             |             |
+clk0 [get_nets clk]                     |    1.000 MHz|  181.028 MHz|    12  
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+Peak Memory Usage: 49.246  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.406  secs
+--------------------------------------------------------------
+
+
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diff --git a/yellowstone_blink/xxx_lse_cp_file_list b/yellowstone_blink/xxx_lse_cp_file_list
new file mode 100644
index 0000000..7fe09d5
--- /dev/null
+++ b/yellowstone_blink/xxx_lse_cp_file_list
@@ -0,0 +1,34 @@
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
+3	 c:/users/chamberlin/documents/liron/top.v
diff --git a/yellowstone_blink/xxx_lse_sign_file b/yellowstone_blink/xxx_lse_sign_file
new file mode 100644
index 0000000..edf21c6
--- /dev/null
+++ b/yellowstone_blink/xxx_lse_sign_file
@@ -0,0 +1,34 @@
+LSE_CPS_ID_1 "c:/users/chamberlin/documents/liron/top.v:2[10:17]"
+LSE_CPS_ID_2 "c:/users/chamberlin/documents/liron/top.v:3[10:16]"
+LSE_CPS_ID_3 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_4 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_5 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_6 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_7 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_8 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_9 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_10 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_11 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_12 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_13 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_14 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_15 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_16 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_17 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_18 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_19 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_20 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_21 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_22 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_23 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_24 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_25 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_26 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_27 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_28 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_29 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_30 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_31 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_32 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_33 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
+LSE_CPS_ID_34 "c:/users/chamberlin/documents/liron/top.v:18[18:31]"
diff --git a/yellowstone_blink/yellowstone_blink.xcf b/yellowstone_blink/yellowstone_blink.xcf
new file mode 100644
index 0000000..f882b54
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink.xcf
@@ -0,0 +1,50 @@
+
+
+
+	
+	
+		JTAG
+		
+			
+			1
+			Lattice
+			MachXO2
+			LCMXO2-1200HC
+			0x012ba043
+			All
+			LCMXO2-1200HC
+			
+				8
+				11111111
+				1
+				0
+			
+			C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink_yellowstone_blink.bit
+			10/05/17 15:40:34
+			SRAM Erase,Program,Verify
+			
+		
+	
+	
+		SEQUENTIAL
+		ENTIRED CHAIN
+		No Override
+		TLR
+		TLR
+		
+		1
+	
+	
+		USB
+		EzUSB-0
+		\\?\usb#vid_1134&amp;pid_8001#5&amp;5cf71e0&amp;0&amp;4#
+	
+
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.alt b/yellowstone_blink/yellowstone_blink_yellowstone_blink.alt
new file mode 100644
index 0000000..ed63a3d
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.alt
@@ -0,0 +1,10 @@
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Thu Oct 05 15:40:34 2017 *
+NOTE DESIGN NAME: blink *
+NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS pin_led : 25 : out *
+NOTE PINS en_245 : 30 : out *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: on *
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.arearep b/yellowstone_blink/yellowstone_blink_yellowstone_blink.arearep
new file mode 100644
index 0000000..9fb4ee2
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.arearep
@@ -0,0 +1,12 @@
+----------------------------------------------------------------------
+Report for cell blink.TECH
+Register bits:  21 of 1520 (1.382%)
+I/O cells:      2
+                                  Cell usage:
+                               cell     count   Res Usage(%)
+                              CCU2D        11          100.0
+                            FD1S3AX        21          100.0
+                                GSR         1          100.0
+                                 OB         2          100.0
+                               OSCH         1          100.0
+                              TOTAL        36
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.bgn b/yellowstone_blink/yellowstone_blink_yellowstone_blink.bgn
new file mode 100644
index 0000000..5260ae7
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.bgn
@@ -0,0 +1,71 @@
+BITGEN: Bitstream Generator Diamond (64-bit) 3.9.0.99.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Command: bitgen -g RamCfg:Reset -path C:/Users/chamberlin/Documents/Liron -w -gui -msgset C:/Users/chamberlin/Documents/Liron/promote.xml yellowstone_blink_yellowstone_blink.ncd yellowstone_blink_yellowstone_blink.prf 
+
+Loading design for application Bitgen from file yellowstone_blink_yellowstone_blink.ncd.
+Design name: blink
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from yellowstone_blink_yellowstone_blink.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.94.
+ 
+Saving bit stream in "yellowstone_blink_yellowstone_blink.bit".
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.bit b/yellowstone_blink/yellowstone_blink_yellowstone_blink.bit
new file mode 100644
index 0000000..33ba27e
Binary files /dev/null and b/yellowstone_blink/yellowstone_blink_yellowstone_blink.bit differ
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.ncd b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.ncd
new file mode 100644
index 0000000..43b869b
Binary files /dev/null and b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.ncd differ
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.pad b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.pad
new file mode 100644
index 0000000..07749a4
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.pad
@@ -0,0 +1,177 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Thu Oct 05 12:20:42 2017
+
+Pinout by Port Name:
++-----------+----------+-------------+-------+-----------+-----------+----------------------+
+| Port Name | Pin/Bank | Buffer Type | Site  | PG Enable | BC Enable | Properties           |
++-----------+----------+-------------+-------+-----------+-----------+----------------------+
+| en_245    | 30/2     | LVTTL33_OUT | PB6B  |           |           | DRIVE:8mA SLEW:SLOW  |
+| pin_led   | 25/3     | LVTTL33_OUT | PL10D |           |           | DRIVE:8mA SLEW:SLOW  |
++-----------+----------+-------------+-------+-----------+-----------+----------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+-------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+-------------+-------+---------------+-----------+-----------+
+| 1/3      |     unused, PULL:DOWN |            |             | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      |     unused, PULL:DOWN |            |             | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      |     unused, PULL:DOWN |            |             | PL3A  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |             | PL3B  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |             | PL3C  |               |           |           |
+| 8/3      |     unused, PULL:DOWN |            |             | PL3D  |               |           |           |
+| 9/3      |     unused, PULL:DOWN |            |             | PL4A  |               |           |           |
+| 10/3     |     unused, PULL:DOWN |            |             | PL4B  |               |           |           |
+| 12/3     |     unused, PULL:DOWN |            |             | PL5A  | PCLKT3_1      |           |           |
+| 13/3     |     unused, PULL:DOWN |            |             | PL5B  | PCLKC3_1      |           |           |
+| 14/3     |     unused, PULL:DOWN |            |             | PL5C  |               |           |           |
+| 15/3     |     unused, PULL:DOWN |            |             | PL5D  |               |           |           |
+| 16/3     |     unused, PULL:DOWN |            |             | PL8A  |               |           |           |
+| 17/3     |     unused, PULL:DOWN |            |             | PL8B  |               |           |           |
+| 18/3     |     unused, PULL:DOWN |            |             | PL8C  |               |           |           |
+| 19/3     |     unused, PULL:DOWN |            |             | PL8D  |               |           |           |
+| 20/3     |     unused, PULL:DOWN |            |             | PL9A  | PCLKT3_0      |           |           |
+| 21/3     |     unused, PULL:DOWN |            |             | PL9B  | PCLKC3_0      |           |           |
+| 24/3     |     unused, PULL:DOWN |            |             | PL10C |               |           |           |
+| 25/3     | pin_led               | LOCATED    | LVTTL33_OUT | PL10D |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |             | PB4C  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |             | PB4D  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |             | PB6A  |               |           |           |
+| 30/2     | en_245                | LOCATED    | LVTTL33_OUT | PB6B  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |             | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     |     unused, PULL:DOWN |            |             | PB6D  | SO/SPISO      |           |           |
+| 34/2     |     unused, PULL:DOWN |            |             | PB9A  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |             | PB9B  | PCLKC2_0      |           |           |
+| 36/2     |     unused, PULL:DOWN |            |             | PB11C |               |           |           |
+| 37/2     |     unused, PULL:DOWN |            |             | PB11D |               |           |           |
+| 38/2     |     unused, PULL:DOWN |            |             | PB11A | PCLKT2_1      |           |           |
+| 39/2     |     unused, PULL:DOWN |            |             | PB11B | PCLKC2_1      |           |           |
+| 40/2     |     unused, PULL:DOWN |            |             | PB15A |               |           |           |
+| 41/2     |     unused, PULL:DOWN |            |             | PB15B |               |           |           |
+| 42/2     |     unused, PULL:DOWN |            |             | PB18A |               |           |           |
+| 43/2     |     unused, PULL:DOWN |            |             | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |             | PB18C |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |             | PB18D |               |           |           |
+| 48/2     |     unused, PULL:DOWN |            |             | PB20C | SN            |           |           |
+| 49/2     |     unused, PULL:DOWN |            |             | PB20D | SI/SISPI      |           |           |
+| 51/1     |     unused, PULL:DOWN |            |             | PR10D | DQ1           |           |           |
+| 52/1     |     unused, PULL:DOWN |            |             | PR10C | DQ1           |           |           |
+| 53/1     |     unused, PULL:DOWN |            |             | PR9D  | DQ1           |           |           |
+| 54/1     |     unused, PULL:DOWN |            |             | PR9C  | DQ1           |           |           |
+| 57/1     |     unused, PULL:DOWN |            |             | PR9B  | DQ1           |           |           |
+| 58/1     |     unused, PULL:DOWN |            |             | PR9A  | DQ1           |           |           |
+| 59/1     |     unused, PULL:DOWN |            |             | PR8D  | DQ1           |           |           |
+| 60/1     |     unused, PULL:DOWN |            |             | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |             | PR8A  | DQS1          |           |           |
+| 62/1     |     unused, PULL:DOWN |            |             | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     |     unused, PULL:DOWN |            |             | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     |     unused, PULL:DOWN |            |             | PR5B  | DQS0N         |           |           |
+| 65/1     |     unused, PULL:DOWN |            |             | PR5A  | DQS0          |           |           |
+| 66/1     |     unused, PULL:DOWN |            |             | PR4D  | DQ0           |           |           |
+| 67/1     |     unused, PULL:DOWN |            |             | PR4C  | DQ0           |           |           |
+| 68/1     |     unused, PULL:DOWN |            |             | PR4B  | DQ0           |           |           |
+| 69/1     |     unused, PULL:DOWN |            |             | PR4A  | DQ0           |           |           |
+| 70/1     |     unused, PULL:DOWN |            |             | PR3B  | DQ0           |           |           |
+| 71/1     |     unused, PULL:DOWN |            |             | PR3A  | DQ0           |           |           |
+| 74/1     |     unused, PULL:DOWN |            |             | PR2B  | DQ0           |           |           |
+| 75/1     |     unused, PULL:DOWN |            |             | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |             | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |             | PT17C | INITN         |           |           |
+| 78/0     |     unused, PULL:DOWN |            |             | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |             | PT15D | PROGRAMN      |           |           |
+| 82/0     |     unused, PULL:DOWN |            |             | PT15C | JTAGENB       |           |           |
+| 83/0     |     unused, PULL:DOWN |            |             | PT15B |               |           |           |
+| 84/0     |     unused, PULL:DOWN |            |             | PT15A |               |           |           |
+| 85/0     |     unused, PULL:DOWN |            |             | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     |     unused, PULL:DOWN |            |             | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     |     unused, PULL:DOWN |            |             | PT12B | PCLKC0_1      |           |           |
+| 88/0     |     unused, PULL:DOWN |            |             | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |             | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |             | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |             | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |             | PT10C | TDO           |           |           |
+| 96/0     |     unused, PULL:DOWN |            |             | PT10B |               |           |           |
+| 97/0     |     unused, PULL:DOWN |            |             | PT10A |               |           |           |
+| 98/0     |     unused, PULL:DOWN |            |             | PT9B  |               |           |           |
+| 99/0     |     unused, PULL:DOWN |            |             | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |             | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |             | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |             | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |             | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |             | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |             | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |             | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |             | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |             | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |             | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |             | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |             | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |             | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |             | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |             | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |             | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |             | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |             | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |             | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |             | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |             | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |             | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |             | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |             | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |             | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |             | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |             | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |             | PT17B |               |           |           |
++----------+-----------------------+------------+-------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "en_245"  SITE  "30";
+LOCATE  COMP  "pin_led"  SITE  "25";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Oct 05 12:20:42 2017
+
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.par b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.par
new file mode 100644
index 0000000..14ee88c
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.par
@@ -0,0 +1,192 @@
+
+Lattice Place and Route Report for Design "yellowstone_blink_yellowstone_blink_map.ncd"
+Thu Oct 05 12:20:38 2017
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF yellowstone_blink_yellowstone_blink_map.ncd yellowstone_blink_yellowstone_blink.dir/5_1.ncd yellowstone_blink_yellowstone_blink.prf
+Preference file: yellowstone_blink_yellowstone_blink.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file yellowstone_blink_yellowstone_blink_map.ncd.
+Design name: blink
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)    2+4(JTAG)/108     6% used
+                   2+4(JTAG)/80      8% bonded
+
+   SLICE             12/640           1% used
+
+   OSC                1/1           100% used
+
+
+Number of Signals: 54
+Number of Connections: 65
+
+Pin Constraint Summary:
+   2 out of 2 pins locked (100% locked).
+
+The following 1 signal is selected to use the primary clock routing resources:
+    clk (driver: internal_oscillator_inst, clk load #: 11)
+
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+................
+Placer score = 492.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  382
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Quadrants All (TL, TR, BL, BR) - Global Clocks:
+  PRIMARY "clk" from OSC on comp "internal_oscillator_inst" on site "OSC", clk load = 11
+
+  PRIMARY  : 1 out of 8 (12%)
+  SECONDARY: 0 out of 8 (0%)
+
+Edge Clocks:
+  No edge clock selected.
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   2 + 4(JTAG) out of 108 (5.6%) PIO sites used.
+   2 + 4(JTAG) out of 80 (7.5%) bonded PIO sites used.
+   Number of PIO comps: 2; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+---------------+------------+-----------+
+| I/O Bank | Usage         | Bank Vccio | Bank Vref |
++----------+---------------+------------+-----------+
+| 0        | 0 / 19 (  0%) | -          | -         |
+| 1        | 0 / 21 (  0%) | -          | -         |
+| 2        | 1 / 20 (  5%) | 3.3V       | -         |
+| 3        | 1 / 20 (  5%) | 3.3V       | -         |
++----------+---------------+------------+-----------+
+
+Total placer CPU time: 4 secs 
+
+Dumping design to file yellowstone_blink_yellowstone_blink.dir/5_1.ncd.
+
+0 connections routed; 65 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 12:20:43 10/05/17
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 12:20:43 10/05/17
+
+Start NBR section for initial routing at 12:20:43 10/05/17
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 476.505ns/0.000ns; real time: 5 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 12:20:43 10/05/17
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 476.505ns/0.000ns; real time: 5 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 12:20:43 10/05/17
+
+Start NBR section for re-routing at 12:20:43 10/05/17
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 476.505ns/0.000ns; real time: 5 secs 
+
+Start NBR section for post-routing at 12:20:43 10/05/17
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 476.505ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 5 secs 
+Total REAL time: 5 secs 
+Completely routed.
+End of route.  65 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file yellowstone_blink_yellowstone_blink.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 476.505
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.377
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 5 secs 
+Total REAL time to completion: 5 secs 
+
+par done!
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1_par.asd b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1_par.asd
new file mode 100644
index 0000000..2936a0c
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1_par.asd
@@ -0,0 +1,29 @@
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 1;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = clk;
+GLOBAL_PRIMARY_0_DRIVERTYPE = OSC;
+GLOBAL_PRIMARY_0_LOADNUM = 11;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 0;
+; I/O Bank 0 Usage
+BANK_0_USED = 0;
+BANK_0_AVAIL = 19;
+BANK_0_VCCIO = NA;
+BANK_0_VREF1 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 0;
+BANK_1_AVAIL = 21;
+BANK_1_VCCIO = NA;
+BANK_1_VREF1 = NA;
+; I/O Bank 2 Usage
+BANK_2_USED = 1;
+BANK_2_AVAIL = 20;
+BANK_2_VCCIO = 3.3V;
+BANK_2_VREF1 = NA;
+; I/O Bank 3 Usage
+BANK_3_USED = 1;
+BANK_3_AVAIL = 20;
+BANK_3_VCCIO = 3.3V;
+BANK_3_VREF1 = NA;
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/yellowstone_blink_yellowstone_blink.par b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/yellowstone_blink_yellowstone_blink.par
new file mode 100644
index 0000000..c308fb0
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/yellowstone_blink_yellowstone_blink.par
@@ -0,0 +1,28 @@
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Oct 05 12:20:38 2017
+
+C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f
+yellowstone_blink_yellowstone_blink.p2t
+yellowstone_blink_yellowstone_blink_map.ncd
+yellowstone_blink_yellowstone_blink.dir yellowstone_blink_yellowstone_blink.prf
+-gui
+
+
+Preference file: yellowstone_blink_yellowstone_blink.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            476.505      0            0.377        0            05           Complete
+
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 5 secs 
+
+par done!
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.drc b/yellowstone_blink/yellowstone_blink_yellowstone_blink.drc
new file mode 100644
index 0000000..ec074a2
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.drc
@@ -0,0 +1 @@
+DRC detected 0 errors and 0 warnings.
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.jed b/yellowstone_blink/yellowstone_blink_yellowstone_blink.jed
new file mode 100644
index 0000000..0157cbd
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.jed
@@ -0,0 +1,2714 @@
+*
+NOTE Diamond (64-bit) 3.9.0.99.2 JEDEC Compatible Fuse File.*
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
+NOTE All Rights Reserved.*
+NOTE DATE CREATED:	Thu Oct 05 12:21:04 2017*
+NOTE DESIGN NAME:	yellowstone_blink_yellowstone_blink.ncd*
+NOTE DEVICE NAME:	LCMXO2-1200HC-4TQFP100*
+NOTE JEDEC FILE STATUS:	Final   Version 1.94*
+NOTE PIN ASSIGNMENTS*
+NOTE PINS pin_led : 25 : out*
+NOTE PINS en_245 : 30 : out*
+QP100*
+QF343936*
+G0*
+F0*
+L000000
+11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000001100010010010010
+10000010011010000000110110110000001111111111110001000110000000000000000000000000101110001110000000000001010011010000000000000000
+00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.lpf b/yellowstone_blink/yellowstone_blink_yellowstone_blink.lpf
new file mode 100644
index 0000000..b9d3a29
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.lpf
@@ -0,0 +1,4 @@
+#BLOCK ASYNCPATHS;
+#BLOCK RESETPATHS;
+
+#FREQUENCY 1.000000 MHz;
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.lsedata b/yellowstone_blink/yellowstone_blink_yellowstone_blink.lsedata
new file mode 100644
index 0000000..16b19e9
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.lsedata
@@ -0,0 +1,367 @@
+
+
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+    
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diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.mrp b/yellowstone_blink/yellowstone_blink_yellowstone_blink.mrp
new file mode 100644
index 0000000..b9518b5
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.mrp
@@ -0,0 +1,204 @@
+
+            Lattice Mapping Report File for Design Module 'blink'
+
+
+Design Information
+------------------
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     yellowstone_blink_yellowstone_blink.ngd -o
+     yellowstone_blink_yellowstone_blink_map.ncd -pr
+     yellowstone_blink_yellowstone_blink.prf -mp
+     yellowstone_blink_yellowstone_blink.mrp -lpf C:/Users/chamberlin/Documents/
+     Liron/yellowstone_blink/yellowstone_blink_yellowstone_blink.lpf -lpf
+     C:/Users/chamberlin/Documents/Liron/yellowstone_blink.lpf -c 0 -gui 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.9.0.99.2
+Mapped on:  10/05/17  12:20:37
+
+Design Summary
+--------------
+
+   Number of registers:     21 out of  1520 (1%)
+      PFU registers:           21 out of  1280 (2%)
+      PIO registers:            0 out of   240 (0%)
+   Number of SLICEs:        12 out of   640 (2%)
+      SLICEs as Logic/ROM:     12 out of   640 (2%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:         11 out of   640 (2%)
+   Number of LUT4s:         23 out of  1280 (2%)
+      Number used as logic LUTs:          1
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       22
+      Number used as shift registers:     0
+   Number of PIO sites used: 2 + 4(JTAG) out of 80 (8%)
+   Number of block RAMs:  0 out of 7 (0%)
+   Number of GSRs:  0 out of 1 (0%)
+   EFB used :       No
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  Yes
+   Startup used :   No
+   POR :            On
+   Bandgap :        On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Number of PLLs:  0 out of 1 (0%)
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  1
+     Net clk: 11 loads, 11 rising, 0 falling (Driver: internal_oscillator_inst )
+
+                                    Page 1
+
+
+
+
+Design:  blink                                         Date:  10/05/17  12:20:37
+
+Design Summary (cont)
+---------------------
+     
+   Number of Clock Enables:  0
+   Number of LSRs:  0
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net pin_led_c_20: 2 loads
+     Net n143: 1 loads
+     Net n144: 1 loads
+     Net n2: 1 loads
+     Net n3: 1 loads
+     Net n4: 1 loads
+     Net n90: 1 loads
+     Net n91: 1 loads
+     Net n93: 1 loads
+     Net VCC_net: 1 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+   No errors or warnings present.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| pin_led             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| en_245              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+Removed logic
+-------------
+
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal GND_net undriven or does not drive anything - clipped.
+Signal led_timer_9_10_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal led_timer_9_10_add_4_1/CI undriven or does not drive anything - clipped.
+Signal led_timer_9_10_add_4_21/CO undriven or does not drive anything - clipped.
+     
+Block i1 was optimized away.
+
+Memory Usage
+------------
+
+
+     
+
+                                    Page 2
+
+
+
+
+Design:  blink                                         Date:  10/05/17  12:20:37
+
+
+OSC Summary
+-----------
+
+OSC 1:                                     Pin/Node Value
+  OSC Instance Name:                                internal_oscillator_inst
+  OSC Type:                                         OSCH
+  STDBY Input:                                      NONE
+  OSC Output:                              NODE     clk
+  OSC Nominal Frequency (MHz):                      2.08
+
+ASIC Components
+---------------
+
+Instance Name: internal_oscillator_inst
+         Type: OSCH
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 36 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                    Page 3
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights
+     reserved.
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.ncd b/yellowstone_blink/yellowstone_blink_yellowstone_blink.ncd
new file mode 100644
index 0000000..43b869b
Binary files /dev/null and b/yellowstone_blink/yellowstone_blink_yellowstone_blink.ncd differ
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.ngd b/yellowstone_blink/yellowstone_blink_yellowstone_blink.ngd
new file mode 100644
index 0000000..c9f4285
Binary files /dev/null and b/yellowstone_blink/yellowstone_blink_yellowstone_blink.ngd differ
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.p2t b/yellowstone_blink/yellowstone_blink_yellowstone_blink.p2t
new file mode 100644
index 0000000..945b9db
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.p2t
@@ -0,0 +1,9 @@
+-w
+-l 5
+-i 6
+-n 1
+-t 1
+-s 1
+-c 0
+-e 0
+-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.p3t b/yellowstone_blink/yellowstone_blink_yellowstone_blink.p3t
new file mode 100644
index 0000000..34f2a91
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.p3t
@@ -0,0 +1,5 @@
+-rem
+-distrce
+-log "yellowstone_blink_yellowstone_blink.log"
+-o "yellowstone_blink_yellowstone_blink.csv"
+-pr "yellowstone_blink_yellowstone_blink.prf"
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.pad b/yellowstone_blink/yellowstone_blink_yellowstone_blink.pad
new file mode 100644
index 0000000..07749a4
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.pad
@@ -0,0 +1,177 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Thu Oct 05 12:20:42 2017
+
+Pinout by Port Name:
++-----------+----------+-------------+-------+-----------+-----------+----------------------+
+| Port Name | Pin/Bank | Buffer Type | Site  | PG Enable | BC Enable | Properties           |
++-----------+----------+-------------+-------+-----------+-----------+----------------------+
+| en_245    | 30/2     | LVTTL33_OUT | PB6B  |           |           | DRIVE:8mA SLEW:SLOW  |
+| pin_led   | 25/3     | LVTTL33_OUT | PL10D |           |           | DRIVE:8mA SLEW:SLOW  |
++-----------+----------+-------------+-------+-----------+-----------+----------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+-------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+-------------+-------+---------------+-----------+-----------+
+| 1/3      |     unused, PULL:DOWN |            |             | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      |     unused, PULL:DOWN |            |             | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      |     unused, PULL:DOWN |            |             | PL3A  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |             | PL3B  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |             | PL3C  |               |           |           |
+| 8/3      |     unused, PULL:DOWN |            |             | PL3D  |               |           |           |
+| 9/3      |     unused, PULL:DOWN |            |             | PL4A  |               |           |           |
+| 10/3     |     unused, PULL:DOWN |            |             | PL4B  |               |           |           |
+| 12/3     |     unused, PULL:DOWN |            |             | PL5A  | PCLKT3_1      |           |           |
+| 13/3     |     unused, PULL:DOWN |            |             | PL5B  | PCLKC3_1      |           |           |
+| 14/3     |     unused, PULL:DOWN |            |             | PL5C  |               |           |           |
+| 15/3     |     unused, PULL:DOWN |            |             | PL5D  |               |           |           |
+| 16/3     |     unused, PULL:DOWN |            |             | PL8A  |               |           |           |
+| 17/3     |     unused, PULL:DOWN |            |             | PL8B  |               |           |           |
+| 18/3     |     unused, PULL:DOWN |            |             | PL8C  |               |           |           |
+| 19/3     |     unused, PULL:DOWN |            |             | PL8D  |               |           |           |
+| 20/3     |     unused, PULL:DOWN |            |             | PL9A  | PCLKT3_0      |           |           |
+| 21/3     |     unused, PULL:DOWN |            |             | PL9B  | PCLKC3_0      |           |           |
+| 24/3     |     unused, PULL:DOWN |            |             | PL10C |               |           |           |
+| 25/3     | pin_led               | LOCATED    | LVTTL33_OUT | PL10D |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |             | PB4C  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |             | PB4D  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |             | PB6A  |               |           |           |
+| 30/2     | en_245                | LOCATED    | LVTTL33_OUT | PB6B  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |             | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     |     unused, PULL:DOWN |            |             | PB6D  | SO/SPISO      |           |           |
+| 34/2     |     unused, PULL:DOWN |            |             | PB9A  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |             | PB9B  | PCLKC2_0      |           |           |
+| 36/2     |     unused, PULL:DOWN |            |             | PB11C |               |           |           |
+| 37/2     |     unused, PULL:DOWN |            |             | PB11D |               |           |           |
+| 38/2     |     unused, PULL:DOWN |            |             | PB11A | PCLKT2_1      |           |           |
+| 39/2     |     unused, PULL:DOWN |            |             | PB11B | PCLKC2_1      |           |           |
+| 40/2     |     unused, PULL:DOWN |            |             | PB15A |               |           |           |
+| 41/2     |     unused, PULL:DOWN |            |             | PB15B |               |           |           |
+| 42/2     |     unused, PULL:DOWN |            |             | PB18A |               |           |           |
+| 43/2     |     unused, PULL:DOWN |            |             | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |             | PB18C |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |             | PB18D |               |           |           |
+| 48/2     |     unused, PULL:DOWN |            |             | PB20C | SN            |           |           |
+| 49/2     |     unused, PULL:DOWN |            |             | PB20D | SI/SISPI      |           |           |
+| 51/1     |     unused, PULL:DOWN |            |             | PR10D | DQ1           |           |           |
+| 52/1     |     unused, PULL:DOWN |            |             | PR10C | DQ1           |           |           |
+| 53/1     |     unused, PULL:DOWN |            |             | PR9D  | DQ1           |           |           |
+| 54/1     |     unused, PULL:DOWN |            |             | PR9C  | DQ1           |           |           |
+| 57/1     |     unused, PULL:DOWN |            |             | PR9B  | DQ1           |           |           |
+| 58/1     |     unused, PULL:DOWN |            |             | PR9A  | DQ1           |           |           |
+| 59/1     |     unused, PULL:DOWN |            |             | PR8D  | DQ1           |           |           |
+| 60/1     |     unused, PULL:DOWN |            |             | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |             | PR8A  | DQS1          |           |           |
+| 62/1     |     unused, PULL:DOWN |            |             | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     |     unused, PULL:DOWN |            |             | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     |     unused, PULL:DOWN |            |             | PR5B  | DQS0N         |           |           |
+| 65/1     |     unused, PULL:DOWN |            |             | PR5A  | DQS0          |           |           |
+| 66/1     |     unused, PULL:DOWN |            |             | PR4D  | DQ0           |           |           |
+| 67/1     |     unused, PULL:DOWN |            |             | PR4C  | DQ0           |           |           |
+| 68/1     |     unused, PULL:DOWN |            |             | PR4B  | DQ0           |           |           |
+| 69/1     |     unused, PULL:DOWN |            |             | PR4A  | DQ0           |           |           |
+| 70/1     |     unused, PULL:DOWN |            |             | PR3B  | DQ0           |           |           |
+| 71/1     |     unused, PULL:DOWN |            |             | PR3A  | DQ0           |           |           |
+| 74/1     |     unused, PULL:DOWN |            |             | PR2B  | DQ0           |           |           |
+| 75/1     |     unused, PULL:DOWN |            |             | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |             | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |             | PT17C | INITN         |           |           |
+| 78/0     |     unused, PULL:DOWN |            |             | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |             | PT15D | PROGRAMN      |           |           |
+| 82/0     |     unused, PULL:DOWN |            |             | PT15C | JTAGENB       |           |           |
+| 83/0     |     unused, PULL:DOWN |            |             | PT15B |               |           |           |
+| 84/0     |     unused, PULL:DOWN |            |             | PT15A |               |           |           |
+| 85/0     |     unused, PULL:DOWN |            |             | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     |     unused, PULL:DOWN |            |             | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     |     unused, PULL:DOWN |            |             | PT12B | PCLKC0_1      |           |           |
+| 88/0     |     unused, PULL:DOWN |            |             | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |             | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |             | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |             | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |             | PT10C | TDO           |           |           |
+| 96/0     |     unused, PULL:DOWN |            |             | PT10B |               |           |           |
+| 97/0     |     unused, PULL:DOWN |            |             | PT10A |               |           |           |
+| 98/0     |     unused, PULL:DOWN |            |             | PT9B  |               |           |           |
+| 99/0     |     unused, PULL:DOWN |            |             | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |             | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |             | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |             | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |             | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |             | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |             | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |             | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |             | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |             | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |             | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |             | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |             | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |             | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |             | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |             | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |             | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |             | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |             | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |             | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |             | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |             | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |             | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |             | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |             | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |             | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |             | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |             | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |             | PT17B |               |           |           |
++----------+-----------------------+------------+-------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "en_245"  SITE  "30";
+LOCATE  COMP  "pin_led"  SITE  "25";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Oct 05 12:20:42 2017
+
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.par b/yellowstone_blink/yellowstone_blink_yellowstone_blink.par
new file mode 100644
index 0000000..6beee04
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.par
@@ -0,0 +1,220 @@
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Oct 05 12:20:38 2017
+
+C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f
+yellowstone_blink_yellowstone_blink.p2t
+yellowstone_blink_yellowstone_blink_map.ncd
+yellowstone_blink_yellowstone_blink.dir yellowstone_blink_yellowstone_blink.prf
+-gui
+
+
+Preference file: yellowstone_blink_yellowstone_blink.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            476.505      0            0.377        0            05           Complete
+
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 5 secs 
+
+par done!
+
+Lattice Place and Route Report for Design "yellowstone_blink_yellowstone_blink_map.ncd"
+Thu Oct 05 12:20:38 2017
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF yellowstone_blink_yellowstone_blink_map.ncd yellowstone_blink_yellowstone_blink.dir/5_1.ncd yellowstone_blink_yellowstone_blink.prf
+Preference file: yellowstone_blink_yellowstone_blink.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file yellowstone_blink_yellowstone_blink_map.ncd.
+Design name: blink
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)    2+4(JTAG)/108     6% used
+                   2+4(JTAG)/80      8% bonded
+
+   SLICE             12/640           1% used
+
+   OSC                1/1           100% used
+
+
+Number of Signals: 54
+Number of Connections: 65
+
+Pin Constraint Summary:
+   2 out of 2 pins locked (100% locked).
+
+The following 1 signal is selected to use the primary clock routing resources:
+    clk (driver: internal_oscillator_inst, clk load #: 11)
+
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+................
+Placer score = 492.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  382
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Quadrants All (TL, TR, BL, BR) - Global Clocks:
+  PRIMARY "clk" from OSC on comp "internal_oscillator_inst" on site "OSC", clk load = 11
+
+  PRIMARY  : 1 out of 8 (12%)
+  SECONDARY: 0 out of 8 (0%)
+
+Edge Clocks:
+  No edge clock selected.
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   2 + 4(JTAG) out of 108 (5.6%) PIO sites used.
+   2 + 4(JTAG) out of 80 (7.5%) bonded PIO sites used.
+   Number of PIO comps: 2; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+---------------+------------+-----------+
+| I/O Bank | Usage         | Bank Vccio | Bank Vref |
++----------+---------------+------------+-----------+
+| 0        | 0 / 19 (  0%) | -          | -         |
+| 1        | 0 / 21 (  0%) | -          | -         |
+| 2        | 1 / 20 (  5%) | 3.3V       | -         |
+| 3        | 1 / 20 (  5%) | 3.3V       | -         |
++----------+---------------+------------+-----------+
+
+Total placer CPU time: 4 secs 
+
+Dumping design to file yellowstone_blink_yellowstone_blink.dir/5_1.ncd.
+
+0 connections routed; 65 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 12:20:43 10/05/17
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 12:20:43 10/05/17
+
+Start NBR section for initial routing at 12:20:43 10/05/17
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 476.505ns/0.000ns; real time: 5 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 12:20:43 10/05/17
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 476.505ns/0.000ns; real time: 5 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 12:20:43 10/05/17
+
+Start NBR section for re-routing at 12:20:43 10/05/17
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 476.505ns/0.000ns; real time: 5 secs 
+
+Start NBR section for post-routing at 12:20:43 10/05/17
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 476.505ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 5 secs 
+Total REAL time: 5 secs 
+Completely routed.
+End of route.  65 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file yellowstone_blink_yellowstone_blink.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 476.505
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.377
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 5 secs 
+Total REAL time to completion: 5 secs 
+
+par done!
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.prf b/yellowstone_blink/yellowstone_blink_yellowstone_blink.prf
new file mode 100644
index 0000000..5810c1e
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.prf
@@ -0,0 +1,11 @@
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.9.0.99.2 -- WARNING: Map write only section -- Thu Oct 05 12:20:37 2017
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "pin_led" SITE "25" ;
+LOCATE COMP "en_245" SITE "30" ;
+FREQUENCY NET "clk" 2.080000 MHz ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+COMMERCIAL ;
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.pt b/yellowstone_blink/yellowstone_blink_yellowstone_blink.pt
new file mode 100644
index 0000000..e5e32de
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.pt
@@ -0,0 +1,10 @@
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 4
+-sphld m
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink.t2b b/yellowstone_blink/yellowstone_blink_yellowstone_blink.t2b
new file mode 100644
index 0000000..54feeaf
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink.t2b
@@ -0,0 +1,5 @@
+
+
+-g RamCfg:Reset
+
+-path "C:/Users/chamberlin/Documents/Liron"  
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_bgn.html b/yellowstone_blink/yellowstone_blink_yellowstone_blink_bgn.html
new file mode 100644
index 0000000..d9503a5
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink_bgn.html
@@ -0,0 +1,137 @@
+
+Bitgen Report
+
+
+
    BITGEN: Bitstream Generator Diamond (64-bit) 3.9.0.99.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+Command: bitgen -g RamCfg:Reset -path C:/Users/chamberlin/Documents/Liron -w -gui -msgset C:/Users/chamberlin/Documents/Liron/promote.xml yellowstone_blink_yellowstone_blink.ncd yellowstone_blink_yellowstone_blink.prf 
+
+Loading design for application Bitgen from file yellowstone_blink_yellowstone_blink.ncd.
+Design name: blink
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from yellowstone_blink_yellowstone_blink.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.94.
+ 
+Saving bit stream in "yellowstone_blink_yellowstone_blink.bit".
+
+
+
+
    
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+
+
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_lattice.synproj b/yellowstone_blink/yellowstone_blink_yellowstone_blink_lattice.synproj
new file mode 100644
index 0000000..688da7b
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink_lattice.synproj
@@ -0,0 +1,41 @@
+-a "MachXO2"
+-d LCMXO2-1200HC
+-t TQFP100
+-s 4
+
+-optimization_goal Balanced
+-bram_utilization 100
+-ramstyle Auto
+-romstyle auto
+-dsp_utilization 100
+-use_dsp 1
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr Auto
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-loop_limit 1950
+
+
+
+-use_io_insertion 1
+-resolve_mixed_drivers 0
+-use_io_reg auto
+
+
+-lpf 1
+-p "C:/Users/chamberlin/Documents/Liron"
+-ver "C:/Users/chamberlin/Documents/Liron/top.v"
+-top blink
+
+
+-p "C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data" "C:/Users/chamberlin/Documents/Liron/yellowstone_blink" "C:/Users/chamberlin/Documents/Liron"
+
+-ngd "yellowstone_blink_yellowstone_blink.ngd"
+
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.asd b/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.asd
new file mode 100644
index 0000000..39561a0
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.asd
@@ -0,0 +1,13 @@
+[ActiveSupport MAP]
+Device = LCMXO2-1200HC;
+Package = TQFP100;
+Performance = 4;
+LUTS_avail = 1280;
+LUTS_used = 23;
+FF_avail = 1360;
+FF_used = 21;
+OUTPUT_LVTTL33 = 2;
+IO_avail = 80;
+IO_used = 2;
+EBR_avail = 7;
+EBR_used = 0;
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.cam b/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.cam
new file mode 100644
index 0000000..d9e316b
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.cam
@@ -0,0 +1,21 @@
+[ START MERGED ]
+[ END MERGED ]
+[ START CLIPPED ]
+GND_net
+led_timer_9_10_add_4_1/S0
+led_timer_9_10_add_4_1/CI
+led_timer_9_10_add_4_21/CO
+[ END CLIPPED ]
+[ START OSC ]
+clk 2.08
+[ END OSC ]
+[ START DESIGN PREFS ]
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.9.0.99.2 -- WARNING: Map write only section -- Thu Oct 05 12:20:37 2017
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "pin_led" SITE "25" ;
+LOCATE COMP "en_245" SITE "30" ;
+FREQUENCY NET "clk" 2.080000 MHz ;
+SCHEMATIC END ;
+[ END DESIGN PREFS ]
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.hrr b/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.hrr
new file mode 100644
index 0000000..b676cf1
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.hrr
@@ -0,0 +1,10 @@
+---------------------------------------------------
+Report for cell blink
+   Instance path: blink
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      12.00        100.0
+                                  LUT4	       1.00        100.0
+                                 IOBUF	          2        100.0
+                                PFUREG	         21        100.0
+                                RIPPLE	         11        100.0
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.ncd b/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.ncd
new file mode 100644
index 0000000..1d5f9e3
Binary files /dev/null and b/yellowstone_blink/yellowstone_blink_yellowstone_blink_map.ncd differ
diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_mrp.html b/yellowstone_blink/yellowstone_blink_yellowstone_blink_mrp.html
new file mode 100644
index 0000000..a89d174
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink_mrp.html
@@ -0,0 +1,259 @@
+
+Project Summary
+
+
+
    
+            Lattice Mapping Report File for Design Module 'blink'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     yellowstone_blink_yellowstone_blink.ngd -o
+     yellowstone_blink_yellowstone_blink_map.ncd -pr
+     yellowstone_blink_yellowstone_blink.prf -mp
+     yellowstone_blink_yellowstone_blink.mrp -lpf C:/Users/chamberlin/Documents/
+     Liron/yellowstone_blink/yellowstone_blink_yellowstone_blink.lpf -lpf
+     C:/Users/chamberlin/Documents/Liron/yellowstone_blink.lpf -c 0 -gui 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.9.0.99.2
+Mapped on:  10/05/17  12:20:37
+
+
+Design Summary
+   Number of registers:     21 out of  1520 (1%)
+      PFU registers:           21 out of  1280 (2%)
+      PIO registers:            0 out of   240 (0%)
+   Number of SLICEs:        12 out of   640 (2%)
+      SLICEs as Logic/ROM:     12 out of   640 (2%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:         11 out of   640 (2%)
+   Number of LUT4s:         23 out of  1280 (2%)
+      Number used as logic LUTs:          1
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       22
+      Number used as shift registers:     0
+   Number of PIO sites used: 2 + 4(JTAG) out of 80 (8%)
+   Number of block RAMs:  0 out of 7 (0%)
+   Number of GSRs:  0 out of 1 (0%)
+   EFB used :       No
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  Yes
+   Startup used :   No
+   POR :            On
+   Bandgap :        On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Number of PLLs:  0 out of 1 (0%)
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  1
+     Net clk: 11 loads, 11 rising, 0 falling (Driver: internal_oscillator_inst )
+
+     
+   Number of Clock Enables:  0
+   Number of LSRs:  0
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net pin_led_c_20: 2 loads
+     Net n143: 1 loads
+     Net n144: 1 loads
+     Net n2: 1 loads
+     Net n3: 1 loads
+     Net n4: 1 loads
+     Net n90: 1 loads
+     Net n91: 1 loads
+     Net n93: 1 loads
+     Net VCC_net: 1 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| pin_led             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| en_245              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal GND_net undriven or does not drive anything - clipped.
+Signal led_timer_9_10_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal led_timer_9_10_add_4_1/CI undriven or does not drive anything - clipped.
+Signal led_timer_9_10_add_4_21/CO undriven or does not drive anything - clipped.
+     
+Block i1 was optimized away.
+
+
+
+Memory Usage
+
+
+     
+
+
+OSC Summary
+-----------
+
+OSC 1:                                     Pin/Node Value
+  OSC Instance Name:                                internal_oscillator_inst
+  OSC Type:                                         OSCH
+  STDBY Input:                                      NONE
+  OSC Output:                              NODE     clk
+  OSC Nominal Frequency (MHz):                      2.08
+
+
+
+ASIC Components
+---------------
+
+Instance Name: internal_oscillator_inst
+         Type: OSCH
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 36 MB
+        
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
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diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_pad.html b/yellowstone_blink/yellowstone_blink_yellowstone_blink_pad.html
new file mode 100644
index 0000000..f5d5ed7
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink_pad.html
@@ -0,0 +1,242 @@
+
+PAD Specification File
+
+
+
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Thu Oct 05 12:20:42 2017
+
+Pinout by Port Name:
++-----------+----------+-------------+-------+-----------+-----------+----------------------+
+| Port Name | Pin/Bank | Buffer Type | Site  | PG Enable | BC Enable | Properties           |
++-----------+----------+-------------+-------+-----------+-----------+----------------------+
+| en_245    | 30/2     | LVTTL33_OUT | PB6B  |           |           | DRIVE:8mA SLEW:SLOW  |
+| pin_led   | 25/3     | LVTTL33_OUT | PL10D |           |           | DRIVE:8mA SLEW:SLOW  |
++-----------+----------+-------------+-------+-----------+-----------+----------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+-------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+-------------+-------+---------------+-----------+-----------+
+| 1/3      |     unused, PULL:DOWN |            |             | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      |     unused, PULL:DOWN |            |             | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      |     unused, PULL:DOWN |            |             | PL3A  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |             | PL3B  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |             | PL3C  |               |           |           |
+| 8/3      |     unused, PULL:DOWN |            |             | PL3D  |               |           |           |
+| 9/3      |     unused, PULL:DOWN |            |             | PL4A  |               |           |           |
+| 10/3     |     unused, PULL:DOWN |            |             | PL4B  |               |           |           |
+| 12/3     |     unused, PULL:DOWN |            |             | PL5A  | PCLKT3_1      |           |           |
+| 13/3     |     unused, PULL:DOWN |            |             | PL5B  | PCLKC3_1      |           |           |
+| 14/3     |     unused, PULL:DOWN |            |             | PL5C  |               |           |           |
+| 15/3     |     unused, PULL:DOWN |            |             | PL5D  |               |           |           |
+| 16/3     |     unused, PULL:DOWN |            |             | PL8A  |               |           |           |
+| 17/3     |     unused, PULL:DOWN |            |             | PL8B  |               |           |           |
+| 18/3     |     unused, PULL:DOWN |            |             | PL8C  |               |           |           |
+| 19/3     |     unused, PULL:DOWN |            |             | PL8D  |               |           |           |
+| 20/3     |     unused, PULL:DOWN |            |             | PL9A  | PCLKT3_0      |           |           |
+| 21/3     |     unused, PULL:DOWN |            |             | PL9B  | PCLKC3_0      |           |           |
+| 24/3     |     unused, PULL:DOWN |            |             | PL10C |               |           |           |
+| 25/3     | pin_led               | LOCATED    | LVTTL33_OUT | PL10D |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |             | PB4C  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |             | PB4D  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |             | PB6A  |               |           |           |
+| 30/2     | en_245                | LOCATED    | LVTTL33_OUT | PB6B  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |             | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     |     unused, PULL:DOWN |            |             | PB6D  | SO/SPISO      |           |           |
+| 34/2     |     unused, PULL:DOWN |            |             | PB9A  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |             | PB9B  | PCLKC2_0      |           |           |
+| 36/2     |     unused, PULL:DOWN |            |             | PB11C |               |           |           |
+| 37/2     |     unused, PULL:DOWN |            |             | PB11D |               |           |           |
+| 38/2     |     unused, PULL:DOWN |            |             | PB11A | PCLKT2_1      |           |           |
+| 39/2     |     unused, PULL:DOWN |            |             | PB11B | PCLKC2_1      |           |           |
+| 40/2     |     unused, PULL:DOWN |            |             | PB15A |               |           |           |
+| 41/2     |     unused, PULL:DOWN |            |             | PB15B |               |           |           |
+| 42/2     |     unused, PULL:DOWN |            |             | PB18A |               |           |           |
+| 43/2     |     unused, PULL:DOWN |            |             | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |             | PB18C |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |             | PB18D |               |           |           |
+| 48/2     |     unused, PULL:DOWN |            |             | PB20C | SN            |           |           |
+| 49/2     |     unused, PULL:DOWN |            |             | PB20D | SI/SISPI      |           |           |
+| 51/1     |     unused, PULL:DOWN |            |             | PR10D | DQ1           |           |           |
+| 52/1     |     unused, PULL:DOWN |            |             | PR10C | DQ1           |           |           |
+| 53/1     |     unused, PULL:DOWN |            |             | PR9D  | DQ1           |           |           |
+| 54/1     |     unused, PULL:DOWN |            |             | PR9C  | DQ1           |           |           |
+| 57/1     |     unused, PULL:DOWN |            |             | PR9B  | DQ1           |           |           |
+| 58/1     |     unused, PULL:DOWN |            |             | PR9A  | DQ1           |           |           |
+| 59/1     |     unused, PULL:DOWN |            |             | PR8D  | DQ1           |           |           |
+| 60/1     |     unused, PULL:DOWN |            |             | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |             | PR8A  | DQS1          |           |           |
+| 62/1     |     unused, PULL:DOWN |            |             | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     |     unused, PULL:DOWN |            |             | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     |     unused, PULL:DOWN |            |             | PR5B  | DQS0N         |           |           |
+| 65/1     |     unused, PULL:DOWN |            |             | PR5A  | DQS0          |           |           |
+| 66/1     |     unused, PULL:DOWN |            |             | PR4D  | DQ0           |           |           |
+| 67/1     |     unused, PULL:DOWN |            |             | PR4C  | DQ0           |           |           |
+| 68/1     |     unused, PULL:DOWN |            |             | PR4B  | DQ0           |           |           |
+| 69/1     |     unused, PULL:DOWN |            |             | PR4A  | DQ0           |           |           |
+| 70/1     |     unused, PULL:DOWN |            |             | PR3B  | DQ0           |           |           |
+| 71/1     |     unused, PULL:DOWN |            |             | PR3A  | DQ0           |           |           |
+| 74/1     |     unused, PULL:DOWN |            |             | PR2B  | DQ0           |           |           |
+| 75/1     |     unused, PULL:DOWN |            |             | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |             | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |             | PT17C | INITN         |           |           |
+| 78/0     |     unused, PULL:DOWN |            |             | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |             | PT15D | PROGRAMN      |           |           |
+| 82/0     |     unused, PULL:DOWN |            |             | PT15C | JTAGENB       |           |           |
+| 83/0     |     unused, PULL:DOWN |            |             | PT15B |               |           |           |
+| 84/0     |     unused, PULL:DOWN |            |             | PT15A |               |           |           |
+| 85/0     |     unused, PULL:DOWN |            |             | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     |     unused, PULL:DOWN |            |             | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     |     unused, PULL:DOWN |            |             | PT12B | PCLKC0_1      |           |           |
+| 88/0     |     unused, PULL:DOWN |            |             | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |             | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |             | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |             | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |             | PT10C | TDO           |           |           |
+| 96/0     |     unused, PULL:DOWN |            |             | PT10B |               |           |           |
+| 97/0     |     unused, PULL:DOWN |            |             | PT10A |               |           |           |
+| 98/0     |     unused, PULL:DOWN |            |             | PT9B  |               |           |           |
+| 99/0     |     unused, PULL:DOWN |            |             | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |             | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |             | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |             | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |             | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |             | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |             | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |             | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |             | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |             | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |             | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |             | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |             | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |             | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |             | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |             | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |             | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |             | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |             | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |             | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |             | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |             | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |             | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |             | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |             | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |             | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |             | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |             | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |             | PT17B |               |           |           |
++----------+-----------------------+------------+-------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "en_245"  SITE  "30";
+LOCATE  COMP  "pin_led"  SITE  "25";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Oct 05 12:20:42 2017
+
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diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_par.html b/yellowstone_blink/yellowstone_blink_yellowstone_blink_par.html
new file mode 100644
index 0000000..d6a7dea
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink_par.html
@@ -0,0 +1,289 @@
+
+Place & Route Report
+
+
+
    PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Oct 05 12:20:38 2017
+
+C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f
+yellowstone_blink_yellowstone_blink.p2t
+yellowstone_blink_yellowstone_blink_map.ncd
+yellowstone_blink_yellowstone_blink.dir yellowstone_blink_yellowstone_blink.prf
+-gui
+
+
+Preference file: yellowstone_blink_yellowstone_blink.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            476.505      0            0.377        0            05           Complete
+
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 5 secs 
+
+par done!
+
+Lattice Place and Route Report for Design "yellowstone_blink_yellowstone_blink_map.ncd"
+Thu Oct 05 12:20:38 2017
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF yellowstone_blink_yellowstone_blink_map.ncd yellowstone_blink_yellowstone_blink.dir/5_1.ncd yellowstone_blink_yellowstone_blink.prf
+Preference file: yellowstone_blink_yellowstone_blink.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file yellowstone_blink_yellowstone_blink_map.ncd.
+Design name: blink
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)    2+4(JTAG)/108     6% used
+                   2+4(JTAG)/80      8% bonded
+
+   SLICE             12/640           1% used
+
+   OSC                1/1           100% used
+
+
+Number of Signals: 54
+Number of Connections: 65
+
+Pin Constraint Summary:
+   2 out of 2 pins locked (100% locked).
+
+The following 1 signal is selected to use the primary clock routing resources:
+    clk (driver: internal_oscillator_inst, clk load #: 11)
+
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+................
+Placer score = 492.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  382
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Quadrants All (TL, TR, BL, BR) - Global Clocks:
+  PRIMARY "clk" from OSC on comp "internal_oscillator_inst" on site "OSC", clk load = 11
+
+  PRIMARY  : 1 out of 8 (12%)
+  SECONDARY: 0 out of 8 (0%)
+
+Edge Clocks:
+  No edge clock selected.
+
+
+
+
+I/O Usage Summary (final):
+   2 + 4(JTAG) out of 108 (5.6%) PIO sites used.
+   2 + 4(JTAG) out of 80 (7.5%) bonded PIO sites used.
+   Number of PIO comps: 2; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+---------------+------------+-----------+
+| I/O Bank | Usage         | Bank Vccio | Bank Vref |
++----------+---------------+------------+-----------+
+| 0        | 0 / 19 (  0%) | -          | -         |
+| 1        | 0 / 21 (  0%) | -          | -         |
+| 2        | 1 / 20 (  5%) | 3.3V       | -         |
+| 3        | 1 / 20 (  5%) | 3.3V       | -         |
++----------+---------------+------------+-----------+
+
+Total placer CPU time: 4 secs 
+
+Dumping design to file yellowstone_blink_yellowstone_blink.dir/5_1.ncd.
+
+0 connections routed; 65 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 12:20:43 10/05/17
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 12:20:43 10/05/17
+
+Start NBR section for initial routing at 12:20:43 10/05/17
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 476.505ns/0.000ns; real time: 5 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 12:20:43 10/05/17
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 476.505ns/0.000ns; real time: 5 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 12:20:43 10/05/17
+
+Start NBR section for re-routing at 12:20:43 10/05/17
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 476.505ns/0.000ns; real time: 5 secs 
+
+Start NBR section for post-routing at 12:20:43 10/05/17
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 476.505ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 5 secs 
+Total REAL time: 5 secs 
+Completely routed.
+End of route.  65 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file yellowstone_blink_yellowstone_blink.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 476.505
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.377
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 5 secs 
+Total REAL time to completion: 5 secs 
+
+par done!
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
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diff --git a/yellowstone_blink/yellowstone_blink_yellowstone_blink_summary.html b/yellowstone_blink/yellowstone_blink_yellowstone_blink_summary.html
new file mode 100644
index 0000000..5e8f962
--- /dev/null
+++ b/yellowstone_blink/yellowstone_blink_yellowstone_blink_summary.html
@@ -0,0 +1,83 @@
+
+Project Summary
+
+
+
    
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+
    yellowstone_blink project summary
    Module Name:yellowstone_blinkSynthesis:Lattice LSE
    Implementation Name:yellowstone_blinkStrategy Name:Strategy1
    Last Process:State:
    Target Device:LCMXO2-1200HC-4TG100CDevice Family:MachXO2
    Device Type:LCMXO2-1200HCPackage Type:TQFP100
    Performance grade:4Operating conditions:COM
    Logic preference file:yellowstone_blink.lpf
    Physical Preference file:yellowstone_blink/yellowstone_blink_yellowstone_blink.prf
    Product Version:3.9.0.99.2Patch Version:
    Updated:2018/02/14 12:33:53
    Implementation Location:C:/Users/chamberlin/Documents/Liron/yellowstone_blink
    Project File:C:/Users/chamberlin/Documents/Liron/yellowstone_blink.ldf
    
+
    
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+
diff --git a/yellowstone_blink1.sty b/yellowstone_blink1.sty
new file mode 100644
index 0000000..4b01225
--- /dev/null
+++ b/yellowstone_blink1.sty
@@ -0,0 +1,204 @@
+
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diff --git a/yellowstone_blink_tcl.html b/yellowstone_blink_tcl.html
new file mode 100644
index 0000000..1e3bb6f
--- /dev/null
+++ b/yellowstone_blink_tcl.html
@@ -0,0 +1,156 @@
+
+Lattice TCL Log
+
+
+
    pn171005145152
+#Start recording tcl command: 10/5/2017 11:43:34
+#Project Location: C:/Users/chamberlin/Documents/Liron; Project name: yellowstone_blink
+C:/Users/chamberlin/Documents/Liron/lattice
+liron
+#Start recording tcl command: 10/5/2017 14:51:52
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project new -name "yellowstone_blink" -impl "yellowstone_blink" -dev LCMXO2-1200HC-4TG100C -synthesis "lse"
+prj_project save
+prj_src add -exclude "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+prj_src enable "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program set -cable USB
+pgr_program set -port EzUSB-0
+prj_src add "C:/Users/chamberlin/Documents/Liron/top.v"
+prj_run PAR -impl yellowstone_blink
+prj_run PAR -impl yellowstone_blink
+prj_run Export -impl yellowstone_blink
+prj_run Export -impl yellowstone_blink
+pgr_program run
+pgr_project save "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_project save "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program run
+prj_run Export -impl yellowstone_blink
+pgr_program run
+prj_run PAR -impl yellowstone_blink
+prj_run PAR -impl yellowstone_blink
+prj_run Export -impl yellowstone_blink
+pgr_project save "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program run
+prj_project save
+prj_project close
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+#Stop recording: 10/5/2017 14:51:52
+
+
+
+pn171005155108
+#Start recording tcl command: 10/5/2017 15:05:29
+#Project Location: C:/Users/chamberlin/Documents/Liron; Project name: yellowstone_blink
+prj_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink.ldf"
+pgr_project close
+pgr_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+prj_run Export -impl yellowstone_blink -task Bitgen -forceOne
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_project save "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+prj_project close
+#Stop recording: 10/5/2017 15:51:08
+
+
+
+pn180130154424
+#Start recording tcl command: 1/25/2018 16:29:45
+#Project Location: C:/Users/chamberlin/Documents/Liron; Project name: yellowstone_blink
+prj_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink.ldf"
+pgr_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+prj_project close
+#Stop recording: 1/30/2018 15:44:24
+
+
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diff --git a/yellowstone_blink_tcr.dir/pn171005145152.tcr b/yellowstone_blink_tcr.dir/pn171005145152.tcr
new file mode 100644
index 0000000..bf53845
--- /dev/null
+++ b/yellowstone_blink_tcr.dir/pn171005145152.tcr
@@ -0,0 +1,32 @@
+#Start recording tcl command: 10/5/2017 11:43:34
+#Project Location: C:/Users/chamberlin/Documents/Liron; Project name: yellowstone_blink
+C:/Users/chamberlin/Documents/Liron/lattice
+liron
+#Start recording tcl command: 10/5/2017 14:51:52
+#Project Location: C:/Users/chamberlin/Documents/Liron/lattice; Project name: liron
+prj_project new -name "yellowstone_blink" -impl "yellowstone_blink" -dev LCMXO2-1200HC-4TG100C -synthesis "lse"
+prj_project save
+prj_src add -exclude "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+prj_src enable "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program set -cable USB
+pgr_program set -port EzUSB-0
+prj_src add "C:/Users/chamberlin/Documents/Liron/top.v"
+prj_run PAR -impl yellowstone_blink
+prj_run PAR -impl yellowstone_blink
+prj_run Export -impl yellowstone_blink
+prj_run Export -impl yellowstone_blink
+pgr_program run
+pgr_project save "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_project save "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program run
+prj_run Export -impl yellowstone_blink
+pgr_program run
+prj_run PAR -impl yellowstone_blink
+prj_run PAR -impl yellowstone_blink
+prj_run Export -impl yellowstone_blink
+pgr_project save "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program run
+prj_project save
+prj_project close
+prj_project open "C:/Users/chamberlin/Documents/Liron/lattice/liron.ldf"
+#Stop recording: 10/5/2017 14:51:52
diff --git a/yellowstone_blink_tcr.dir/pn171005155108.tcr b/yellowstone_blink_tcr.dir/pn171005155108.tcr
new file mode 100644
index 0000000..21b99bc
--- /dev/null
+++ b/yellowstone_blink_tcr.dir/pn171005155108.tcr
@@ -0,0 +1,35 @@
+#Start recording tcl command: 10/5/2017 15:05:29
+#Project Location: C:/Users/chamberlin/Documents/Liron; Project name: yellowstone_blink
+prj_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink.ldf"
+pgr_project close
+pgr_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+prj_run Export -impl yellowstone_blink -task Bitgen -forceOne
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_project save "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+prj_project close
+#Stop recording: 10/5/2017 15:51:08
diff --git a/yellowstone_blink_tcr.dir/pn180130154424.tcr b/yellowstone_blink_tcr.dir/pn180130154424.tcr
new file mode 100644
index 0000000..e145c5a
--- /dev/null
+++ b/yellowstone_blink_tcr.dir/pn180130154424.tcr
@@ -0,0 +1,16 @@
+#Start recording tcl command: 1/25/2018 16:29:45
+#Project Location: C:/Users/chamberlin/Documents/Liron; Project name: yellowstone_blink
+prj_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink.ldf"
+pgr_project open "C:/Users/chamberlin/Documents/Liron/yellowstone_blink/yellowstone_blink.xcf"
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+pgr_program run
+prj_project close
+#Stop recording: 1/30/2018 15:44:24