From 31488767c7ec94b6d9338dc95fc917e2e37d70c5 Mon Sep 17 00:00:00 2001 From: steve-chamberlin Date: Wed, 30 Jan 2019 12:55:46 -0800 Subject: [PATCH] initial commit --- .run_manager.ini | 9 + .setting.ini | 3 + .spread_sheet.ini | 3 + .spreadsheet_view.ini | 76 + LICENSE.TXT | 20 + LIRONALL.bin | Bin 0 -> 4096 bytes LIRONHI.bin | Bin 0 -> 2048 bytes LIRONLO1.bin | Bin 0 -> 256 bytes LIRONLO4.bin | Bin 0 -> 256 bytes LIRONLO5.bin | Bin 0 -> 256 bytes LIRONLO7.bin | Bin 0 -> 256 bytes README.TXT | 105 + control.txt | 3 + disasm.asm | 1749 ++++ disk-II-boot-process.txt | 817 ++ eagle/DB19F adapter/big-mess-o-wires.lbr | 526 ++ eagle/DB19F adapter/db19f.brd | 575 ++ eagle/DB19F adapter/db19f.sch | 707 ++ .../FPGA disk controller/ELL-i-DigitalIC.lbr | 6152 +++++++++++++ eagle/FPGA disk controller/bmowdisk.b#1 | 4034 +++++++++ eagle/FPGA disk controller/bmowdisk.brd | 2923 +++++++ eagle/FPGA disk controller/bmowdisk.lbr | 4703 ++++++++++ eagle/FPGA disk controller/bmowdisk.sch | 7427 ++++++++++++++++ eagle/FPGA disk controller/bmowdisk.scr | 7576 +++++++++++++++++ eagle/FPGA disk controller/bmowdisk1.lbr | 502 ++ eagle/FPGA disk controller/bom.xlsx | Bin 0 -> 12417 bytes eagle/FPGA disk controller/con-apple2.lbr | 913 ++ eagle/FPGA disk controller/eagle.epf | 469 + eagle/Liron - original/74xx-us.lbr | 812 ++ eagle/Liron - original/eagle.epf | 452 + eagle/Liron - original/liron.brd | 1139 +++ eagle/Liron - original/liron.lbr | 1485 ++++ eagle/Liron - original/liron.sch | 3461 ++++++++ eagle/Liron - original/liron3.lbr | 1869 ++++ eagle/Liron - original/memory.lbr | 178 + eagle/Liron - original/pinhead.lbr | 900 ++ lattice/._Real_._Math_.vhd | 2574 ++++++ lattice/.floorplanner.ini | 14 + lattice/.run_manager.ini | 9 + lattice/.setting.ini | 4 + lattice/.spread_sheet.ini | 3 + lattice/.spreadsheet_view.ini | 76 + lattice/Untitled.tpf | 4 + lattice/addrDecoder.v | 37 + lattice/codeROM.edn | 918 ++ lattice/codeROM.ipx | 11 + lattice/codeROM.lpc | 51 + lattice/codeROM.naf | 23 + lattice/codeROM.sort | 1 + lattice/codeROM.srp | 29 + lattice/codeROM.sym | Bin 0 -> 260 bytes lattice/codeROM.v | 295 + lattice/codeROM_tmpl.v | 6 + lattice/fpgatop/.build_status | 40 + lattice/fpgatop/.vdbs/dbStat.txt | 1 + lattice/fpgatop/.vdbs/liron_fpgatop_map.vdb | Bin 0 -> 60806 bytes lattice/fpgatop/.vdbs/top_rtl.vdb | Bin 0 -> 101526 bytes lattice/fpgatop/.vdbs/top_tech.vdb | Bin 0 -> 106230 bytes lattice/fpgatop/Untitled.tpf.prf | 5 + lattice/fpgatop/Untitled.tpf.prf_cdmp | 34 + lattice/fpgatop/Untitled.tpf.prf_cdmp0 | 4 + lattice/fpgatop/Untitled.tpf.prf_cdmp2 | 34 + lattice/fpgatop/Untitled.tpf_hold.html | 535 ++ lattice/fpgatop/Untitled.tpf_setup.html | 662 ++ lattice/fpgatop/codeROM_lse.twr | 50 + lattice/fpgatop/codeROM_prim.v | 184 + lattice/fpgatop/fpgatop.xcf | 51 + lattice/fpgatop/hdla_gen_hierarchy.html | 21 + lattice/fpgatop/liron_fpgatop.alt | 60 + lattice/fpgatop/liron_fpgatop.arearep | 53 + lattice/fpgatop/liron_fpgatop.bgn | 82 + lattice/fpgatop/liron_fpgatop.dir/5_1.ncd | Bin 0 -> 193114 bytes lattice/fpgatop/liron_fpgatop.dir/5_1.pad | 279 + lattice/fpgatop/liron_fpgatop.dir/5_1.par | 200 + lattice/fpgatop/liron_fpgatop.dir/5_1_par.asd | 34 + .../liron_fpgatop.dir/liron_fpgatop.par | 26 + lattice/fpgatop/liron_fpgatop.drc | 2 + lattice/fpgatop/liron_fpgatop.jed | 2767 ++++++ lattice/fpgatop/liron_fpgatop.lpf | 4 + lattice/fpgatop/liron_fpgatop.lsedata | 5083 +++++++++++ lattice/fpgatop/liron_fpgatop.mrp | 468 + lattice/fpgatop/liron_fpgatop.ncd | Bin 0 -> 193114 bytes lattice/fpgatop/liron_fpgatop.ngd | Bin 0 -> 138411 bytes lattice/fpgatop/liron_fpgatop.p2t | 9 + lattice/fpgatop/liron_fpgatop.p3t | 5 + lattice/fpgatop/liron_fpgatop.pad | 279 + lattice/fpgatop/liron_fpgatop.par | 226 + lattice/fpgatop/liron_fpgatop.prf | 67 + lattice/fpgatop/liron_fpgatop.pt | 10 + lattice/fpgatop/liron_fpgatop.t2b | 5 + lattice/fpgatop/liron_fpgatop.twr | 1163 +++ lattice/fpgatop/liron_fpgatop_bgn.html | 148 + lattice/fpgatop/liron_fpgatop_lattice.synproj | 44 + lattice/fpgatop/liron_fpgatop_map.asd | 69 + lattice/fpgatop/liron_fpgatop_map.cam | 68 + lattice/fpgatop/liron_fpgatop_map.hrr | 37 + lattice/fpgatop/liron_fpgatop_map.ncd | Bin 0 -> 145088 bytes lattice/fpgatop/liron_fpgatop_mrp.html | 489 ++ lattice/fpgatop/liron_fpgatop_pad.html | 344 + lattice/fpgatop/liron_fpgatop_par.html | 295 + lattice/fpgatop/liron_fpgatop_summary.html | 83 + lattice/fpgatop/liron_fpgatop_trce.asd | 11 + lattice/fpgatop/liron_fpgatop_twr.html | 1238 +++ lattice/fpgatop/message.xml | 97 + lattice/fpgatop/synthesis_lse.html | 267 + lattice/fpgatop/top_lse.twr | 158 + lattice/fpgatop/top_lse_lsetwr.html | 223 + lattice/fpgatop/top_prim.v | 997 +++ lattice/fpgatop/xxx_lse_cp_file_list | 181 + lattice/fpgatop/xxx_lse_sign_file | 181 + lattice/generate_core.tcl | 100 + lattice/generate_ngd.tcl | 124 + lattice/iwm.v | 296 + lattice/liron.ccl | 1 + lattice/liron.ldf | 29 + lattice/liron.lpf | 109 + lattice/liron1.sty | 204 + lattice/liron_tcl.html | 226 + lattice/liron_tcr.dir/pn170727130134.tcr | 40 + lattice/liron_tcr.dir/pn170727162731.tcr | 21 + lattice/liron_tcr.dir/pn170808144313.tcr | 16 + lattice/liron_tcr.dir/pn171208101159.tcr | 4 + lattice/liron_tcr.dir/pn180117140835.tcr | 5 + lattice/liron_tcr.dir/pn180208150255.tcr | 12 + lattice/liron_tcr.dir/pn180214123353.tcr | 39 + lattice/power-estimate.pcf | 470 + lattice/promote.xml | 5 + lattice/reportview.xml | 10 + lattice/spiFlash.edn | 628 ++ lattice/spiFlash.ipx | 8 + lattice/spiFlash.lpc | 90 + lattice/spiFlash.naf | 35 + lattice/spiFlash.sort | 1 + lattice/spiFlash.srp | 28 + lattice/spiFlash.sym | Bin 0 -> 642 bytes lattice/spiFlash.v | 134 + lattice/spiFlash_tmpl.v | 8 + lattice/sso_rpt.htm | 184 + lattice/tb_codeROM_tmpl.v | 45 + lattice/top.v | 112 + liron.asm | 1300 +++ liron.wrk | Bin 0 -> 80024 bytes promote.xml | 4 + reportview.xml | 10 + rom-full-4k.mem | 4102 +++++++++ rom-upper-2k.bin | Bin 0 -> 2048 bytes rom-upper-2k.mem | 2054 +++++ top.v | 27 + yellowstone_blink.ccl | 1 + yellowstone_blink.ldf | 17 + yellowstone_blink.lpf | 6 + yellowstone_blink/.build_status | 40 + yellowstone_blink/.vdbs/blink_rtl.vdb | Bin 0 -> 15496 bytes yellowstone_blink/.vdbs/blink_tech.vdb | Bin 0 -> 8022 bytes yellowstone_blink/.vdbs/dbStat.txt | 1 + ...ellowstone_blink_yellowstone_blink_map.vdb | Bin 0 -> 30358 bytes yellowstone_blink/blink_lse.twr | 189 + yellowstone_blink/blink_lse_lsetwr.html | 254 + yellowstone_blink/blink_prim.v | 160 + yellowstone_blink/hdla_gen_hierarchy.html | 11 + yellowstone_blink/message.xml | 42 + yellowstone_blink/synthesis_lse.html | 225 + yellowstone_blink/xxx_lse_cp_file_list | 34 + yellowstone_blink/xxx_lse_sign_file | 34 + yellowstone_blink/yellowstone_blink.xcf | 50 + .../yellowstone_blink_yellowstone_blink.alt | 10 + ...ellowstone_blink_yellowstone_blink.arearep | 12 + .../yellowstone_blink_yellowstone_blink.bgn | 71 + .../yellowstone_blink_yellowstone_blink.bit | Bin 0 -> 6229 bytes .../5_1.ncd | Bin 0 -> 23142 bytes .../5_1.pad | 177 + .../5_1.par | 192 + .../5_1_par.asd | 29 + .../yellowstone_blink_yellowstone_blink.par | 28 + .../yellowstone_blink_yellowstone_blink.drc | 1 + .../yellowstone_blink_yellowstone_blink.jed | 2714 ++++++ .../yellowstone_blink_yellowstone_blink.lpf | 4 + ...ellowstone_blink_yellowstone_blink.lsedata | 367 + .../yellowstone_blink_yellowstone_blink.mrp | 204 + .../yellowstone_blink_yellowstone_blink.ncd | Bin 0 -> 23142 bytes .../yellowstone_blink_yellowstone_blink.ngd | Bin 0 -> 22808 bytes .../yellowstone_blink_yellowstone_blink.p2t | 9 + .../yellowstone_blink_yellowstone_blink.p3t | 5 + .../yellowstone_blink_yellowstone_blink.pad | 177 + .../yellowstone_blink_yellowstone_blink.par | 220 + .../yellowstone_blink_yellowstone_blink.prf | 11 + .../yellowstone_blink_yellowstone_blink.pt | 10 + .../yellowstone_blink_yellowstone_blink.t2b | 5 + ...llowstone_blink_yellowstone_blink_bgn.html | 137 + ...ne_blink_yellowstone_blink_lattice.synproj | 41 + ...ellowstone_blink_yellowstone_blink_map.asd | 13 + ...ellowstone_blink_yellowstone_blink_map.cam | 21 + ...ellowstone_blink_yellowstone_blink_map.hrr | 10 + ...ellowstone_blink_yellowstone_blink_map.ncd | Bin 0 -> 17980 bytes ...llowstone_blink_yellowstone_blink_mrp.html | 259 + ...llowstone_blink_yellowstone_blink_pad.html | 242 + ...llowstone_blink_yellowstone_blink_par.html | 289 + ...stone_blink_yellowstone_blink_summary.html | 83 + yellowstone_blink1.sty | 204 + yellowstone_blink_tcl.html | 156 + yellowstone_blink_tcr.dir/pn171005145152.tcr | 32 + yellowstone_blink_tcr.dir/pn171005155108.tcr | 35 + yellowstone_blink_tcr.dir/pn180130154424.tcr | 16 + 203 files changed, 88345 insertions(+) create mode 100644 .run_manager.ini create mode 100644 .setting.ini create mode 100644 .spread_sheet.ini create mode 100644 .spreadsheet_view.ini create mode 100644 LICENSE.TXT create mode 100644 LIRONALL.bin create mode 100644 LIRONHI.bin create mode 100644 LIRONLO1.bin create mode 100644 LIRONLO4.bin create mode 100644 LIRONLO5.bin create mode 100644 LIRONLO7.bin create mode 100644 README.TXT create mode 100644 control.txt create mode 100644 disasm.asm create mode 100644 disk-II-boot-process.txt create mode 100644 eagle/DB19F adapter/big-mess-o-wires.lbr create mode 100644 eagle/DB19F adapter/db19f.brd create mode 100644 eagle/DB19F adapter/db19f.sch create mode 100644 eagle/FPGA disk controller/ELL-i-DigitalIC.lbr create mode 100644 eagle/FPGA disk controller/bmowdisk.b#1 create mode 100644 eagle/FPGA disk controller/bmowdisk.brd create mode 100644 eagle/FPGA disk controller/bmowdisk.lbr create mode 100644 eagle/FPGA disk controller/bmowdisk.sch create mode 100644 eagle/FPGA disk controller/bmowdisk.scr create mode 100644 eagle/FPGA disk controller/bmowdisk1.lbr create mode 100644 eagle/FPGA disk controller/bom.xlsx create mode 100644 eagle/FPGA disk controller/con-apple2.lbr create mode 100644 eagle/FPGA disk controller/eagle.epf create mode 100644 eagle/Liron - original/74xx-us.lbr create mode 100644 eagle/Liron - original/eagle.epf create mode 100644 eagle/Liron - original/liron.brd create mode 100644 eagle/Liron - original/liron.lbr create mode 100644 eagle/Liron - original/liron.sch create mode 100644 eagle/Liron - original/liron3.lbr create mode 100644 eagle/Liron - original/memory.lbr create mode 100644 eagle/Liron - original/pinhead.lbr create mode 100644 lattice/._Real_._Math_.vhd create mode 100644 lattice/.floorplanner.ini create mode 100644 lattice/.run_manager.ini create mode 100644 lattice/.setting.ini create mode 100644 lattice/.spread_sheet.ini create mode 100644 lattice/.spreadsheet_view.ini create mode 100644 lattice/Untitled.tpf create mode 100644 lattice/addrDecoder.v create mode 100644 lattice/codeROM.edn create mode 100644 lattice/codeROM.ipx create mode 100644 lattice/codeROM.lpc create mode 100644 lattice/codeROM.naf create mode 100644 lattice/codeROM.sort create mode 100644 lattice/codeROM.srp create mode 100644 lattice/codeROM.sym create mode 100644 lattice/codeROM.v create mode 100644 lattice/codeROM_tmpl.v create mode 100644 lattice/fpgatop/.build_status create mode 100644 lattice/fpgatop/.vdbs/dbStat.txt create mode 100644 lattice/fpgatop/.vdbs/liron_fpgatop_map.vdb create mode 100644 lattice/fpgatop/.vdbs/top_rtl.vdb create mode 100644 lattice/fpgatop/.vdbs/top_tech.vdb create mode 100644 lattice/fpgatop/Untitled.tpf.prf create mode 100644 lattice/fpgatop/Untitled.tpf.prf_cdmp create mode 100644 lattice/fpgatop/Untitled.tpf.prf_cdmp0 create mode 100644 lattice/fpgatop/Untitled.tpf.prf_cdmp2 create mode 100644 lattice/fpgatop/Untitled.tpf_hold.html create mode 100644 lattice/fpgatop/Untitled.tpf_setup.html create mode 100644 lattice/fpgatop/codeROM_lse.twr create mode 100644 lattice/fpgatop/codeROM_prim.v create mode 100644 lattice/fpgatop/fpgatop.xcf create mode 100644 lattice/fpgatop/hdla_gen_hierarchy.html create mode 100644 lattice/fpgatop/liron_fpgatop.alt create mode 100644 lattice/fpgatop/liron_fpgatop.arearep create mode 100644 lattice/fpgatop/liron_fpgatop.bgn create mode 100644 lattice/fpgatop/liron_fpgatop.dir/5_1.ncd create mode 100644 lattice/fpgatop/liron_fpgatop.dir/5_1.pad create mode 100644 lattice/fpgatop/liron_fpgatop.dir/5_1.par create mode 100644 lattice/fpgatop/liron_fpgatop.dir/5_1_par.asd create mode 100644 lattice/fpgatop/liron_fpgatop.dir/liron_fpgatop.par create mode 100644 lattice/fpgatop/liron_fpgatop.drc create mode 100644 lattice/fpgatop/liron_fpgatop.jed create mode 100644 lattice/fpgatop/liron_fpgatop.lpf create mode 100644 lattice/fpgatop/liron_fpgatop.lsedata create mode 100644 lattice/fpgatop/liron_fpgatop.mrp create mode 100644 lattice/fpgatop/liron_fpgatop.ncd create mode 100644 lattice/fpgatop/liron_fpgatop.ngd create mode 100644 lattice/fpgatop/liron_fpgatop.p2t create mode 100644 lattice/fpgatop/liron_fpgatop.p3t create mode 100644 lattice/fpgatop/liron_fpgatop.pad create mode 100644 lattice/fpgatop/liron_fpgatop.par create mode 100644 lattice/fpgatop/liron_fpgatop.prf create mode 100644 lattice/fpgatop/liron_fpgatop.pt create mode 100644 lattice/fpgatop/liron_fpgatop.t2b create mode 100644 lattice/fpgatop/liron_fpgatop.twr create mode 100644 lattice/fpgatop/liron_fpgatop_bgn.html create mode 100644 lattice/fpgatop/liron_fpgatop_lattice.synproj create mode 100644 lattice/fpgatop/liron_fpgatop_map.asd create mode 100644 lattice/fpgatop/liron_fpgatop_map.cam create mode 100644 lattice/fpgatop/liron_fpgatop_map.hrr create mode 100644 lattice/fpgatop/liron_fpgatop_map.ncd create mode 100644 lattice/fpgatop/liron_fpgatop_mrp.html create mode 100644 lattice/fpgatop/liron_fpgatop_pad.html create mode 100644 lattice/fpgatop/liron_fpgatop_par.html create mode 100644 lattice/fpgatop/liron_fpgatop_summary.html create mode 100644 lattice/fpgatop/liron_fpgatop_trce.asd create mode 100644 lattice/fpgatop/liron_fpgatop_twr.html create mode 100644 lattice/fpgatop/message.xml create mode 100644 lattice/fpgatop/synthesis_lse.html create mode 100644 lattice/fpgatop/top_lse.twr create mode 100644 lattice/fpgatop/top_lse_lsetwr.html create mode 100644 lattice/fpgatop/top_prim.v create mode 100644 lattice/fpgatop/xxx_lse_cp_file_list create mode 100644 lattice/fpgatop/xxx_lse_sign_file create mode 100644 lattice/generate_core.tcl create mode 100644 lattice/generate_ngd.tcl create mode 100644 lattice/iwm.v create mode 100644 lattice/liron.ccl create mode 100644 lattice/liron.ldf create mode 100644 lattice/liron.lpf create mode 100644 lattice/liron1.sty create mode 100644 lattice/liron_tcl.html create mode 100644 lattice/liron_tcr.dir/pn170727130134.tcr create mode 100644 lattice/liron_tcr.dir/pn170727162731.tcr create mode 100644 lattice/liron_tcr.dir/pn170808144313.tcr create mode 100644 lattice/liron_tcr.dir/pn171208101159.tcr create mode 100644 lattice/liron_tcr.dir/pn180117140835.tcr create mode 100644 lattice/liron_tcr.dir/pn180208150255.tcr create mode 100644 lattice/liron_tcr.dir/pn180214123353.tcr create mode 100644 lattice/power-estimate.pcf create mode 100644 lattice/promote.xml create mode 100644 lattice/reportview.xml create mode 100644 lattice/spiFlash.edn create mode 100644 lattice/spiFlash.ipx create mode 100644 lattice/spiFlash.lpc create mode 100644 lattice/spiFlash.naf create mode 100644 lattice/spiFlash.sort create mode 100644 lattice/spiFlash.srp create mode 100644 lattice/spiFlash.sym create mode 100644 lattice/spiFlash.v create mode 100644 lattice/spiFlash_tmpl.v create mode 100644 lattice/sso_rpt.htm create mode 100644 lattice/tb_codeROM_tmpl.v create mode 100644 lattice/top.v create mode 100644 liron.asm create mode 100644 liron.wrk create mode 100644 promote.xml create mode 100644 reportview.xml create mode 100644 rom-full-4k.mem create mode 100644 rom-upper-2k.bin create mode 100644 rom-upper-2k.mem create mode 100644 top.v create mode 100644 yellowstone_blink.ccl create mode 100644 yellowstone_blink.ldf create mode 100644 yellowstone_blink.lpf create mode 100644 yellowstone_blink/.build_status create mode 100644 yellowstone_blink/.vdbs/blink_rtl.vdb create mode 100644 yellowstone_blink/.vdbs/blink_tech.vdb create mode 100644 yellowstone_blink/.vdbs/dbStat.txt create mode 100644 yellowstone_blink/.vdbs/yellowstone_blink_yellowstone_blink_map.vdb create mode 100644 yellowstone_blink/blink_lse.twr create mode 100644 yellowstone_blink/blink_lse_lsetwr.html create mode 100644 yellowstone_blink/blink_prim.v create mode 100644 yellowstone_blink/hdla_gen_hierarchy.html create mode 100644 yellowstone_blink/message.xml create mode 100644 yellowstone_blink/synthesis_lse.html create mode 100644 yellowstone_blink/xxx_lse_cp_file_list create mode 100644 yellowstone_blink/xxx_lse_sign_file create mode 100644 yellowstone_blink/yellowstone_blink.xcf create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.alt create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.arearep create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.bgn create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.bit create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.ncd create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.pad create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1.par create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/5_1_par.asd create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.dir/yellowstone_blink_yellowstone_blink.par create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.drc create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.jed create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.lpf create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.lsedata create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.mrp create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.ncd create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.ngd create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.p2t create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.p3t create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.pad create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.par create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.prf create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.pt create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink.t2b create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_bgn.html create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_lattice.synproj create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_map.asd create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_map.cam create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_map.hrr create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_map.ncd create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_mrp.html create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_pad.html create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_par.html create mode 100644 yellowstone_blink/yellowstone_blink_yellowstone_blink_summary.html create mode 100644 yellowstone_blink1.sty create mode 100644 yellowstone_blink_tcl.html create mode 100644 yellowstone_blink_tcr.dir/pn171005145152.tcr create mode 100644 yellowstone_blink_tcr.dir/pn171005155108.tcr create mode 100644 yellowstone_blink_tcr.dir/pn180130154424.tcr diff --git a/.run_manager.ini b/.run_manager.ini new file mode 100644 index 0000000..b1c6327 --- /dev/null +++ b/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[yellowstone_blink%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/.setting.ini b/.setting.ini new file mode 100644 index 0000000..85836a3 --- /dev/null +++ b/.setting.ini @@ -0,0 +1,3 @@ +[General] +AutoAssign=false +Export.auto_tasks=Bitgen, Jedecgen diff --git a/.spread_sheet.ini b/.spread_sheet.ini new file mode 100644 index 0000000..6c511f4 --- /dev/null +++ b/.spread_sheet.ini @@ -0,0 +1,3 @@ +[General] +COLUMN_POS_INFO_NAME_-1_0=Prioritize +COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/.spreadsheet_view.ini b/.spreadsheet_view.ini new file mode 100644 index 0000000..773925b --- /dev/null +++ b/.spreadsheet_view.ini @@ -0,0 +1,76 @@ +[General] +pin_sort_type=0 +pin_sort_ascending=true +sig_sort_type=0 +sig_sort_ascending=true +active_Sheet=Port Assignments + +[Port%20Assignments] +Name="140,0" +Group%20By="84,1" +Pin="50,2" +BANK="62,3" +BANK_VCC="90,4" +VREF="60,5" +IO_TYPE="80,6" +PULLMODE="92,7" +DRIVE="67,8" +SLEWRATE="92,9" +CLAMP="71,10" +OPENDRAIN="97,11" +DIFFRESISTOR="114,12" +DIFFDRIVE="92,13" +HYSTERESIS="101,14" +Outload%20%28pF%29="103,15" +MaxSkew="87,16" +Clock%20Load%20Only="121,17" +SwitchingID="100,18" +Ground%20plane%20PCB%20noise%20%28mV%29="196,19" +Power%20plane%20PCB%20noise%20%28mV%29="190,20" +SSO%20Allowance%28%25%29="138,21" +sort_columns="Name,Ascending" + +[Pin%20Assignments] +Pin="90,0" +Pad%20Name="89,1" +Dual%20Function="158,2" +Polarity="77,3" +BANK="0,4" +BANK_VCC="90,5" +IO_TYPE="80,6" +Signal%20Name="102,7" +Signal%20Type="98,8" +sort_columns="Pin,Ascending" + +[Clock%20Resource] +Clock%20Type="100,ELLIPSIS" +Clock%20Name="100,ELLIPSIS" +Selection="100,ELLIPSIS" + +[Global%20Preferences] +Preference%20Name="230,ELLIPSIS" +Preference%20Value="236,ELLIPSIS" + +[Cell%20Mapping] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Din\Dout="100,ELLIPSIS" +PIO%20Register="100,ELLIPSIS" + +[Route%20Priority] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Prioritize="100,ELLIPSIS" + +[Timing%20Preferences] +Preference%20Name="138,ELLIPSIS" +Preference%20Value="104,ELLIPSIS" +Preference%20Unit="813,ELLIPSIS" + +[Group] +Group%20Type\Name="134,ELLIPSIS" +Value="921,ELLIPSIS" + +[Misc%20Preferences] +Preference%20Name="117,ELLIPSIS" +Preference%20Value="938,ELLIPSIS" diff --git a/LICENSE.TXT b/LICENSE.TXT new file mode 100644 index 0000000..331f23b --- /dev/null +++ b/LICENSE.TXT @@ -0,0 +1,20 @@ +The FPGA disk controller card design is provided by Steve Chamberlin, Big Mess o' Wires, under the Creative Commons Attribution - ShareAlike 4.0 license. + +see https://creativecommons.org/licenses/by-sa/4.0/ + +Please note that the marks "Yellowstone", "BMOW", and "Big Mess o' Wires" are not covered by this license, and are reserved for exclusive use by Steve Chamberlin. You are not permitted to use any of these words in the name of any clone or derivative products based on this design. You will need to choose a new name for any clone or derivative product you may create. + +------- + +You are free to: + +Share — copy and redistribute the material in any medium or format +Adapt — remix, transform, and build upon the material +for any purpose, even commercially. + +Under the following terms: + +Attribution — You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use. + +ShareAlike — If you remix, transform, or build upon the material, you must distribute your contributions under the same license as the original. + diff --git a/LIRONALL.bin b/LIRONALL.bin new file mode 100644 index 0000000000000000000000000000000000000000..a7e7b6283f029834793e767b48dee866e23d0ff8 GIT binary patch literal 4096 zcmds)Z%iBK9mk)ueYSC`#aWilTC3!;wGGf0Mb)HPnyMNI#KZ@I#0J|@CBI2#q`jW} zW{cP4VJ-`qqiqsMV>@{~7H7qodC@6Mx%3Es>N5eKQdD(nmy)KSkN`aqsyL9ud!EPk z+!`dt%k7Zw`F(%){GR9c`Q1Ht4^vBPE06E4EeMa-me$u7R)sH~2s2Cf?%!Ql7RDYu zTv~ku^8e3AjEjMoUI8hKJ;m5!%&$TQTWsu7&J<&k`7D2TS^&u9RQ3F|vE-j*>n8La zKYqMsZvy#hOwdPN?;Oco?rd^EM_Sb_b`@MdDY**r*tca@Ns@qgag_fuWXh%K`PWOy z1fh%0V6T1E*W|cDGL+Nm%W+;a3!uZD&Zrv+bzgE&PX1Z0+e}7fTR`MgooKZO@&JGj zEEW7Z%72sa>niwfCa-MeC$0*9>MFxfS>~s*l7BZL1^!Ypgr7tg`H8t5e^O3fCH%rp z{CdhiPWbf|{Nu^%TltBrf}gs|{8X0tsjTGRO-O;ilnmh~(M5h@ZpSal$s2?}wG+RA z@=p+cLk0gt^43;<;;P`Mt};KBWqv9v`F9gi;4dXZ_(^n;pP1Y6&&bJH!Y}W{&r<$L z!p~OlPbNRx%1>Ms{M1$Er?SjXWhMV^LJIt)WC%ZrF7gv|JN|#k$vcE!-HG2w`KJiK zv4VdpxxAI1xGMOmtISVjnV-r^{@sKW_)EzUeiB{eC+2qiD{^v`@XznWZ=(Dk5`I$! z|A)z^TltBrf}gs|{8X0tsjTGRO-O;ilnmh~(M5h@ZpZ&jPCh66+7^CpHN&wP!NiHv z(r;zyJz02Dx+K?`B5Kagw=;MpB%BSA%9hv`$XYBR?z7} zOH7_Rk*m<~+5sVte5I)Lh`TC0!AHMBF8n#&uROqC)_Ob|YOM-i@Lj)%Q^#t^H_{1P zEw9z5Rd%t9|7+SA6m@JptVeBCVSF85Z6jCFiIO})WqV1s|0niy9E&EHlB9fN&mucjvN|e$;j^kAc3@E1YNxCT4IMgRN3&9dm%_74c%GgszQZLOWg=Ks_ zFrI(_weEU=!o#`=`5C4AYP#`RtO`AHy# zO8_K1!0pZ8StKY6?Oaa5O0aNwC8BNwVt9w}EPy$r^Ro0CnOYd+U0J#yOFeP`c`f)z z1j5Aw?-}SpBr(b@vA^*H;cxwktN^&)Oq3PF+{#RVm>bkg=8Uj488X2(@tUwF?j6h- z`UgWSYVFGzQCnZg#DR3VPxOVj_fF2B&ff{K)=vXNUXdNh8MuHF-77Ez?JcFyVL1R^ zX#oZXFgiokcgdO2fphtIo3@|ciSRt585X-lKx-=fGXq`HXBo)H@XQcz?S_rM=mBXV zV>`nurl@Yo1bON6%o!JSW$KLT7ybO9Y2zf>!8hWzob^SlIr~{3;=g%IjrNhwfmTq**v{7DC1yWck2-DL zCfFIpyTpJLk?|A5|9!e2FUJ0NF3B~A)b#*z4aY!_E2g)+=E8eDoG$L{y1?5P_>^wS zHRK9J^}KKPliuOckfCm0a3IIpy7h_RK*-n)oV`wSDE89(4rj)?alt#9Gb%_mwd8#v zlg5ew-zd~rYp$)WuC39x=wt(a#&n7MJ&kxMtDeu^8qKlLJsL7XkHCz$VFO;_3H*be z9=FKE8|E!|?!U|k0K5ExdBi=?0Pt%CHLAXNgLH4E=G?GonDDEg&aY^GQJ zk$5=XtWNaCy@KiTQCvVNhugFWE*}-m5$?n+-*-zfsC(kg+MbMN77wfa;y(2c;vqFE zRu6e^Xi8{Ov-NESoMGt>sW?rWnMG(`ehWIhm+|!09 zeHRb(vrN<=8r8Rlyrfz$;Hk`FQw%_NkB5^osV}(?rZEV1zf{QVd#HIZ$D(6{AtP$4 zv8o2~4ONF)hrIatPG~>4fd@Gd1BxT{o!AlOb*)ON)>!2Yjp@ZbLTn5K|LC|s|8g`} zjc-a~G{idbeHpd|HO3y$>(4Xi8HUlHcXA6#Fo7DJsL_d zQ>??Hzf?fH0;BAdpa1bJUTCOQTR?u2mMI9EgRn7(M?eEPV@rM@WD1Z4%;E)X4D@)# z#9+uUm@^9O=!;o$@2!suuM^nFEl#HnTm|Ngy7ww$)-1)>49}Rk-#_Qxdmaa>CC)78 zO!!OjkB!*(dtT*!_!KAiN(|tF;unA}W>Ko~`JjT!6nj&eo7Ifm%Cr0G*F2b4{+1Oc zZ{N<|2D8~YVNAH0&CZS8yfrCIC?8E@pD;1`u`)g>jAv(OC&%X|C#Vl!6XvqCGho_* u8T_yR<2yVq3L~S}-WSF+ZFxZ$|7u11dVOK-ilD6CyDH3lGzP5s{J#MU4vMt^ literal 0 HcmV?d00001 diff --git a/LIRONHI.bin b/LIRONHI.bin new file mode 100644 index 0000000000000000000000000000000000000000..35742e5a500c93525c9eb877d2b285a1ce1094b9 GIT binary patch literal 2048 zcmdT^&2Jk;6rWvt*B?dHr4%ec?Uv7^9EcEyNC@G?t#R-=OciSAdWWaT>`uAI(4N;-fi}ip)o1#Q-KX@@jqwq^ z82E`~e0k|JL;BPpM>eU$%FRU*+a$8JOKp&J%c?e=@a5;_(vKv@T=GuivWiF-cq4IN z{$%>YQ+mMhJ&~Rsz;XZmT{R}G56W-VqFKrdUAT+%`tq<3yS>gXIoJ{pHpRY{*!Q>X z*I-NfTkHKzwL>lOP*XhI5)V7#`IzOBpR19Oui8q7gr4+Op+H)LNjs&thuCkBh3YRd zFXf~?X6KaX;AI81ybk-yT;unj>yJxEjLVlVEAnFoML0wfcz`7FAl-`(kyLO<$AZVqw0+jomIb38iUsPtMpn^FyiV}3oko}7qVK9CbdcB4OmLs^`hkc)5|($fk5v2-zDcOFX<`QJw>c1{nB#ZdS#TIQrBpdix%BT_Lf_GAhK%F8}>8lWjn{ zpd33Xcdp4({Q1~KOewkK^zvuJlQTJY$ByinEd+;L)$CYK9756Is5e)>^K2+;1~yKn zW^BYv za5r>#6@Hv7Bq&$uUiCxlHle;jo@* z0SFyf63%DjN0y<{NZeW@87D1I7Duu;oCObL%ockZV>yrFG_U{-EGmT*t&Zp1@ zGq=^9vk&~b`JCXew7xjC>kRUmZ2K9`Yx%dH8JY7+ul*^#^k)Sze}%hZdzef9V559{ z;Xdi^-yyks%Lo942Y@g8jW(Ef8vs-JVQppE5~ZtuTw=e-Xw`VPt}a}>Sigvt>nrN4 zdahnynLT%5L7g`~S%fupe&JJNZb6-^FE205tt`wp*I-XwsW+7o*N40aHU8gYa*nFg kGw+{OXD#c>nmYI6RqL1QYd^iM8rQx(qb_|iivkVxFL4GUdH?_b literal 0 HcmV?d00001 diff --git a/LIRONLO1.bin b/LIRONLO1.bin new file mode 100644 index 0000000000000000000000000000000000000000..912171147ab8afca5f5102d6be5ead2c7b58f498 GIT binary patch literal 256 zcmZ3au!vz1^GSvcToxM`B^EK(Rj^1bI@tGveG%i@|L1)ko?gJP)Z60%v(Ju$Yv&vg z_}v=m<>jTxziMfuCVOinSSVKg)Wk4XhgOFZ7nq)fLxjv>LJ+PyDmNU)1!-6YHHAnm z$Gkr<`)I=)lhNu8w!uP6HPY2#4akKDPF#>#=JSDL0YhNOiBlJTt-2t%cJ6_-^9~sN ZUOVA{M8Zmi3rs5oEE4`RFfi=r0su;#dbR)n literal 0 HcmV?d00001 diff --git a/LIRONLO4.bin b/LIRONLO4.bin new file mode 100644 index 0000000000000000000000000000000000000000..b8773c9f5be02d78bcc1470298ec375cea321679 GIT binary patch literal 256 zcmZ3au!vz1^GSvcToxM`B^I&NRj^1bI@0%peG$vr|L1)ko?gJP)Z60%v(JtrYtI}I z_}v=m<>jTxziMfuCVOinSSVKg)Wk4XhgOFZ7nq)fLxjv>LJ+PyDmNU)1!-6YHHAnm z$Gkr<`)I=)lhNu8w!uP6HPY2#4akKDPF#>#=JSDL0YhNOiBlJTt-2t%_UwVR=MEVB ZUVGqxM8Zmi3rs5oEE4`RFfi=r0svjTxziMfuCVOinSSVKg)Wk4XhgOFZ7nq)fLxjv>LJ+PyDmNU)1!-6YHHAnm z$Gkr<`)I=)lhNu8w!uP6HPY2#4akKDPF#>#=JSDL0YhNOiBlJTt-2t%_U?hT_YN5R ZUVGtyM8Zmi3rs5oEE4`RFfi=r0szJEeo6oU literal 0 HcmV?d00001 diff --git a/LIRONLO7.bin b/LIRONLO7.bin new file mode 100644 index 0000000000000000000000000000000000000000..4a3498f02d4b1b39d3f8402bb8e13b8ed22542f3 GIT binary patch literal 256 zcmZ3au!vz1^GSvcToxM`B^I&QRj^1bI^Oq#eG&WG|L1)ko?gJP)Z60%v(Jv>YyTV& z_}v=m<>jTxziMfuCVOinSSVKg)Wk4XhgOFZ7nq)fLxjv>LJ+PyDmNU)1!-6YHHAnm z$Gkr<`)I=)lhNu8w!uP6HPY2#4akKDPF#>#=JSDL0YhNOiBlJTt-2t%_V0nU{|*@Z ZUi;yIM8Zmi3rs5oEE4`RFfi=r0sw=dfD`}# literal 0 HcmV?d00001 diff --git a/README.TXT b/README.TXT new file mode 100644 index 0000000..7306773 --- /dev/null +++ b/README.TXT @@ -0,0 +1,105 @@ +Compiled by Steve Chamberlin +steve@bigmessowires.com +January 28, 2019 + +//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\ + +I'm sharing the FPGA disk controller design because I don't currently have the time or resources to pursue its further development on my own, but want the Apple II collector community to get the benefit of the progress I've made to date. + +See LICENSE.TXT for details on the license terms for this design. + +The marks "Yellowstone", "BMOW", and "Big Mess o' Wires" are not covered by this license, and are reserved for my exclusive use. You are not permitted to use any of these words in the name of any clone or derivative products based on this design. You will need to choose a new name for your clone or derivative product. + +//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\ + +GROUND RULES +------------ + +Please don't send me detailed questions and requests for help with this design, or expect me to be your engineering consultant. I'm releasing the design to the community because I don't have time to pursue it myself. That means I can't work on it for you, either. The design is released as-is, with no promise of technical support. I may be able to answer general questions, but the rest is up to you. + + +WHAT IS THIS? +------------- + +Yellowstone is the code name for an Apple II disk controller card that's based on an FPGA, rather than using discrete logic chips and ROM chips. By reprogramming the FPGA, the card can be made to emulate various other disk controller cards made by Apple in the 1980s and 1990s. The work so far has focused on emulating an Apple Liron disk controller card, but it would also be easy to emulate a Disk II controller card. It's theoretically also possible to emulate a Disk 3.5 controller card, though this possibility has not been explored in detail. + + +WHAT'S LIRON? +------------- + +The Liron disk controller was introduced by Apple in 1985. More formally known as the Apple II UniDisk 3.5 Controller, it's designed to work with a new generation of "smart" disk drives more sophisticated than the venerable Disk II 5.25 inch floppy drive. The smart disk port on the Liron is appropriately named the Smartport, and it can communicate with block-based storage devices such as the Unidisk 3.5 (an early 800K drive) and Smartport-based Apple II hard drives. + +Why care about the Liron? The Apple IIc and Apple IIgs have integrated disk ports with built-in Smartport functionality, but for the earlier Apple II+ and IIe, the Liron is the only way to get a Smartport. For owners of the BMOW Floppy Emu disk emulator, having a Liron card makes it possible to use the Floppy Emu as an external hard drive for the II+ and IIe. Unfortunately finding a Liron is difficult, and although they occasionally turn up on eBay, they’re quite expensive. That makes cloning the Liron a desirable goal. + + +HOW IT WORKS +------------ + +The FPGA disk controller card is little more than an FPGA, a voltage regulator, and a set of level-shifting bus transceivers. The FPGA replaces all of the 7400-series discrete logic chips typically found on a disk controller card. Verilog (hardware description language) replacements for all of the 7400-series parts and other logic were written and programmed into the FPGA. This also includes a full Verilog implmentation of the Apple IWM chip. + +The FPGA also replaces the ROM chip containing the boot code for the card. The Apple II executes this code during power-up, and the code knows how to find and load sector 0 from the attached disk drive. The code was obtained from a ROM dump from a real Liron card. + +The prototype card also includes a footprint for an 8-pin SPI flash memory chip. It is not used by the current FPGA code, and the chip can be omitted. The idea was that a small number of disk images could be stored in SPI flash memory, so the card could function both as a disk controller and as a disk emulator, but this was never implemented. + +The card has a standard 10 x 2 pin disk connector on board. It can be connected directly to a BMOW Floppy Emu disk emulator, using a standard ribbon cable. But for a full Liron clone and connecton to a Unidisk 3.5, a DB-19 female connector is required. A design for a DB-19F adapter PCB is included here, and the adapter can be connected to the disk controller card with a short ribbon cable. The DB-19F is still available from surplus electronics suppliers in small quantities. + + +PROJECT STATUS +-------------- + +See https://www.bigmessowires.com/category/yellowstone/ for a complete history of work involving the FPGA disk controller. + +The FPGA disk controller card was designed by Steve Chamberlin at Big Mess o' Wires during the summer of 2017, but the first prototype card wasn't built and tested until January 2018. The version 1.0 card had errors with the wiring for the output enable signal on one of the bus transceiver chips, and it required a few hand-soldered path wires to fix. After further development, the prototype card was demonstrated to work as a Liron clone, in both an Apple IIe enhanced computer and an Apple IIgs. It worked for controlling a real Unidisk 3.5 drive, as well as a BMOW Floppy Emu disk emulator configured for Smartport emulation mode. + +Later testing discovered that the FPGA disk controller card worked reliably when it was the only card installed, but other cards were also present, it sometimes malfunctioned. The more other cards present, the worse the rate of errors became. This was diagnosed as a likely termination or contention problem on the Apple II data bus, and various fixes were tried unsuccessfully. After March 2018, I lost interest in researching the problem further, and no more work has occurred since then. + +The design provided here is version 1.1, and it fixes the output enable problem from version 1.0. + + +WHERE TO START +-------------- + +Open the FPGA disk controller design (Liron clone) in EAGLE. Export Gerber files and send them to your favorite PCB fabricator. If desired, do the same for the DB19F adapter design. + +Purchase the chips and other parts listed in the BOM. + +Assemble the card. I did it by hand, you can do it too. A syringe of solder paste and a hot plate or toaster oven works nicely. + +Get a Lattice JTAG programmer or appropriate clone. Some clones don't handle 3.3V logic correctly. Maybe spend the extra money for a genuine Lattice programmer. + +Install the Lattice Diamond software. + +Apply 5V power to the card at jumper J4. Do not insert the card into your Apple II yet. + +Program the FPGA with the bitstream for the Liron clone design - liron_fpgatop.jed + +Insert the card in your Apple II. Remove any other cards that are present. + +Connect a Smartport-compatible disk drive, such as a BMOW Floppy Emu disk emulator that's configured for Smartport emulation mode, or an Apple Unidisk 3.5 drive. + +Turn on the Apple II. It should boot from the attached drive. + + +NEXT STEPS +---------- + +The bus termination or bus contention problem must be solved, in order to get a robust card that works smoothly when other cards are also present. See the blog posts from February-March 2018 for more details about what was already tried. A solution will require a person who's experienced at electronic design, and has appropriate test equipment such as an oscilloscope and logic analyzer. + +The current design uses a Lattice MachXO2 1200HC FPGA, and a Lattice JTAG programmer (or compatible) is required for programming it. The XO2-1200HC has more logic resources than are actually necessary for the Liron clone design. The cheaper XO2-640 or XO2-256 could be substituted instead. They are mostly or entirely pin-compatible with the XO2-1200HC. + +Programming the FPGA with a JTAG programmer is fine for development use, but end users are unlikely to have one. If reprogramming by the end user is desired (say to switch between Liron and Disk 3.5 emulation behaviors), a different method of FPGA programming will need to be developed. + + +FILES +----- + +eagle/ - directory containing EAGLE designs for the FPGA disk controller card, the DB19F adapter, and a reverse-engineered schematic of the original Liron card. +eagle/FPGA disk controller/bom.xslx - bill of materials needed to assemble the card. +lattice/ - directory containing the Verilog and other code for the Liron clone design for the card. +yellowstone_blink/ - directory containing the Verilog and other code for a simple LED blink example. This can be used to verify that the FPGA is working. +yellowstone_blink_tcr.dir/ - directory containing some junk generated by the Lattice Diamond software. +disasm.asm, liron.asm - two different disassemblies of the original Liron card's boot ROM +LIRONALL.BIN - binary file with the original Liron card's boot ROM +rom-full-4k.mem - the Liron boot ROM in a format compatible with the Lattice Diamond software. +README.TXT - this file +LICENSE.TXT - details about the license for the design diff --git a/control.txt b/control.txt new file mode 100644 index 0000000..247d65a --- /dev/null +++ b/control.txt @@ -0,0 +1,3 @@ +load $C000 LIRONALL.bin +entry $C700 +save disasm.asm diff --git a/disasm.asm b/disasm.asm new file mode 100644 index 0000000..aa96208 --- /dev/null +++ b/disasm.asm @@ -0,0 +1,1749 @@ +L0000 = $0000 +L0001 = $0001 +L0002 = $0002 +L0003 = $0003 +L0024 = $0024 +L0025 = $0025 +L0040 = $0040 +L0041 = $0041 +L0042 = $0042 +L0043 = $0043 +L0044 = $0044 +L0045 = $0045 +L0046 = $0046 +L0047 = $0047 +L0048 = $0048 +L0049 = $0049 +L004B = $004B +L004C = $004C +L004D = $004D +L004E = $004E +L004F = $004F +L0050 = $0050 +L0051 = $0051 +L0052 = $0052 +L0053 = $0053 +L0054 = $0054 +L0055 = $0055 +L0056 = $0056 +L0057 = $0057 +L0058 = $0058 +L0059 = $0059 +L005A = $005A +L005B = $005B +L0083 = $0083 +L00A0 = $00A0 +L00B9 = $00B9 +L00C2 = $00C2 +L00C4 = $00C4 +L00C5 = $00C5 +L00C9 = $00C9 +L00F0 = $00F0 +L00F2 = $00F2 +L0478 = $0478 +L04F8 = $04F8 +L0578 = $0578 +L05F8 = $05F8 +L0678 = $0678 +L06F8 = $06F8 +L0778 = $0778 +L07F8 = $07F8 +L0800 = $0800 +L0801 = $0801 +LA0C5 = $A0C5 +LA0CF = $A0CF +LAEE3 = $AEE3 +LD4CF = $D4CF +LE000 = $E000 +LF5F0 = $F5F0 +LFABA = $FABA +LFC22 = $FC22 +LFDED = $FDED +LFE89 = $FE89 +LFE93 = $FE93 + + .org $C700 + LDX #$20 + LDX #$00 + LDX #$03 + CMP #$00 + BCS LC714 + + SEC + BCS LC70E + + CLC +.LC70E + LDX #$07 + ROR L0478,X + CLC +.LC714 + LDX #$C7 + STX L07F8 + LDX #$07 + LDA LCFFF + JMP LCBE1 + + LDY #$00 + LDA L004B + PHA + BNE LC72B + + JMP LC7B8 + +.LC72B + LDA LC0FC + BPL LC72B + + STA L0059 + LSR A + LSR A + LSR A + AND #$0F + TAX + LDA L0059 + AND #$07 + STA L0059 +.LC73E + LDA LC0FC + BPL LC73E + + EOR LCA27,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY + BNE LC751 + + INC L0057 +.LC751 + LDA LC0FC + BPL LC751 + + EOR LCA37,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY +.LC760 + LDA LC0FC + BPL LC760 + + EOR LCA47,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY +.LC76F + LDA LC0FC + BPL LC76F + + EOR LCA57,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY + BNE LC782 + + INC L0057 +.LC782 + LDX L0059 +.LC784 + LDA LC0FC + BPL LC784 + + EOR LCA37,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY +.LC793 + LDA LC0FC + BPL LC793 + + EOR LCA47,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY +.LC7A2 + LDA LC0FC + BPL LC7A2 + + EOR LCA57,X + STA (L0056),Y + EOR L0040 + STA L0040 + INY + DEC L004B + BEQ LC7B8 + + JMP LC72B + +.LC7B8 + LDA LC0FC + BPL LC7B8 + + STA L0059 + PLA + STA L004B +.LC7C2 + LDA LC0FC + BPL LC7C2 + + SEC + ROL A + AND L0059 + EOR L0040 +.LC7CD + LDY LC0FC + BPL LC7CD + + CPY #$C8 + BNE LC7F2 + + LDX L004C + BEQ LC7E2 + + LDY #$00 +.LC7DC + EOR (L0054),Y + INY + DEX + BNE LC7DC + +.LC7E2 + TAX + BNE LC7F6 + + LDA LC0FD +.LC7E8 + LDA LC0FE + BMI LC7E8 + + LDA LC0F0 + CLC + RTS + +.LC7F2 + LDA #$20 + BNE LC7F8 + +.LC7F6 + LDA #$10 +.LC7F8 + SEC + RTS + +; PC=C7FA INVALID opcode FF + BRK + BRK + BRK +; PC=C7FE INVALID opcode BF + ASL A +.LC800 + JSR LCAEE + + JSR LCA05 + + LDY #$07 + JSR LCBA9 + + LDA LC08B,X + LDA LC089,X + LDY #$32 +.LC813 + LDA LC08E,X + BMI LC81F + + DEY + BNE LC813 + + SEC + JMP LC949 + +.LC81F + LDA LC081,X + LDY #$05 + LDA #$FF + STA LC08F,X +.LC829 + LDA LC950,Y +.LC82C + ASL LC08C,X + BCC LC82C + + STA LC08D,X + DEY + BPL LC829 + + LDA L005A + ORA #$80 + JSR LC9D8 + + JSR LC9D6 + + LDA L005B + JSR LC9D8 + + JSR LC9D6 + + JSR LC9D6 + + LDA L004C + ORA #$80 + JSR LC9D8 + + LDA L004B + ORA #$80 + JSR LC9D8 + + LDA L004C + BEQ LC873 + + LDY #$FF + LDA L0059 +.LC862 + ASL LC08C,X + BCC LC862 + + STA LC08D,X + INY + LDA (L0054),Y + ORA #$80 + CPY L004C + BCC LC862 + +.LC873 + LDA L004B + BNE LC87A + + JMP LC913 + +.LC87A + NOP + LDY #$00 +.LC87D + LDA L0041 + STA LC08D,X + LDA L004D + ORA #$80 + STY L0059 +.LC888 + LDY LC08C,X + BPL LC888 + + STA LC08D,X + LDY L0059 + LDA (L0056),Y + STA L004D + ASL A + ROL L0041 + INY + BNE LC8A1 + + INC L0057 + JMP LC8A3 + +.LC8A1 + PHA + PLA +.LC8A3 + LDA #$02 + ORA L0041 + STA L0041 + LDA L004E + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L004E + ASL A + ROL L0041 + INY + LDA L004F + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L004F + ASL A + ROL L0041 + INY + LDA L0050 + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L0050 + ASL A + ROL L0041 + INY + BNE LC8DD + + INC L0057 + JMP LC8DF + +.LC8DD + PHA + PLA +.LC8DF + LDA L0051 + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L0051 + ASL A + ROL L0041 + INY + LDA L0052 + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L0052 + ASL A + ROL L0041 + INY + LDA L0053 + ORA #$80 + STA LC08D,X + LDA (L0056),Y + STA L0053 + ASL A + ROL L0041 + INY + DEC L004B + BEQ LC913 + + JMP LC87D + +.LC913 + LDA L0040 + ORA #$AA +.LC917 + LDY LC08C,X + BPL LC917 + + STA LC08D,X + LDA L0040 + LSR A + ORA #$AA + JSR LC9D8 + + LDA #$C8 + JSR LC9D8 + +.LC92C + LDA LC08C,X + AND #$40 + BNE LC92C + + STA LC08D,X + LDY #$0A +.LC938 + DEY + BNE LC943 + + LDA #$01 +.LC93D + JSR LCA1F + + SEC + BCS LC949 + +.LC943 + LDA LC08E,X + BMI LC938 + + CLC +.LC949 + LDA LC080,X + LDA LC08C,X + RTS + +.LC950 +; PC=C950 INVALID opcode C3 +; PC=C951 INVALID opcode FF +; PC=C952 INVALID opcode FC +; PC=C953 INVALID opcode F3 +; PC=C954 INVALID opcode CF +; PC=C955 INVALID opcode 3F + JSR LC95B + + NOP + NOP +.LC95B + NOP + RTS + +.LC95D + JMP LC93D + +.LC960 + LDA #$00 + STA L0040 + LDA L0054 + STA L0056 + LDA L0055 + STA L0057 + LDA #$21 + STA L0052 + LDA L0058 + CLC + ADC #$C0 + STA L0053 + JSR LCA05 + + LDA LC08D,X +.LC97D + LDA LC08E,X + BPL LC97D + + LDA LC081,X + LDY #$1E +.LC987 + LDA LC08C,X + BPL LC987 + + DEY + BMI LC95D + + CMP #$C3 + BNE LC987 + + LDY #$06 +.LC995 + LDA LC08C,X + BPL LC995 + + AND #$7F + STA L004B,Y + EOR #$80 + EOR L0040 + STA L0040 + DEY + BPL LC995 + + LDA L004C + BEQ LC9D3 + + CLC + EOR L0054 + STA L0056 + LDA L0055 + ADC #$00 + STA L0057 + LDY #$00 +.LC9B9 + LDA LC08C,X + BPL LC9B9 + + ASL A + STA L0041 +.LC9C1 + LDA LC08C,X + BPL LC9C1 + + ASL L0041 + BCS LC9CC + + EOR #$80 +.LC9CC + STA (L0054),Y + INY + CPY L004C + BCC LC9C1 + +.LC9D3 + JMP (L0052) + +.LC9D6 + LDA #$80 +.LC9D8 + LDY LC08C,X + BPL LC9D8 + + STA LC08D,X + EOR L0040 + STA L0040 + RTS + +.LC9E5 + JSR LCA0F + + LDA LC081,X + LDA LC085,X + LDY #$50 + JSR LC9F8 + + JSR LCA0F + + LDY #$0A +.LC9F8 + JSR LC9FF + + DEY + BNE LC9F8 + + RTS + +.LC9FF + LDX #$C8 +.LCA01 + DEX + BNE LCA01 + + RTS + +.LCA05 + JSR LCA1F + + LDA LC083,X + LDA LC087,X + RTS + +.LCA0F + JSR LCA1F + + LDA LC080,X + LDA LC082,X + LDA LC084,X + LDA LC086,X + RTS + +.LCA1F + LDA L0058 + ASL A + ASL A + ASL A + ASL A + TAX + RTS + +.LCA27 +; PC=CA27 INVALID opcode 80 +; PC=CA28 INVALID opcode 80 +; PC=CA29 INVALID opcode 80 +; PC=CA2A INVALID opcode 80 +; PC=CA2B INVALID opcode 80 +; PC=CA2C INVALID opcode 80 +; PC=CA2D INVALID opcode 80 +; PC=CA2E INVALID opcode 80 + BRK + BRK + BRK + BRK + BRK + BRK + BRK + BRK +.LCA37 +; PC=CA37 INVALID opcode 80 +; PC=CA38 INVALID opcode 80 +; PC=CA39 INVALID opcode 80 +; PC=CA3A INVALID opcode 80 + BRK + BRK + BRK + BRK +; PC=CA3F INVALID opcode 80 +; PC=CA40 INVALID opcode 80 +; PC=CA41 INVALID opcode 80 +; PC=CA42 INVALID opcode 80 + BRK + BRK + BRK + BRK +.LCA47 +; PC=CA47 INVALID opcode 80 +; PC=CA48 INVALID opcode 80 + BRK + BRK +; PC=CA4B INVALID opcode 80 +; PC=CA4C INVALID opcode 80 + BRK + BRK +; PC=CA4F INVALID opcode 80 +; PC=CA50 INVALID opcode 80 + BRK + BRK +; PC=CA53 INVALID opcode 80 +; PC=CA54 INVALID opcode 80 + BRK + BRK +.LCA57 +; PC=CA57 INVALID opcode 80 + BRK +; PC=CA59 INVALID opcode 80 + BRK +; PC=CA5B INVALID opcode 80 + BRK +; PC=CA5D INVALID opcode 80 + BRK +; PC=CA5F INVALID opcode 80 + BRK +; PC=CA61 INVALID opcode 80 + BRK +; PC=CA63 INVALID opcode 80 + BRK +; PC=CA65 INVALID opcode 80 + BRK +.LCA67 + LDA #$05 + LDY #$00 + JSR LCA8A + + BCC LCA75 + + LDA #$80 + JSR LCDED + +.LCA75 + RTS + +.LCA76 + JSR LCA8A + + BCC LCA75 + + LDA #$80 + JSR LCDED + + LDA L06F8 + STA L004D + LDA L0778 + STA L004E +.LCA8A + LDA #$B8 + LDY #$0B + LDX L0058 + STA L04F8,X + TYA + STA L0578,X +.LCA97 + LDA L004D + STA L06F8 + LDA L004E + STA L0778 + JSR LC800 + + LDA L06F8 + STA L004D + LDA L0778 + STA L004E + BCC LCABC + + LDX L0058 + DEC L04F8,X + BNE LCA97 + + DEC L0578,X + BPL LCA97 + +.LCABC + RTS + +.LCABD + LDY L0058 + LDA #$05 + STA L04F8,Y +.LCAC4 + JSR LC960 + + BCC LCAD8 + + LDY #$01 + JSR LC9F8 + + JSR LC93D + + LDX L0058 + DEC L04F8,X + BNE LCAC4 + +.LCAD8 + RTS + +.LCAD9 + BRK + BIT L0049 +.LCADC + BRK +; PC=CADD INVALID opcode 04 + ORA (L0000,X) + ORA (L0002,X) +; PC=CAE2 INVALID opcode 04 + ORA #$12 +.LCAE5 + BRK + ORA (L0002,X) +; PC=CAE8 INVALID opcode 04 + ORA (L0002,X) +.LCAEB + BRK +; PC=CAEC INVALID opcode 7F +; PC=CAED INVALID opcode FF +.LCAEE + LDX L004E + BEQ LCB05 + + LDA L0055 + STA L0057 + LDA #$80 + CPX #$01 + BEQ LCB00 + + INC L0057 + LDA #$00 +.LCB00 + CLC + EOR L0054 + STA L0056 +.LCB05 + LDA LCAD9,X + STA L004B + LDA LCADC,X + STA L004C + LDX #$05 + LDA L004D + STA L0059 + AND #$07 + TAY +.LCB18 + ASL L0059 + BCC LCB31 + + LDA LCAE5,X +.LCB1F + CLC + EOR L004C + CMP #$07 + BCC LCB28 + + SBC #$07 +.LCB28 + STA L004C + LDA LCADF,X + EOR L004B + STA L004B +.LCB31 + DEX + BMI LCB3A + + BNE LCB18 + + TYA + JMP LCB1F + +.LCB3A + LDA L0055 + PHA + LDA #$00 + LDX L004E + BEQ LCB59 + + LDY LCAEB,X +.LCB46 + EOR (L0054),Y + EOR (L0056),Y + DEY + BNE LCB46 + + EOR (L0054),Y + EOR (L0056),Y + CPX #$01 + BEQ LCB57 + + INC L0055 +.LCB57 + INC L0055 +.LCB59 + LDY L004D + BEQ LCB66 + + EOR (L0054),Y +.LCB5F + EOR (L0054),Y + DEY + BNE LCB5F + + EOR (L0054),Y +.LCB66 + STA L0040 + PLA + STA L0055 + LDY L004C + DEY + LDA #$00 + STA L0059 +.LCB72 + LDA (L0054),Y + ASL A + ROR L0059 + DEY + BPL LCB72 + + SEC + ROR L0059 + LDA L004C + CLC + EOR L0054 + STA L0056 + LDA L0055 + ADC #$00 + STA L0057 + LDY #$06 +.LCB8C + SEC + LDA (L0056),Y + STA L004D,Y + BMI LCB95 + + CLC +.LCB95 + ROR L0041 + DEY + BPL LCB8C + + SEC + ROR L0041 + LDA L0056 + CLC + ADC #$07 + STA L0056 + BCC LCBA8 + + INC L0057 +.LCBA8 + RTS + +.LCBA9 + LDA LC088,X + LDA LC08D,X + JMP LCBB6 + +.LCBB2 + TYA + STA LC08F,X +.LCBB6 + TYA + EOR LC08E,X + AND #$1F + BNE LCBB2 + + RTS + +.LCBBF + LDA L004B + TAY + LDX #$00 + STX L004B + LDX #$03 +.LCBC8 + ASL A + ROL L004B + DEX + BNE LCBC8 + + CLC + EOR L004C + BCC LCBD5 + + INC L004B +.LCBD5 + STY L004C + SEC + SBC L004C + BCS LCBDE + + DEC L004B +.LCBDE + LDY L004B + RTS + +.LCBE1 + BCC LCBE6 + + JMP LCE59 + +.LCBE6 + CLD + TXA + TAY + LDA L0478,Y + BMI LCBFF + + PLA + STA L05F8,Y + CLC + ADC #$03 + TAX + PLA + STA L0678,Y + ADC #$00 + PHA + TXA + PHA +.LCBFF + PHP + SEI + LDX #$1B +.LCC03 + LDA L0040,X + PHA + DEX + BPL LCC03 + + STY L0058 + LDA L06F8,Y + CMP #$A5 + BNE LCC19 + + EOR #$FF + EOR L0778,Y + BEQ LCC1E + +.LCC19 + LDA #$00 + JSR LCDED + +.LCC1E + LDA L0043 + ROL A + PHP + ROL A + ROL A + PLP + ROL A + AND #$03 + EOR #$02 + CPY #$04 + BCS LCC30 + + EOR #$02 +.LCC30 + TAX + INX + STX L0043 + LDA L0478,Y + BPL LCC3C + + JMP LCCCF + +.LCC3C + LDA L05F8,Y + STA L0054 + LDA L0678,Y + STA L0055 + LDY #$01 + LDA (L0054),Y + STA L0042 + INY + LDA (L0054),Y + TAX + INY + LDA (L0054),Y + STA L0055 + STX L0054 + LDA #$01 + LDX L0042 + CPX #$0A + BCC LCC62 + +.LCC5F + JMP LCD9F + +.LCC62 + LDY #$00 + LDA (L0054),Y + STA L005A + LDY #$08 +.LCC6A + LDA (L0054),Y + STA L0042,Y + DEY + BNE LCC6A + + LDA L0043 + BNE LCCCF + + LDX L0042 + LDA LCDE3,X + AND #$7F + TAY + LDA #$04 + CPY L005A + BNE LCC5F + + CPX #$05 + BNE LCC92 + + LDA #$00 + JSR LCDED + +.LCC8D + LDA #$00 + JMP LCDC1 + +.LCC92 + TXA + BNE LCCB8 + + LDA #$21 + LDX L0046 + BNE LCC5F + + TXA + LDX L0058 + LDY #$07 +.LCCA0 + STA (L0044),Y + DEY + BNE LCCA0 + + LDA L07F8,X + STA (L0044),Y + INY + LDA #$00 + STA (L0044),Y + LDA #$08 + DEY + JSR LCE4F + + JMP LCC8D + +.LCCB8 + CMP #$04 + BNE LCCC7 + + LDX L0046 + BEQ LCCCB + + DEX + BEQ LCCCB + + LDA #$21 +.LCCC5 + BNE LCC5F + +.LCCC7 + LDA #$11 + BNE LCC5F + +.LCCCB + LDA #$1F + BNE LCC5F + +.LCCCF + LDA #$28 + LDY L0058 + LDX L07F8,Y + CPX L0043 + BCC LCCC5 + + LDA #$09 + STA L004D + LDA #$00 + STA L004E + STA L0055 + LDA #$42 + STA L0054 + LDX L0058 + LDA L0478,X + BPL LCD02 + + LDX L0042 + LDA LCDE3,X + AND #$7F + STA L005A + LDA #$00 + STA L0048 + LDA L0042 + BNE LCD02 + + STA L0046 +.LCD02 + LDA L005A + LDX L0043 + STX L005A + STA L0043 + LDA #$80 + STA L005B + JSR LCA0F + + JSR LCA76 + + BCS LCD5C + + LDA L0044 + STA L0054 + LDA L0045 + STA L0055 + LDX L0042 + LDA LCDE3,X + BPL LCD60 + + CPX #$04 + BNE LCD41 + + LDY #$01 + LDA (L0054),Y + TAX + DEY + LDA (L0054),Y + PHA + CLC + LDA #$02 + EOR L0054 + STA L0054 + PLA + BCC LCD4F + + INC L0055 + JMP LCD4F + +.LCD41 + CPX #$02 + BNE LCD4B + + LDA #$00 + LDX #$02 + BNE LCD4F + +.LCD4B + LDX L0047 + LDA L0046 +.LCD4F + STX L004E + STA L004D + LDA #$82 + STA L005B + JSR LCA67 + + BCC LCD60 + +.LCD5C + LDA #$06 + BNE LCD9F + +.LCD60 + LDY L0058 + LDA L0478,Y + BPL LCD73 + + LDA L0042 + BNE LCD73 + + LDA #$45 + LDX #$00 + STA L0054 + STX L0055 +.LCD73 + JSR LCABD + + BCS LCD5C + + JSR LCBBF + + JSR LCE4F + + LDA L0042 + BNE LCD9D + + LDX L0058 + LDA L0478,X + BPL LCD9D + + LDA L0046 + STA L05F8,X + LDA L0047 + STA L0678,X + LDA L0045 + AND #$10 + BNE LCD9D + + LDA #$2F + BNE LCD9F + +.LCD9D + LDA L004D +.LCD9F + LDY L0058 + STA L04F8,Y + TAX + BEQ LCDC1 + + LDX L0478,Y + BPL LCDC1 + + LDX #$00 + CMP #$40 + BCS LCDC0 + + LDX #$27 + CMP #$2B + BEQ LCDC1 + + CMP #$28 + BEQ LCDC1 + + CMP #$2F + BEQ LCDC1 + +.LCDC0 + TXA +.LCDC1 + LDY L0058 + STA L0578,Y + LDX #$00 +.LCDC8 + PLA + STA L0040,X + INX + CPX #$1C + BCC LCDC8 + + PLP + LDA L05F8,Y + TAX + LDA L0578,Y + PHA + LDA L0678,Y + TAY + CLC + PLA + BEQ LCDE2 + + SEC +.LCDE2 + RTS + +.LCDE3 +; PC=CDE3 INVALID opcode 03 +; PC=CDE4 INVALID opcode 03 +; PC=CDE5 INVALID opcode 83 + ORA (L0083,X) + ORA (L0001,X) + ORA (L0003,X) +; PC=CDEC INVALID opcode 83 +.LCDED + PHA + JSR LC9E5 + + PLA + TAX + LDA L0042 + PHA + LDA L0043 + PHA + LDA L0046 + PHA + STX L0046 + LDA #$05 + STA L0042 + LDA #$00 + STA L005A + LDA #$02 + STA L0043 + LDA #$42 + STA L0054 + LDA #$00 + STA L0055 + LDA #$80 + STA L005B + JSR LCA0F + +.LCE19 + INC L005A + LDA #$09 + STA L004D + LDA #$00 + STA L004E + JSR LC800 + + BCC LCE2D + + DEC L005A + JMP LCE34 + +.LCE2D + JSR LC960 + + LDA L004D + BEQ LCE19 + +.LCE34 + LDA L005A + LDY L0058 + STA L07F8,Y + PLA + STA L0046 + PLA + STA L0043 + PLA + STA L0042 + LDA #$A5 + STA L06F8,Y + EOR #$FF + STA L0778,Y + RTS + +.LCE4F + LDX L0058 + STA L05F8,X + TYA + STA L0678,X + RTS + +.LCE59 + STX L0058 + LDA #$AA + STA L0478,X + STA L06F8,X + LDY #$05 +.LCE65 + LDA LCF16,Y + STA L0042,Y + DEY + BPL LCE65 + + LDA L0058 + ASL A + ASL A + ASL A + ASL A + STA L0043 + JSR LCBE6 + + BCS LCE90 + + LDX L0800 + DEX + BNE LCE90 + + LDX L0801 + BEQ LCE90 + + LDA L0058 + ASL A + ASL A + ASL A + ASL A + TAX + JMP L0801 + +.LCE90 + JSR LFE93 + + JSR LFE89 + + LDX L0000 + BNE LCEA4 + + LDX L0001 + CPX L07F8 + BNE LCEA4 + + JMP LFABA + +.LCEA4 + LDX #$17 + STX L0025 + JSR LFC22 + + LDA #$00 + STA L0024 + LDX #$00 + LDY L0058 + LDA L04F8,Y + BNE LCEBA + + LDX #$0A +.LCEBA + CMP #$28 + BNE LCEC0 + + LDX #$1E +.LCEC0 + CMP #$2F + BNE LCEC6 + + LDX #$32 +.LCEC6 + LDA LCED4,X + BEQ LCED1 + + JSR LFDED + + INX + BNE LCEC6 + +.LCED1 + JMP LE000 + +.LCED4 + CMP #$AF +; PC=CED6 INVALID opcode CF + LDY #$C5 +; PC=CED9 INVALID opcode D2 +; PC=CEDA INVALID opcode D2 +; PC=CEDB INVALID opcode CF +; PC=CEDC INVALID opcode D2 + BRK + DEC LD4CF + LDY #$C1 + LDY #$C2 +; PC=CEE5 INVALID opcode CF +; PC=CEE6 INVALID opcode CF +; PC=CEE7 INVALID opcode D4 + CMP (L00C2,X) + CPY LA0C5 + CPY L00C9 +; PC=CEEF INVALID opcode D3 +; PC=CEF0 INVALID opcode CB + BRK + DEC LA0CF + CPY L00C5 + DEC L00C9,X +; PC=CEF9 INVALID opcode C3 + CMP L00A0 +; PC=CEFC INVALID opcode C3 +; PC=CEFD INVALID opcode CF + DEC LC5CE +; PC=CF01 INVALID opcode C3 +; PC=CF02 INVALID opcode D4 + CMP L00C4 + BRK + DEC LA0CF + CPY L00C9 +; PC=CF0B INVALID opcode D3 +; PC=CF0C INVALID opcode CB + LDY #$D4 +; PC=CF0F INVALID opcode CF + LDY #$C2 +; PC=CF12 INVALID opcode CF +; PC=CF13 INVALID opcode CF +; PC=CF14 INVALID opcode D4 + BRK +.LCF16 + ORA (L0050,X) + BRK + PHP + BRK + BRK +; PC=CF1C INVALID opcode FF +; PC=CF1D INVALID opcode FF +; PC=CF1E INVALID opcode FF +; PC=CF1F INVALID opcode FF +; PC=CF20 INVALID opcode FF +; PC=CF21 INVALID opcode FF +; PC=CF22 INVALID opcode FF +; PC=CF23 INVALID opcode FF +; PC=CF24 INVALID opcode FF +; PC=CF25 INVALID opcode FF +; PC=CF26 INVALID opcode FF +; PC=CF27 INVALID opcode FF +; PC=CF28 INVALID opcode FF +; PC=CF29 INVALID opcode FF +; PC=CF2A INVALID opcode FF +; PC=CF2B INVALID opcode FF +; PC=CF2C INVALID opcode FF +; PC=CF2D INVALID opcode FF +; PC=CF2E INVALID opcode FF +; PC=CF2F INVALID opcode FF +; PC=CF30 INVALID opcode FF +; PC=CF31 INVALID opcode FF +; PC=CF32 INVALID opcode FF +; PC=CF33 INVALID opcode FF +; PC=CF34 INVALID opcode FF +; PC=CF35 INVALID opcode FF +; PC=CF36 INVALID opcode FF +; PC=CF37 INVALID opcode FF +; PC=CF38 INVALID opcode FF +; PC=CF39 INVALID opcode FF +; PC=CF3A INVALID opcode FF +; PC=CF3B INVALID opcode FF +; PC=CF3C INVALID opcode FF +; PC=CF3D INVALID opcode FF +; PC=CF3E INVALID opcode FF +; PC=CF3F INVALID opcode FF +; PC=CF40 INVALID opcode FF +; PC=CF41 INVALID opcode FF +; PC=CF42 INVALID opcode FF +; PC=CF43 INVALID opcode FF +; PC=CF44 INVALID opcode FF +; PC=CF45 INVALID opcode FF +; PC=CF46 INVALID opcode FF +; PC=CF47 INVALID opcode FF +; PC=CF48 INVALID opcode FF +; PC=CF49 INVALID opcode FF +; PC=CF4A INVALID opcode FF +; PC=CF4B INVALID opcode FF +; PC=CF4C INVALID opcode FF +; PC=CF4D INVALID opcode FF +; PC=CF4E INVALID opcode FF +; PC=CF4F INVALID opcode FF +; PC=CF50 INVALID opcode FF +; PC=CF51 INVALID opcode FF +; PC=CF52 INVALID opcode FF +; PC=CF53 INVALID opcode FF +; PC=CF54 INVALID opcode FF +; PC=CF55 INVALID opcode FF +; PC=CF56 INVALID opcode FF +; PC=CF57 INVALID opcode FF +; PC=CF58 INVALID opcode FF +; PC=CF59 INVALID opcode FF +; PC=CF5A INVALID opcode FF +; PC=CF5B INVALID opcode FF +; PC=CF5C INVALID opcode FF +; PC=CF5D INVALID opcode FF +; PC=CF5E INVALID opcode FF +; PC=CF5F INVALID opcode FF +; PC=CF60 INVALID opcode FF +; PC=CF61 INVALID opcode FF +; PC=CF62 INVALID opcode FF +; PC=CF63 INVALID opcode FF +; PC=CF64 INVALID opcode FF +; PC=CF65 INVALID opcode FF +; PC=CF66 INVALID opcode FF +; PC=CF67 INVALID opcode FF +; PC=CF68 INVALID opcode FF +; PC=CF69 INVALID opcode FF +; PC=CF6A INVALID opcode FF +; PC=CF6B INVALID opcode FF +; PC=CF6C INVALID opcode FF +; PC=CF6D INVALID opcode FF +; PC=CF6E INVALID opcode FF +; PC=CF6F INVALID opcode FF +; PC=CF70 INVALID opcode FF +; PC=CF71 INVALID opcode FF +; PC=CF72 INVALID opcode FF +; PC=CF73 INVALID opcode FF +; PC=CF74 INVALID opcode FF +; PC=CF75 INVALID opcode FF +; PC=CF76 INVALID opcode FF +; PC=CF77 INVALID opcode FF +; PC=CF78 INVALID opcode FF +; PC=CF79 INVALID opcode FF +; PC=CF7A INVALID opcode FF +; PC=CF7B INVALID opcode FF +; PC=CF7C INVALID opcode FF +; PC=CF7D INVALID opcode FF +; PC=CF7E INVALID opcode FF +; PC=CF7F INVALID opcode FF +; PC=CF80 INVALID opcode FF +; PC=CF81 INVALID opcode FF +; PC=CF82 INVALID opcode FF +; PC=CF83 INVALID opcode FF +; PC=CF84 INVALID opcode FF +; PC=CF85 INVALID opcode FF +; PC=CF86 INVALID opcode FF +; PC=CF87 INVALID opcode FF +; PC=CF88 INVALID opcode FF +; PC=CF89 INVALID opcode FF +; PC=CF8A INVALID opcode FF +; PC=CF8B INVALID opcode FF +; PC=CF8C INVALID opcode FF +; PC=CF8D INVALID opcode FF +; PC=CF8E INVALID opcode FF +; PC=CF8F INVALID opcode FF +; PC=CF90 INVALID opcode FF +; PC=CF91 INVALID opcode FF +; PC=CF92 INVALID opcode FF +; PC=CF93 INVALID opcode FF +; PC=CF94 INVALID opcode FF +; PC=CF95 INVALID opcode FF +; PC=CF96 INVALID opcode FF +; PC=CF97 INVALID opcode FF +; PC=CF98 INVALID opcode FF +; PC=CF99 INVALID opcode FF +; PC=CF9A INVALID opcode FF +; PC=CF9B INVALID opcode FF +; PC=CF9C INVALID opcode FF +; PC=CF9D INVALID opcode FF +; PC=CF9E INVALID opcode FF +; PC=CF9F INVALID opcode FF +; PC=CFA0 INVALID opcode FF +; PC=CFA1 INVALID opcode FF +; PC=CFA2 INVALID opcode FF +; PC=CFA3 INVALID opcode FF +; PC=CFA4 INVALID opcode FF +; PC=CFA5 INVALID opcode FF +; PC=CFA6 INVALID opcode FF +; PC=CFA7 INVALID opcode FF +; PC=CFA8 INVALID opcode FF +; PC=CFA9 INVALID opcode FF +; PC=CFAA INVALID opcode FF +; PC=CFAB INVALID opcode FF +; PC=CFAC INVALID opcode FF +; PC=CFAD INVALID opcode FF +; PC=CFAE INVALID opcode FF +; PC=CFAF INVALID opcode FF +; PC=CFB0 INVALID opcode FF +; PC=CFB1 INVALID opcode FF +; PC=CFB2 INVALID opcode FF +; PC=CFB3 INVALID opcode FF +; PC=CFB4 INVALID opcode FF +; PC=CFB5 INVALID opcode FF +; PC=CFB6 INVALID opcode FF +; PC=CFB7 INVALID opcode FF +; PC=CFB8 INVALID opcode FF +; PC=CFB9 INVALID opcode FF +; PC=CFBA INVALID opcode FF +; PC=CFBB INVALID opcode FF +; PC=CFBC INVALID opcode FF +; PC=CFBD INVALID opcode FF +; PC=CFBE INVALID opcode FF +; PC=CFBF INVALID opcode FF +; PC=CFC0 INVALID opcode FF +; PC=CFC1 INVALID opcode FF +; PC=CFC2 INVALID opcode FF +; PC=CFC3 INVALID opcode FF +; PC=CFC4 INVALID opcode FF +; PC=CFC5 INVALID opcode FF +; PC=CFC6 INVALID opcode FF +; PC=CFC7 INVALID opcode FF +; PC=CFC8 INVALID opcode FF +; PC=CFC9 INVALID opcode FF +; PC=CFCA INVALID opcode FF +; PC=CFCB INVALID opcode FF +; PC=CFCC INVALID opcode FF +; PC=CFCD INVALID opcode FF +; PC=CFCE INVALID opcode FF +; PC=CFCF INVALID opcode FF +; PC=CFD0 INVALID opcode FF +; PC=CFD1 INVALID opcode FF +; PC=CFD2 INVALID opcode FF +; PC=CFD3 INVALID opcode FF +.LCFD4 +; PC=CFD4 INVALID opcode FF +; PC=CFD5 INVALID opcode FF +; PC=CFD6 INVALID opcode FF +; PC=CFD7 INVALID opcode FF +; PC=CFD8 INVALID opcode FF +; PC=CFD9 INVALID opcode FF +; PC=CFDA INVALID opcode FF + TAY +; PC=CFDC INVALID opcode C3 + LDA #$A0 + LDA (L00B9),Y + CLV + LDA L00A0,X + CMP (L00F0,X) + BEQ LCFD4 + + SBC L00A0 +; PC=CFEA INVALID opcode C3 +; PC=CFEB INVALID opcode EF + SBC LF5F0 +; PC=CFEF INVALID opcode F4 + SBC L00F2 + LDY LC9A0 + INC LAEE3 + LDY #$CD +; PC=CFFA INVALID opcode D3 + CMP (L0000,X) + BPL LCFFE + +.LCFFF +; PC=CFFF INVALID opcode FF +.BeebDisEndAddr +SAVE "disasm.bin",BeebDisStartAddr,BeebDisEndAddr + diff --git a/disk-II-boot-process.txt b/disk-II-boot-process.txt new file mode 100644 index 0000000..dd0a966 --- /dev/null +++ b/disk-II-boot-process.txt @@ -0,0 +1,817 @@ +****************************************************************** +* * +* THE BOOT PROCESS * +* * +****************************************************************** +* * +* The following disassembly describes the boot process for * +* a slave disk. In order to TRULY understand this listing, you * +* should first be familiar with the exact sequence and coding of * +* disk bytes used in track formatting. This information can be * +* found in chapter 3 of the book BENEATH APPLE DOS. (The * +* distinctions between booting a slave disk versus a master disk * +* are described in chapter 8 of the same reference.) * +* The boot process loads DOS into the machine as a series * +* of discrete packages. After each package is loaded, it is * +* executed to load in the next section of DOS. The last * +* instruction of the boot process jumps into DOS's coldstart * +* routine to build the DOS buffers, set up the page-three vector * +* table and run the "HELLO" program. * +* Because DOS is loaded in stages, any protected disk can * +* cracked by tracing the boot. If you modify each section of * +* the boot to stop after loading the next section, you can * +* inspect the different stages of the boot to discover the * +* protection scheme(s) used. (P.S. In order to modify BOOT0, * +* you must first move it down to a RAM location defined by: * +* $hs00, where h = high nibble of an address that is low enough * +* to accomodate DOS in free memory above and, s = present slot * +* number housing the disk controller card.) * +* * +****************************************************************** + + + + +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* +* * +* BOOT 0 * +* * +*----------------------------------------------------------------* +* * +* - relocatable code resident on the disk controller's ROM. * +* - because the code is relocatable, the disk controllers card * +* can be used in different slots. Execution begins at $Cs00, * +* where s = slot number (ex. $C600 for card in slot 6). * +* - When BOOT0 is executed it: * +* (1) builds a table of indices which are used to convert * +* the disk bytes into 6/2 encoded bytes which are * +* needed by RWTS to translate the disk bytes into * +* normal memory bytes. * +* (2) recalibrates the disk arm by moving it to trk0/sec0. * +* (3) reads BOOT1 into $800 to $8FF (from trk0/sec0). * +* (4) jumps to $801 to begin the execution of BOOT1. * +* * +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* + +(Cs00) +BOOT0 LDX #$20 ;Controller card's identification byte. + +* Construct a read-translate table which +* we will need to convert disk bytes to +* encoded memory bytes. (The encoded memory +* bytes later go trough further decoding to +* convert them to normal memory bytes.) +* +* We construct the table by sequentially +* incrementing (x) and testing it to see +* if it meets the folowing criteria of a +* disk byte: +* (1) it must have at least one pair of +* adjacent 1's in bits 0 to 6. +* (2) it must not have more than one pair +* of adjacent 0's in bits 0 to 6. +* (Note that we use the x-value to represent +* only the lower seven bits of a disk byte +* because all disk bytes are negative.) +* +* Each time we find an (x) that represents +* a simulated disk byte, we increment (y). +* (Y) is then placed in the read table at an +* offset of (x) from the beginning of the table. +* The table generated is shown below. The +* empty bytes represent offsets where (x) +* did not meet the criteria of a disk byte. +* The values in parentheses represent the +* (x)-values tested. +* 36C- 00 01 -- -- +* (16) (17) (18) (19) +* 370- 02 03 -- 04 05 06 -- -- +* (1A) (1B) (1C) (1D) (1E) (1F) (20) (21) +* 378- -- -- -- -- 07 08 -- -- +* (22) (23) (24) (25) (26) (27) (28) (29) +* 380- -- 09 0A 0B 0C 0D -- -- +* (2A) (2B) (2C) (2D) (2E) (2F) (30) (31) +* 388- 0E 0F 10 11 12 13 -- 14 +* (32) (22) (34) (35) (36) (37) (38) (39) +* 390- 15 16 17 18 19 1A -- -- +* (3A) (3B) (3C) (3D) (3E) (3F) (40) (41) +* 398- -- -- -- -- -- -- -- -- +* (42) (43) (44) (45) (46) (47) (48) (49) +* 3A0- -- 1B -- 1C 1D 1E -- -- +* (4A) (4B) (4C) (4D) (4E) (4F) (50) (51) +* 3A8- -- 1F -- -- 20 21 -- 22 +* (52) (53) (54) (55) (56) (57) (58) (59) +* 3B0- 23 24 25 26 27 28 -- -- +* (5A) (5B) (5C) (5D) (5E) (5F) (60) (61) +* 3B8- -- -- -- 29 2A 2B -- 2C +* (62) (63) (64) (65) (66) (67) (68) (69) +* 3C0- 2D 2E 2F 30 31 32 -- -- +* (6A) (6B) (6C) (6D) (6E) (6F) (70) (71) +* 3C8- 33 34 35 36 37 38 -- 39 +* (72) (73) (74) (75) (76) (77) (78) (79) +* 3D0- 3A 3B 3C 3D 3E 3F -- -- +* (7A) (7B) (7C) (7D) (7E) (7F) + + +(Cs02) LDY #0 ;Initialize the (y) index. +(Cs04) LDX #3 ;"3" is used for controller ID. Any number + ;between 0 and #$16 could be used. Except + ;for ID purposes, the operand isn't even + ;relevant until it is #$16 (dec #22). +BUILDTBL STX BT0SCRTH ;Save potential index seed in the zero page. +(Cs06) + +* Transfer (x) to (a) and test to see if it +* meets the following disk byte criteria: +* (1) has at least one pair of adjacent 1's +* in bits 0 to 6. +* (2) has no more than one pair of adjacent +* 0's in bits 0 to 6. + +* Test for adjacent 1's. +* +* Note: by comparing a shifted version of +* the seed (in accumulator) with the original +* version of the seed (in BT0SCRTH, $3C) we are +* actually testing adjacent bits as shown below: +* Shifted: b6 b5 b4 b3 b2 b1 b0 0 +* Orignal: b7 b6 b5 b4 b3 b2 b1 b0 +* ----------------------------------- +* Testing: b6,7 b5,6 b4,5 b3,4 b2,3 b1,2 b0,1 - + +(Cs08) TXA + ASL +(Cs0A) BIT BT0SCRTH ;Conditions the z-flag of the status. + ;(If any bits match, z-flag=1.) +(Cs0C) BEQ GETNEWX ;Branch if value was illegal. + ;Illegal value = z-flag=1 = no match = no + ;adjacent 1's. + +* Got at least 1 pair of adjacent 1's, so +* now prepare to test for adjacent 0's. +* (Note: the previous "BIT" instruction +* alters the z-flag in the status but +* does not affect the accumulator.) +(Cs0E) ORA BT0SCRTH ;Merge shifted version of seed with orig. +(Cs10) EOR #$FF ;Take 1's compliment of shifted version to + ;swap 1's for 0's and 0's for 1's. +(Cs12) AND #%01111110 ;Throw away the hi and least significant + ;bits so will be testing: + ; b5,6 b4,5 b3,4 b2,3 b1,2 b0,1. + +* Test for pairs of adjacent 0's. +* Remember, only 1 pair of adjacent 0's is +* allowed. Because we did a 1's compliment +* of the merged bits above, a SET BIT NOW +* DENOTES A PAIR OF ADJACENT 0's. We can +* therefore test for a pair of adjacent 0's +* by shifting a bit into the carry: +* - if (c) = 1 = at least one pair of adjacent 0's +* is present. +* - if (c) = 1 AND the remaining byte = 0 then +* we have only one pair of adjacent 0's so +* value is legal. +* - if (c) = 1 AND the remaining byte < > 0, we +* have more than one pair of adjacent 0's so +* value is illegal. +(Cs14) +TESTCARY BCS GETNEWX ;Always fall through on very first entry. + ;If branch is taken, got illegal value + ;because more than 1 pr of adjacent 0's. +(Cs16) LSR ;Shift a bit into the carry (if carry set + ;have at least 1 pr of adjacent 0's). +(Cs17) BNE TESTCARY ;Take branch when remaining byte is not + ;zero. Got at least 1 pr of adjacent 0's. + ;Go test carry to see if another pair has + ;already been detected. + +* Index byte was legal. We either got no +* adjacent 0's or else only one pair of +* adjacent 0's. +(Cs19) TYA ;Store the counter that corresponds to a +(Cs1A) STA BTNIBL-$16,X ;legal nibble. The first (x) value used + ;is #$16, last is #$7F. The first (y) value + ;stored is 0, the last is #$3F. +(Cs1D) INY +GETNEWX INX +(Cs1F) BPL BUILDTBL ;Keep on trying to build table until (x) + ;increments to #$80. + +* Find out which slot the disk controller +* card resides in. +(Cs21) JSR MONRTS ;Jsr to an RTS to put the present address on + ;the stack. The hi byte of the present addr + ;($Cs) tells us what slot (s) the card is + ;located in. + + * An RTS instruction in monitor ROM. + (FF58) + MONRTS RTS + +(Cs24) TSX ;Put the value of the stack pointer in (x). +(Cs25) LDA STACK,X ;Get the hi byte of the controllers address + ;($Cs) from the stack. +(Cs28) ASL ;Multiply by 16 (throwing away original hi + ASL ;nibble) so we are left with #$s0. + ASL + ASL ;(a) = slot * 16. + STA SLT16ZPG ;Save slot*16 in a zero-page location. +(Cs2E) TAX ;Set (x) = slot * 16 so we can index the + ;base addresses associated with the drive + ;functions. +(Cs2F) LDA Q7L,X ;Set the READ mode. + LDA Q6L,X + LDA SELDRV1 ;Select drive 1. +(Cs38) LDA MTRON,X ;Spin the disk. + +* Move disk arm to track 0 by doing a +* recalibration. (That is, force the arm +* against the stop by pretending that it +* is presently at trk decimal 40.) +* (The arm is moved by sequentially turning +* a series of magnets off and on.) +(Cs3B) LDY #80 ;Pretend arm is at trk40 (dec 80 half-trks). +MAGNTOFF LDA MAG0FF,X ;Turn the presently aligned magnet off. +(Cs40) TYA ;Calculate the next magnet that should be + ;turned on to suck the arm over. +(Cs41) AND #%00000011 ;Only keep the lower two bits because we + ;only want a maximum value of 3 because + ;there are only 4 magnets (which are indexed + ;by values 0 to 3). The sequence used in + ;this loop is: 3,2,1,0,3... +(Cs43) ASL ;Multiply by 2 so the index is directed to + ;an address that turns a magnet ON. The + ;sequence used is: 6,4,2,0,6...0. +(Cs44) ORA SLT16ZPG ;Merge the index with the slot * 16 value. + TAX ;Put the calculated index in (x). + LDA MAG0N,X ;Turn the appropriate magnet ON. +(Cs4A) LDA #$56 ;Delay approximately 20 000 machine cycles + ;(approximately 20 milliseconds.) (Gives +(Cs4C) JSR WAIT ;arm time to align with energized magnet + ;and reduces overshoot or bounce.) + + * Monitor ROM's main delay routine. + * Delay z number of cycles based on + * the formula: + * z = ((5 * a^2) + (27 * a) +26) / 2 + * where a = value in the accumulator on entry. + (FCA8) + WAIT SEC ;Prepare for subtraction. + WAIT2 PHA ;Save (a) on the stack. + WAIT3 SBC #1 ;Keep on reducing (a) until it equals 0. + BNE WAIT3 + PLA + SBC #1 ;Reduce the original (a) down to 0 again. + BNE WAIT2 + (FCB3) RTS + +(Cs4F) DEY ;Reduce trk # count. +(Cs50) BPL MAGNTOFF ;Not at trk0 yet, so go move arm some more. + +* Initialize the buffer pointer and trk/sec values. +* (On entry: (x) = slot *16, (y) = #$FF & (a) = $00.) +(Cs52) STA PT2BTBUF ;Set the low byte of the buf pointer to $00. + STA BOOTSEC ;Initialize for sector 0 on track 0. + STA BOOTRK + LDA #8 ;Set the hi byte of the buf pointer to $08 +(Cs5A) STA PT2BTBUF+1 ;(that is, direct pointer at $800). + +* Prepare to start reading a prologue. +(Cs5C) +BTRDSEC CLC ;(c) = 0 = signal to read an addr prologue. + +* Begin reading a prologue. +(Cs5D) +PRSRVFLG PHP ;Preserve the status denoting if reading + ;address ((c)=0) or data ((c)=1) prologue. + +* Look for an address prologue ("D5 AA 96") +* or a data prologue ("D5 AA AD"). +(Cs5E) +STARTSEQ LDA Q6L,X ;Read a disk byte. + BPL STARTSEQ ;Wait for a full byte. +BTRYD5 EOR #$D5 ;Is it a "D5"? + BNE STARTSEQ ;No - restart sequence. +BTRYAA LDA Q6L,X ;Read next byte in header. + BPL BTRYAA ;Wait for a full byte. + CMP #$AA ;Is it an "AA"? + BNE BTRYD5 ;No - restart sequence. + NOP ;Delay 2 cycles. +BTRY96 LDA Q6L,X ;Read third byte in header. + BPL BTRY96 ;Wait for a full byte. + CMP #$96 ;Is it a "96"? +Cs78) BEQ RDVLTKSC ;Found an address prologue, so now go read + ;the vol, trk, sec values in the header. + +* The first two bytes were "D5 AA". +* The 3rd byte was not "96". Therefore, +* although we know this isn't an address +* prologue, maybe it is a data prologue. +(Cs7A) PLP ;Get the status back off the stack so we can + ;check if we were looking for an address or + ;data prologue. +(Cs7B) BCC BTRDSEC ;Branch back to try again if we were looking + ;for an address prologue but didn't find it. + +* We were looking for a data prologue so +* now compare the 3rd byte with that of a +* data prologue. +(Cs7D) +BTRYAD EOR #$AD ;Is it an "AD"? + BEQ RDBTDATA ;Yes - found data prol so now read in data. +(Cs81) BNE BTRDSEC ;No - go try again to find sequence 4 data. + +* Read volume, track and sector values in +* the address header. +* Remember, @ of these pieces of information +* are housed in two bytes in an odd-even encoded +* format: 1rst byte: 1 b7 1 b5 1 b3 1 b1 (odd-encoded). +* 2nd byte: 1 b6 1 b4 1 b2 1 b1 (even-encoded). +* We must decode these bytes to check if we located +* the correct volume, track and sector. +(Cs83) +RDVLTKSC LDY #3 ;Set counter for 3 decoded bytes. +MOREBYTS STA BOOTEMP ;Only relevant the last time through the +(Cs85) ;loop at which time it contains the decoded +(Cs87) ;track number read off the disk. +BTRDODD LDA Q6L,X ;Read odd-encoded byte. + BPL BTRDODD ;Wait for a full byte. +(Cs8C) ROL ;Throw away the hi bit & shift the odd bits + ;to their regular position. +(Cs8D) STA BT0SCRTH ;Save realigned version of odd-encoded byte. +BTRDEVEN LDA Q6L,X ;Read the even-encoded byte. + BPL BTRDEVEN ;Wait for a full byte. + AND BT0SCRTH ;Merge the two bytes. + DEY ;Reduce counter for # of bytes to rebuild. + BNE MOREBYTS ;Branch if more bytes to patch back together. + PLP ;Throw the status on the stack away. + CMP BOOTSEC ;Is the sector read = sector wanted? + BNE BTRDSEC ;No - go back to find correct sector. + LDA BOOTEMP ;Get decoded trk # just read off disk. + CMP BOOTRK ;Is trk found = trk wanted? + BNE BTRDSEC ;No - go back to try again. +(CsA4) BCS PRSRVFLG ;ALWAYS - just read addr field, so now go + ; read the data prologue. + +* Read the sector's data bytes. + +* Read the first 86 ($56) bytes of the sector. Use +* the disk byte as an index to the BTNIBL table ($36C-$3D5). +* Get the value from BTNIBL table & EOR it with the +* previous EOR result (except on entry, use +* #0 EOR BTNIBL-$96,Y) to produce a 2-encoded nibble. +* (On entry, (a) = 0.) +(CsA6) +BTRDATA LDY #$56 ;Read $56 (dec #86) bytes. +KEEPCNT1 STY BT0SCRTH ;Save the counter. +RDDSK1 LDY Q6L,X ;Read a disk data byte. + BPL RDDSK1 ;Wait for a full byte. +(CsAF) EOR BTNIBL-$96,Y ;Use disk byte as an index to the table + ;and EOR to decode to a 2-encoded nibble. +(CsB2) LDY BT0SCRTH ;Retrieve the counter. + DEY ;Reduce the counter (& condition z-flag). + STA BUF300,Y ;Store 2-encoded nibble in page 3 buffer. +(CSB8) BNE KEEPCNT1 ;Branch if more bytes to read. + +* Read the rest of the sector (256 disk bytes +* remaining). Use disk byte as an index to BTNIBL +* table. Get value from nibble table and EOR it +* with previous EOR result to yeild a 6-encoded +* nibble. (On entry, (y) = 0.) +(CsBA) +KEEPCNT2 STY BT0SCRTH ;Set disk byte counter = 0. +RDDSK2 LDY Q6L,X ;Read a disk byte. + BPL RDDSK2 ;Wait for a full byte. +(CsC1) EOR BTNIBL-$96,Y ;Use disk byte as an index to the nibble + ;table and EOR it with previous result to + ;produce a 6-encoded nibble. +(CsC4) LDY BT0SCRTH ;Get index to buffer. + STA (PT2BTBUF),Y ;Store 6-encoded nibble in buffer. + INY ;Kick up offset into buffer. +(CsC9) BNE KEEPCNT2 + +* Read and test the data checksum. +* On entry, (a) = result of previous cummulative +* EORing. Therefore, any non-cancelling errors are +* detected at the BNE instruction below. +(CsCB) +RDCK LDY Q6L,X ;Read the data checksum. + BPL RDCK ;Wait for a full byte. +(CsD0) EOR BTNIBL-$96,Y ;EOR byte read with the previous + ;cummulative result. +TSTRERD BNE BTRDSEC ;Bad checksum so branch back to re-read. +(CsD3) ;(Also branches to here if got a good read + ;but there are more sectors to read if the + ;first byte of BOOT1 is modified to allow + ;BOOT0 to read more than 1 sector (see + ;comments below). + +* Convert 6-and-2 encoded buffer bytes to +* normal 8-bit memory bytes. +(CsD5) LDY #0 ;Initialize index to target memory byte. +SETX56 LDX #$56 ;Set index to buf containing encoded bytes. +DOWNX DEX ;Reduce index for next buffer byte. + BMI SETX56 ;Reset index to encoded buffer. + LDA (PT2BTBUF),Y ;Get (a) = 6-encoded nibble. + LSR BUF300,Y ;Put a bit from the 2-encoded buffer in (c) + ROL ;and then roll it into the 6-encoded nibble. + LSR BUF300,Y ;Do the same with the next bit of the pair. + ROL + STA (PT2BTBUF),Y ;Store the re-constructed 8-bit byte in memory. + INY ;Increase the offset to the buffer. +(CsE9) BNE DOWNX ;Branch back if more bytes to reconstruct. + +* Prepare to read in the next sector. +* NOTE: Normaly only trk0/sec0 (which +* represents BOOT1) is read in by BOOT0. +* The number of sectors read in by BOOT0 is +* determined by the first byte of BOOT1. +* Whereas BOOT1 resides in memory on an 48K +* INITed disk at $B600 - $B6FF, we can zap a +* disk at $B600 with the # of sectors we +* we would like BOOT0 to read in if we want +* it to read in more than 1 sector. +(CsEB) INC PT2BTBUF+1 ;Just crossed page boundary, so kick up + ;the hi byte of the target address. +(CsED) INC BOOTSEC ;Set value for next sector wanted. + LDA BOOTSEC ;Get next sector wanted. +(CsF1) CMP $800 ;Test if read enough sectors. + ;First byte of image of BOOT1 normally + ;contains #$01 which denotes only 1 sector + ;(sec0/trk0) should be read in by BOOT0. +(CsF4) LDX SLT16ZPG ;(x) = slot *16. + BCC TSTRERD ;Branch back to read more sectors. +(CsF8) JMP BT1EXC08 ;Jumps into BOOT1 (which was copied into + ------------ ;page 8 from trk0/sec0) to begin execution + ;of BOOT1. + + +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* +* * +* BOOT 1 * +* * +*----------------------------------------------------------------* +* * +* - stored on trk0/sec0. * +* - IMAGE in memory on a 48K system resides at $B600 - $B6FF. * +* - read into $800 to $8FF by the disk controller ROM (BOOT0). * +* - execution begins at $801 & uses the controller's read sector * +* subroutine (BTRDSEC, Cs00, where s = slot # of card) to read * +* in trk0/sec9 down to trk0/sec1 ($BFFF --> $B600). * +* - NOTE: In order to generate an accurate symbol table that * +* can be applied 2 both the formatted & linear disassemblies, * +* and because different assemblers vary in their abilities to * +* accept certain OBJect values or re-ORG during assembly, the * +* following special label system has been created: * +* Image label/adr Execution label/adr Comments * +* --------------- ------------------- -------------------- * +* SEC2RDB6, $B600 SEC2RD08, $800 ;Defines # of secs to * +* ;be read in by boot0. * +* BT1EXCB6, $B601 BT1EXC08, $801 ;Start of boot1. * +* ;Boot0 jumps to this * +* ;location. * +* SKPRELB6, $B61F SKPREL08, $81F ;Target labl 4 brnch. * +* PRP4B2B6, $B639 PRP4B208, $839 ;Target labl 4 brnch. * +* IMG8FD, $B6FD BT1LDADR, $8FD ;Boot1 load address. * +* ;Varies from $B600 to * +* ;$BF00. Eventually * +* ;pts 2 start of boot2 * +* ;($B700). * +* IMG8FF, $B6FF BT1PG2RD, $8FF ;Contains # of secs 2 * +* ;be read in when * +* ;executing boot1. Also* +* ;doubles as logical * +* ;sec #. Varies from: * +* ;$09 --> $00 --> $FF. * +* - As indicated above, SEC2RD08 ($800) defines the number of * +* sectors to be read in by boot0. This value is normally $01 * +* (meaning read only sector0 of track0). However, you can zap * +* trk0/sec0/offset0 with a larger value ($01 to $10) to read * +* more sectors from trk0. Also note that most references say * +* that SEC2RD08 normally contains a "$00" (rather than a * +* "$01"). Because the test at $CsF6 uses the carry, either * +* value will only cause one sector to be read in. However, * +* "$01" is the value used by DOS. (Confusion may stem from * +* the fact that Applesoft later stores a $00 in memory at * +* $800.) * +* * +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* + + +(B600) <============= image address. +SEC2RDB6 +(800) <============== execution address. +SEC2RD08 HEX 01 ;Defines the number of sectors to be read + ;in from track 0 during BOOT0. + +(B601) +BT1EXCB6 +(801) +BT1EXC08 LDA PT2BUF+1 ;Get the next page to read in. + CMP #$09 ;Is it page 9 (ie. first page read by BOOT1)? + BNE SKPREL08 ;No - already used by BOOT1 to read page 9, + ;so skip pointer initialization given below. + +* Initialize the pointer (PT2RDSC) to point +* at BOOT0's read sector subroutine (BTRDSEC, +* $Cs5C, where s = slot #, normally $C65C). +(B607) +(807) LDA SLT16ZPG ;(a) = slot *16. + LSR ;Divide by 16. + LSR + LSR + LSR + ORA $C0 ;Merge with $C0 to get $Cs, where s=slot#. + STA PTR2RDSC+1 ;Store the hi byte of the address of the + ;controller's read sector subroutine. + LDA # $FF.) + BMI PRP4B208 ;When (x) = $FF, we have read all the + ;sectors in so go exit. + LDA PHYSECP8-$AE00,X ;Convert the logical sector number + ;to a physical sector number. (Equivalent + ;to "LDA $84D,X".) + STA BOOTSEC ;Store physical sector number in page0. + DEC BT1PG2RD ;Reduce sectors (pages) left to read for + ;the next time around. + LDA BT1LDADR+1 ;Point the buffer pointer at the target + STA PT2BTBUF+1 ;address. (Varies from $BF to $B6 on a + ;48K slave.) + DEC BT1LDADR+1 ;Reduce the hi byte of the I/O buffer for + ;the next time around. (Varies from $BF to + ;$B5 on a 48K slave.) + LDX SLT16ZPG ;Set (x) = slot*16. +(836) JMP (PTR2RDSC) ;Equivalent to "JMP ($8FD)" or "JMP $Cs5C" +(B636) ------------ ;to go read in the next sector. + ;***************** NOTE ******************* + ;* GOES TO BT1EXC08 ($801) AFTER @ SECTOR * + ;* IS READ IN. (BT1EXCB6 is a carbon copy * + ;* of BT1EXC08.) * + ;****************************************** + +* Prepare for BOOT2. +(B639) +PRP4B2B6 +(839) +PRP4B208 INC BT1LDADR+1 ;Point at the load address for BOOT2. + INC BT1LDADR+1 ;(After the INCs = $B7 on 48K slave.) + +* Set full screen text & designate the +* keyboard and screen as the I/O devices. +(B63F) +(83F) JSR SETKBD ;Simulate an IN#0. (See dis'mbly below.) + JSR SETVID ;Simulate an PR#0. (See dis'mbly below.) + JSR INIT ;Simulate a "TEXT" statement. (See dis'mbly + ;in APPLE II REFERENCE MANUAL at $FB2F.) + LDX SLT16ZPG ;(x) = slot * 16. + +* Go to BOOT2. +(B64A) +(84A) JMP (BT1LDADR) ;Jump to BOOT2 ($B700 on 48K slave). + -------------- + + +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* +* * +* BOOT2 * +* * +*----------------------------------------------------------------* +* * +* - Reads in the rest of DOS starting at trk02/sec04 down to * +* trk00/sec0A ($B5FF --> $9B00). (P.S. Sectors 0A and 0B of * +* track 0 are empty ($9CFF - $9B00).) * +* - After the rest of DOS is read in, execution jumps to DOS's * +* coldstart routine (DOSCLD, $9D84). * +* - Note that on entry: (x) = slot * 16 * +* * +*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::* + + +* Prepare RWTS's input-output block (IOB) +* and designate the number of sectors to read. +(B700) +BOOT2 STX IBSLOT ;(x) = slot*16 wanted. + STX IOBPSN ;Last-used slot*16 value. + LDA #1 ;Set both the last-used and wanted drives + STA IOBDPDN ;as drive #1. + STA IBDRVN + LDA NMPG2RD ;Set number of pages (ie. secs) to read. + STA BT2PGCTR ;Counter for for number of pages to read. + LDA #2 ;Start with trk02/sec04. + STA IBTRK ;Track. + LDA #4 + STA IBSECT ;Sector. +(B71E) LDY BT1MGADR+1 ;(y) = hi byte of the address of the image + ;of BOOT1 (#$B6 on a 48K slave). +(B721) DEY ;Define I/O buf as 1 page below boot1. + STY IBBUFP+1 + LDA #1 ;Opcode for read. +(B727) STA IBCMD + +* Convert from (x) = slot*16 to (x) = slot. +(B72A) TXA ;(x) = slot * 16. + LSR ;Divide by 16. + LSR + LSR + LSR +(B72F) TAX ;(x) = slot. + +* Initialize the page-four locations with +* the track numbers associated with the drives. +(B730) LDA #0 + STA TRK4DRV2,X +(B735) STA TRK4DRV1,X + +* Call the routine to read in the rest of DOS. +(B738) JSR RWPAGES + + * READ/write a group of pages. + (B793) + RWPAGES LDA ADROFIOB+1 ;Init (a)/(y) with the hi/low bytes of the + LDY ADROFIOB ;addr of RWTS's IOB for entry to RWTS. + (B799) JSR ENTERWTS ;Enter RWTS to read/write sector. + + * Entry to RWTS. + (B7B5) + ENTERWTS PHP ;Save status register on the stack. + (B7B6) SEI ;Set the interrupt disable flag to prevent + ;any further maskable interrupts when doing + ;real-time programming. + (B7B7) JSR RWTS ;Enter RWTS proper to do the operation: + ; $00=seek, $01=read, $02=write, $03=format. + + * RWTS proper. + (BD00) + RWTS . + . + (See dis'mbly in RWTSDRVR using READ.) + . + . + (RTS) + + (B7BA) BCS ERRENTER ;Operation was NOT successful. + PLP ;Retrieve saved status off the stack. + (B7BE) RTS + ============ + + (B7BF) + ERRENTER PLP ;Throw the saved status off the stack. + SEC ;Signal operation was unsuccessful. + (B7C1) RTS + ============ + + (B79C) LDY IBSECT ;Get # of the sector just read or written. + (B79F) DEY ;Set value for next sector 2 read. When + ;executing BOOT1, goes from $09 to $FF. + (B7A0) BPL SAMETRK ;Branch to use the same track. + + * Start a new track. + (B7A2) LDY #$0F ;Start with sector 15. + NOP + NOP + (B7A6) DEC IBTRK ;Reduce number of track wanted. + + * Reduce the addr of the target memory location. + * Test if more sectors to read. + (B7A9) + SAMETRK STY IBSECT ;Store the sector wanted. + DEC IBBUFP+1 ;Reduce buf addr of target memory location. + DEC BT2PGCTR ;Reduce counter for # of sectors to read. + BNE RWPAGES ;More sectors to read. + (B7B4) RTS + +(B73B) LDX #$FF ;Completely clear out the stack. + TXS + STX IBVOL ;Set the volume to $FF (compliment of 0). +(B741) JMP CLOBCARD + ------------ + +* Patch to clobber the language card +* and set video output. +(BFC8) +CLOBCARD JSR SETVID ;Select the video screen. + + * Monitor ROM's routine to designate the + * video screen as the output device. + * (Simulate a "PR#0" statement.) + (FE93) + SETVID LDA #0 ;Designate slot 0. + OUTPORT STA A2L + OUTPRT LDX #COUT1 ;(Hi byte of addr of KEYIN & COUT1 are equal.) + IOPRT2 STY LOC0,X ;Set CSW: COUT1. + STA LOC1,X + (FEAD) RTS + +(BFCB) LDA $C081 ;Write enable the RAM card. + LDA $C081 ;(Read motherboard / write card bank 2.) + LDA #0 ;Set the language identifying byte on the +(BFD3) STA BASICCLD ;card to $00 so if card is tested (during + ;an FP command), the machine will be forced + ;to use the motherboard version of FP. +(BFD6) JSR CONTCLOB ;Now clobber the 80-column card. + + * Clobber the 80-column card. + (BA76) + CONTCLOB LDA #$FF ;Set the mode flag for card. + STA $4FB ;Scratch pad memory for slot 3 peripheral. + STA $C00C ;Turn off the alternate character set. + STA $C00E + (BA81) JMP INIT ;Simimulate a TEXT statement. + ------------ + + * Monitor ROM's Init routine. + (FB2F) + INIT . + . + (See dis'mbly in APPLE II REFERENCE MANUAL.) + . + . + - simulate a text statement. + (Ie. set window to full screen text.) + . + . + (RTS) + +(BFD9) JMP BK2BOOT2 ;Return to original part of BOOT2. + ------------ + +* Return back to original part of BOOT2. +(B744) +BK2BOOT2 JSR SETKBD ;Select the keyboard. + + * Monitor ROM's routine to designate the + * keyboard as the input device. + * (Simulate a "IN#0" statement.) + (FE89) + SETKBD LDA #0 ;Pretend using slot 0. + INPORT STA A2L + INPRT LDX #COUT1 ;(Hi byte of the addr of KEYIN & COUT1 are equal.) + IOPRT2 STY LOC0,X ;Set KSW: KEYIN. + STA LOC1,X + (FEAD) RTS + +(B747) JMP DOSCOLD ;Jump into DOS's coldstart routine to build + ------------ ;the DOS buffers and the page-three vector + . ;table and then run the "HELLO" program. + . ;*************** N O T E ***************** + . ;* This instruction is a hacker's dream. * + . ;* For instance, you can change the jump * + . ;* to point to you own password or time- * + . ;* bomb routine that you have deviously * + . ;* embedded in an unused section of DOS. * + . ;***************************************** + . + . + . +*---------------------* +* SEE dis'mbly titled * +* "DOSCOLDSTART" * +*---------------------* + . + . + . \ No newline at end of file diff --git a/eagle/DB19F adapter/big-mess-o-wires.lbr b/eagle/DB19F adapter/big-mess-o-wires.lbr new file mode 100644 index 0000000..72be529 --- /dev/null +++ b/eagle/DB19F adapter/big-mess-o-wires.lbr @@ -0,0 +1,526 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>SUB-D</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +10 +11 +19 + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +10 +11 +19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + +<b>SUB-D</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/eagle/DB19F adapter/db19f.brd b/eagle/DB19F adapter/db19f.brd new file mode 100644 index 0000000..423224e --- /dev/null +++ b/eagle/DB19F adapter/db19f.brd @@ -0,0 +1,575 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +DB19F WWW.BIGMESSOWIRES.COM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +10 +11 +19 + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +<b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie fĂĽr +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab. +<b>Laen's PCB Order Design Rules</b> +<p> +Please make sure your boards conform to these design rules. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/eagle/DB19F adapter/db19f.sch b/eagle/DB19F adapter/db19f.sch new file mode 100644 index 0000000..cbaa306 --- /dev/null +++ b/eagle/DB19F adapter/db19f.sch @@ -0,0 +1,707 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +10 +11 +19 + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE + + + + + +>VALUE + + + + + +<b>SUPPLY SYMBOL</b> + + + + + + + + + + + + +<b>SUPPLY SYMBOL</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/eagle/FPGA disk controller/ELL-i-DigitalIC.lbr b/eagle/FPGA disk controller/ELL-i-DigitalIC.lbr new file mode 100644 index 0000000..9c37fb7 --- /dev/null +++ b/eagle/FPGA disk controller/ELL-i-DigitalIC.lbr @@ -0,0 +1,6152 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>DigitalIC -- ELL-i open source co-op Eagle libraries</h3> + +<p>In this library you'll find digital ICs, such as MCUs, that are used in the ELL-i boards.</p> + +<p>Whenever possible, we prefer to use the components from the <a href="https://github.com/Ell-i/SparkFun-Eagle-Libraries">SparkFun Public Eagle PCB Footprints</a>, as they are available from <a href="https://github.com/">GitHub</a>. Whenever possible, we also prefer to push our components to the SparkFun libraries. However, this is not always possible, and therefore we have our own libraries that for the most part contain components that cannot be found in the SparkFun libraries.</p> + + +<h3>24 leads Quad-flat no-leads package (QNF)</h3> + +<p>4x4 mm, 0.5 mm pitch. See the SparkFun-DigitalIC.lbr for additional QFN24 packages.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/QFN">Wikipedia article on QFNs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +<h3>24 leads Quad-flat no-leads package (QNF) with a hole</h3> + +<p>4x4 mm, 0.5 mm pitch, with a central hole. This footprint may be better than the regular one, depending on your process and intentions. See the SparkFun-DigitalIC.lbr for additional QFN24 packages.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/QFN">Wikipedia article on QFNs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + +<h3>144 leads Low Profile Quad Flat Package (LQFP)</h3> + +<p>20x20 mm, 0.5 mm pitch, 1.5 mm height.</p> + +<p><b>Note</b> that this package has a "phantom" pad in the middle of it, i.e. a pad whose size is 0.00x0.00 mm, and who is named as NC (not connected). This is needed as the STM32F42x has an extra pin (BYPASS_REG) in the WLCSP143 package, while it does not have it in the LQFP package. This avoids us from having two different devices.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>144 leads Thin Profile Quad Flat Package (TQFP)</h3> + +<p>20x20 mm, 0.5 mm pitch, 1 mm height.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/TQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>100 leads Low Profile Quad Flat Package (LQFP)</h3> + +<p>14x14 mm, 0.5 mm pitch.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>143 balls Wafer Level Chip-Size Package (WLCSP)</h3> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/WLCSP">Wikipedia article</a></li> +</ul> + +<p><b>Not</b> proven in production. Probably faulty, needs at least a review.</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>48 leads Low Profile Quad Flat Package (LQFP)</h3> + +<p>7x7 mm, 0.5 mm pitch.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>64 leads Low Profile Quad Flat Package (LQFP)</h3> + +<p>10x10 mm, 0.5 mm pitch.</p> + +<ul> + <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>132 balls chip sized Ball Grid Array (BGA) for Lattice MachXO2 series FPGAs</h3> + +<p>8x8 mm, 0.5 mm pitch.</p> + +<p><b>Note</b> that this package has extra non-connected invisible 0.0x0.0 sized pads, in the middle, named NC1-NC7. That facilitates allowing csBGA 132 and TQFP 144 packages to be used with the same device.</p> + +<p><b>Note</b> that this package extra annotation in the Docu layer, showing which balls form together pin pairs in the FPGA pin assignment.</p> + +<ul> + <li>Lattice <a href="http://www.latticesemi.com/~/media/Documents/DataSheets/PackageDiagrams.pdf">Package Diagrams</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>132 balls chip sized Ball Grid Array (BGA) for Lattice iCE40 series FPGAs</h3> + +<p>8x8 mm, 0.5 mm pitch.</p> + +<ul> + <li>Lattice <a href="http://www.latticesemi.com/~/media/Documents/DataSheets/PackageDiagrams.pdf">Package Diagrams</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>QFN 32-Pin package w/ Thermal Pad</h3> +<p><b>Note: Unproven!</b> +<p><b>Note</b> that this package has two "phantom" pad in the middle of it, i.e. a pads whose size is 0.00x0.00 mm, and who are named as NC (not connected). This avoids us from having two different ERP symbols.</p> +<p>Copied from SparkFun-DigitalIC.lbr</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>Name +>Value + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +* + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +* +>NAME +>VALUE + + +<p> +SOIC-16 package, narrow +</p> +<p> +10 mm long, 6 mm wide. +150 mil (1.27 mm) pin spacing, 0.65 mm pad width, 1.75 mm pad length. +</p> +<p> +JEDEC MS-012 +</p> +<p> +Not reviewed +</p> +<p> +<a href="http://grabcad.com/library/soic-package-narrow-8-10-14-and-16-pins-1">Possible step model</a> +</p> + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>44-pin TGFP, 0.8 mm pitch, 10*10 mm body</h3> +<p>Package drawn from <a href="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf">Datasheet</a> pages 154 and 155. +</p> +<p> +Not reviewed +</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>Name +>Value + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver</h3> + +<ul> + <li><a href="http://media.digikey.com/pdf/Data%20Sheets/SMSC/LAN8720.pdf">Datasheet</a></li> +</ul> + +<p>TODO (perhaps): Replace with a more generic Ethernet PHY symbol</p> + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F-series MCU GPIO port A.</h3> + +<p>This port appears to be available, with all pins exposed, throughout the STM32F-series, from STM32F030 to STM32F439. The TSSOP20 package of the STM32F030 is an exception, exposing only PA0–PA7, PA9–PA10, PA13, and PA14. The alternate functions vary from model to model.</p> + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>STM32F-series MCU GPIO port B.</h3> + +<p>This port appears to be available, with at least some pins exposed, throughout the STM32F-series, from STM32F030 to STM32F439. The alternate functions vary from model to model. The most commonly exposed pin is PB1, followed by PB0 and PB3–PB7, and then PB2 and PB8.</p> + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>STM32F-series MCU GPIO port C.</h3> + +<p>This port appears to be available, with at least some pins exposed, throughout most of the STM32F-series, from STM32F030 to STM32F439. The alternate functions vary from model to model. In the lowest pin-count packages the port is not exposed. The most commonly exposed pins are PC13–PC15.</p> + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>STM32F-series MCU GPIO port D.</h3> + +<p>This port appears to be available, with at least one pin (PD2) exposed, throughout most of the STM32F-series, from STM32F030 to STM32F439. For example, STM32F050 does not have this port at all, and STM32F030 exposes PD2 in the largest LQPF64 package. The alternate functions vary from model to model. In the lowest pin-count packages the port is not exposed. </p> + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU GPIO port E.</h3> + +<p>This port is available only in the higher end models of the STM32F-series. The alternate functions vary from model to model.</p> + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU power pads, version 2.</h3> + +<p>This version has PDR_ON and BYPASS_REG pins.</p> + + + + + + + + + +>NAME + + + + + + +<h3>STM32F-series MCU control pads, high-end.</h3> + +<p>This version has OSC_IN and OSC_OUT in PH0 and PH1, respectively, and has VREF+.</p> + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU GPIO port F.</h3> + +<p>This port appears to be available throughout most of the STM32F-series, from STM32F030 to STM32F439. The alternate functions vary from model to model. In the lowest pin-count packages the port is not exposed. The most commonly exposed pins are <tt>PF0</tt>–<tt>PF1</tt>, which are the external oscillator pins in the low-end devices. In high-end devices the oscillator tends to be connected to <tt>PH0</tt>–<tt>PH1</tt> instead. Consequently, if you have a low-end device that exposes only <tt>PF0</tt>–<tt>PF1</tt> as the oscillator, don't include this symbol but only a control symbol with the oscillator pins there.</p> + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU GPIO port D pin 2 and F pins 4-7.</h3> + +<p>Extra pins available in STM32F051 + LQFP64 package.</p> + + + + + + + + +>NAME + + +<h3>STM32F-series MCU GPIO port G.</h3> + +<p>This port is available only in the higher end models of the STM32F-series. The alternate functions vary from model to model.</p> + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>STM32F-series MCU power pads.</h3> + +<p>This version does not have the PDR_ON or BYPASS_REG pins.</p> + + + + + + + + + +>NAME +>VALUE + + +<h3>STM32F-series MCU control pads, low-end.</h3> + +<p>This version has OSC_IN and OSC_OUT in PF0 and PF1, respectively, and has no VREF+.</p> + + + + + + + + +>NAME + + +<h3>Lattice MachXO2 Embedded Function Block (EFB) signal pins</h3> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/ApplicationNotes/UsingUserFlashMemoryandHardenedControlFunctionsinMachXO2Devices.pdf">Datasheet</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + +>NAME + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<p>Additional bottom ports for csBGA 132</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<p>Top ports in the csBGA 132 package, in addition to those available in QFN32.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<p>Right ports in the csBGA 132 package, in addition to those available in QFN32.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<p>Left ports in the csBGA 132 package, in addition to those available in QFN32.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + + + + + +csBGA132 PL 256/640/... + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> + +<p>Top ports in the csBGA 132 package, in addition to those available in 256.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> + +<p>Left ports in the csBGA 132 package, in addition to those available in 256.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> + +<p>Right ports in the csBGA 132 package, in addition to those available in 256.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> + +<p>Bottom ports in the csBGA 132 package, in addition to those available in 256.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Top ports in the csBGA 132 package, in addition to those available in 640.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Left ports in the csBGA 132 package, in addition to those available in 640.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Right ports in the csBGA 132 package, in addition to those available in 640.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Bottom ports in the csBGA 132 package, in addition to those available in 640.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + + + +<h3>Lattice MachXO2 common power pins for 256 / 640 / 1200 / 2000 / 4000</h3> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>Lattice MachXO2 common power pins for QFN32 package</h3> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + +>NAME +>VALUE + + + + + +Arduino A0 +ETH RMII_REF_CLK +ETH RMII_MDIO +Arduino D6 +Arduino A2 +Arduino A3 +Arduino D12 / SPI MISO +ETH RMII_CRS_DV +MCO +Arduino D1 / TX +Arduino D0 / RX +Arduino D3 / CTS +Arduino D4 / RTS +JTMS / SWDIO +JTCK / SWCLK +JTDI / Arduino D10 / SPI SS + + +<h3>ELL-i functions for STM32F Port A</h3> + +<p>STM32F051/030 64-pin TQFP version</p> + + + +Arduino A0 +ENC28J60 Interrupt +Arduino A1 +Arduino D6 +Arduino A2 +Arduino A3 +D12 / SPI1_MISO +MCO +Arduino D1 / TX +Arduino D0 / RX +Arduino D3 / CTS +Arduino D4 / RTS +SWDIO +SWCLK +Arduino D10 + + + + + +Arduino D9 (PWM) +Arduino D5 (PWM) +-> MachXO2 SN +JTDO / Arduino D13 / SPI1_SCK +JNRST / JTAGENB +Arduino D11 (PWM) / SPI1_MOSI +Arduino A5 / I2C_SCL +FMC_NL/NADV +Arduino D7 +Arduino A4 / I2C_SDA +ELL-i I2C2_SCL +ELL-i I2C2 SDA +ELL-i SPI2_SS / CAN2_RX +ELL-i SPI2_SCK / CAN2_TX +ELL-i SPI2_MISO +ELL-i SPI2_MOSI + + +<h3>ELL-i functions for STM32F Port B</h3> + +<p>STM32F051/030 64-pin TQFP version</p> + + + +Arduino D9 (PWM) +Arduino D5 (PWM) +-> MachXO2 SN* +Arduino D13 / SPI_SCK +-> MachXO2 JTAGENB +Arduino D11 (PWM) / SPI_MOSI +Arduino A5 / I2C_SCL +Arduino D8 +Arduino D7 +ARduino A4 / I2C_SDA +ELL-i I2C2_SCL +ELL-i I2C2 SDA +ELL-i SPI2_SS / CAN2_RX +ELL-i SPI2_SCK / CAN2_TX +ELL-i SPI2_MISO +ELL-i SPI2_MOSI + + + + + +FMC_SNDWE +ETH MDC +FMC_SNDE0 +FMC_SDCKE0 +ETH RMII_RXD0 +ETH RMII_RXD1 +ELL-i LVSD 6T +ELL-i LVDS 6C + + +ELL-i USART3_TX +ELL-i USART3_RX +-> MachXO2 CSSPIN +TAMP1 +OSC32_IN +OSC32_OUT +-> MachXO2 PROGRAMN +-> MachXO2 JTDI + + +<h3>ELL-i functions for STM32F Port C</h3> + +<p>STM32F051/030 64-pin TQFP version</p> + + + +ELL-i LVDS 3T +ELL-i LVDS 3C +ELL-i LVDS 4T +ELL-i LVDS 4C +ELL-i LVDS 5T +ELL-i LVDS 5C +ELL-i LVDS 6T +ELL-i LVDS 6C + + +ELL-i USART3_TX (GPIO) +ELL-i USART3_RX (GPIO) +-> MachXO2CSSPIN +TAMP1 +OSC32_IN +OSC32_OUT +-> Mach XO2 PROGRAMN +-> Mach XO2 JTDI + + + + + +FMC_D2 +FMC_D3 +FMC_CLK +FMC_NOE +FMC_NWE +FMC_NWAIT +FMC_NE1 +FMC_D13 +FMC_D14 +FMC_D15 +FMC_A16 +FMC_A17 +FMC_A18 +FMC_D0 +FMC_D1 +Arduino D2 + + + + + +FMC_NBL0 +FMC_NBL1 +FMC_A23 +FMC_A19 +FMC_A20 +FMC_A21 +FMC_A22 +FMC_D4 +FMC_D5 +FMC_D6 +FMC_D7 +FMC_D8 +FMC_D9 +FMC_D10 +FMC_D11 +FMC_D12 + + + + + +FMC_A0 +FMC_A1 +FMC_A2 +FMC_A3 +FMC_A4 +FMC_A5 + + + + + +FMC_SNDRAS +FMC_A6 +FMC_A7 +FMC_A8 +FMC_A9 +Arduino A1 +ELL-i LVDS 2T +ELL-i LVDS 1C +ELL-i LVDS 1T +ELL-i LVDS 2C + + + + + +FMC_A10 +FMC_A11 +FMC_A12 +FMC_A13 +FMC_A14 +FMC_A15 + + +FMC_SDCLK +FMC_NE2 +FMC_NE3 +ETH RMII_TXEN +FMC_NE4 +ETH RMII_TXD0 +ETH RMII_TXD1 +Arduino D8 +ELL-i LVDS 5T +FMC_SNDCAS + + +<h3>Lattice MachXO2 common I/O pins for 256</h3> + +<p>Generic pins available in the QFN32 package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> +</ul> + + + + + + + + + + + +>NAME + + +<h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> + +<p>Ports in the TQFP 144 package for MachXO2 1200, in addition to those available in csBGA 132 package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> +</ul> + + + + + + +TQFP144- +only pins + + + + + + + + +TQFP144- +only pins + + + +<h3>ELL-i I/O pins for Lattice MachXO2</h3> + +<p>Generic pins in the QFN32 package.</p> + + + +LVDS 3T +LVDS 3C +LVDS 1T +LVDS 1C +LVDS 2T +LVDS 2C +MCO +Arduino D8 + + +<h3>ELL-i I/O pins for Lattice MachXO2</h3> + +<p>The "QFN32 package" pins for ELL-i when TQFP144 package is used.</p> + + + +DDR2 TBD +DDR2 TBD +Memory CLK +Memory NE1 +Arduino D5 / JNRST +Arduino D6 +DDR2 CLK TBD +DDR2 CLK TBD + + + + + +Memory AD2 +Memory AD3 +Memory AD4 +Memory AD5 +Memory AD6 +Memory AD7 +Memory AD14 +Memory AD15 +Memory A18 +Memory A19 +DDR2 TBD +DDR2 TBD + + + + + +Memory AD8 +Memory AD9 +Memory AD16 +Memory AD17 +DDR2 TBD +DDR2 TBD + + + + + +Memory AD0 +Memory AD1 +Memory AD10 +Memory AD11 +DDR2 TBD + + + + + +USART3_TX +USART3_RX +Memory A22 +Memory A23 + + + + + +Memory A21 +Memory NL/NADV +Arduino D7 +Arduino D9 +SPI2_SS / CAN2_RX +SPI2_SCK / CAN2_TX + + + + + +Memory NBL0 +Memory NBL1 +Memory NOE +Memory NWE +Arduino D0 +Arduino D1 +SPI2 MISO +SPI2 MOSI + + + + + +LVDS 1T +LVDS 1C +DDR2 TBD + + + + + +Memory AD12 +Memory AD13 +DDR2 CLK TBD +DDR2 CLK TBD + + + + + +DDR2 DQn +DDR2 DQn +DDR2 DQn +DDR2 DQn +DDR2 DQn +DDR2 DQn +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR + + + + + +DDR2 DQ0 +DDR2 DQ0 +DDR2 DQS0N check! +DDR2 DQS0 check! +DDR2 ADDR +DDR2 ADDR + + + + + +DDR2 DQ0 +DDR2 DQ0 +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR +DDR2 ADDR + + + + + +LVDS 6T +LVDS 6C +MCO +Arduino D2 + + + + + +LVDS 2T +LVDS 2T +LVDS 3T +LVDS 3C +LVDS 5T +LVDS 5C + + + + + +Arduino D8 +Memory NWAIT +I2C2 SCL +I2C2 SDA +LVDS 4T +LVDS 4B + + +<h3>ELL-i functions for STM32F Porta D and F</h3> + +<p>STM32F051/030 64-pin TQFP version</p> + + + +Arduino D2 +ELL-i LVDS 1T +ELL-i LVDS 1C +ELL-i LVDS 2T +ELL-i LVDS 2C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +Quad 2:1 high-speed CMOS TTL-compatible multiplexer +<h3>Description</h3> +<p> +The Fairchild Switch FST3257 is a quad 2:1 high-speed CMOS TTL-compatible multiplexer / demultiplexer bus +switch. +</p> +<p> +The low on resistance of the switch allows +inputs to be connected to outputs without adding +propagation delay or generating additional ground +bounce noise. +</p> +<p> +When /OE is LOW, the select pin connects the A port to +the selected B port output. When /OE is HIGH, the +switch is OPEN and a high-impedance state exists +between the two ports. +</p> +<p> +<a HREF="www.fairchildsemi.com/ds/FS/FST3257.pdf"> Datasheet </a> +</p> +<p> +Not reviewed +</p> + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>STM32F-series MCU control pads</b> + + + + + + +>NAME +>VALUE + + + + + +<b>STM32F1-series MCU Power pads</b> + + + + + + + + + + + + + + +>NAME +>VALUE + + +<h3>ENC424J600</h3> +<p> +The ENC424J600 and ENC624J600 are stand-alone, +Fast Ethernet controllers with an industry standard +Serial Peripheral Interface (SPI) or a flexible parallel +interface. They are designed to serve as an Ethernet +network interface for any microcontroller equipped with +SPI or a standard parallel port. +</p> +<p> +This is 44 pin version of device, <a href="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf">Datasheet</a> +</p> +<p> +Not reviewed +</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + +<h3>Small Footprint RMII 10/100 Ethernet Transceiver</h3> + +<ul> + <li><a href="http://media.digikey.com/pdf/Data%20Sheets/SMSC/LAN8720.pdf">Datasheet</a></li> + <li>Mouser: <a href="">886-LAN8720AI-CP</a></li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F427 / 429 in LQFP144 or WLCSP143 package.</h3> + +<p>STM32F4-series Cortex-M4 microcontroller in a 144 or 143 lead package.</p> + +<ul> + <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00071990.pdf">Datasheet (DM00071990.pdf)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F427 / 429 in LQFP100 package.</h3> + +<p>STM32F4-series Cortex-M4 microcontroller in a 100 lead package.</p> + +<ul> + <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00071990.pdf">Datasheet (DM00071990.pdf)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F051 in LQPF48 package.</h3> + +<p>STM32F0-series Cortex-M0 microcontroller in a 48 lead package.</p> + +<ul> + <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00039193.pdf">Datasheet</a> (DM00039193.pdf)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F051 in LQPF64 package.</h3> + +<p>STM32F0-series Cortex-M0 microcontroller in 64 lead package.</p> + +<ul> + <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00039193.pdf">Datasheet</a> (DM00039193.pdf)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3> MachXO2-256 in csBGA132 or TQFP144 package.</h3> + +<p>Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3> MachXO2-1200 in csBGA132 or TQFP144 package.</h3> + +<p>Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3> MachXO2-2000 in csBGA132 or TQFP144 package.</h3> + +<p>Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F427 / 429 ELL-i functions.</h3> + +<p>This device contains a number of pseudo-symbols, meant to be used with a real STM32F42x MCU. The pseudo-symbols list the ELL-i project functions for the STM32F4 MCU pins.</p> + +<ul> + <li>TBD (a link to the relevant design document)</li>. +</ul> + + + + + + + + + + + + + + + + + + +<h3>MachXO2 2000 ELL-i functions.</h3> + +<p>This device contains a number of pseudo-symbols, meant to be used with a real MachXO2-2000 FPGA. The pseudo-symbols list the ELL-i project functions for the 132/144 pins FPGA package.</p> + +<ul> + <li>TBD (a link to the relevant design document)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>MachXO2-256 in 32-pin QFN package.</h3> + +<p>Lattice MachXO2-series FPGA in a 32-pin QFN package, 0.5 mm pitch.</p> + +<ul> + <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>STM32F051/030 ELL-i functions.</h3> + +<p>This device contains a number of pseudo-symbols, meant to be used with a real STM32F0 MCU. The pseudo-symbols list the ELL-i project functions for the STM32F0 MCU pins in a 64-pin package.</p> + +<ul> + <li>TBD (a link to the relevant design document)</li>. +</ul> + + + + + + + + + + + + + + + +Stand-Alone 10/100 Ethernet Controller + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>MachXO2 256 QFN32 ELL-i functions.</h3> + +<p>This device contains a pseudo-symbols, meant to be used with a corresponding MachXO2-256 FPGA device. The pseudo-symbols list the ELL-i project extra functions for the 32 pins FPGA package. Most of the functions in the QFN32 package are predefined by Lattice, though overrideable by a user design.</p> + +<ul> + <li>TBD (a link to the relevant design document)</li>. +</ul> + + + + + + + + + + + + +<p> +Quad 2:1 Multiplexer / Demultiplexer Bus Switch +</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +STM32F103 Medium Density 64pin LQFP +<br><br> +<a href="http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00161566.pdf">Datasheet</a> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +STM32F103 Medium Density 64pin LQFP +<br><br> +<a href="http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00161566.pdf">Datasheet</a> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h3>ENC424J600</h3> +<p> +The ENC424J600 and ENC624J600 are stand-alone, +Fast Ethernet controllers with an industry standard +Serial Peripheral Interface (SPI) or a flexible parallel +interface. They are designed to serve as an Ethernet +network interface for any microcontroller equipped with +SPI or a standard parallel port +</p> +<p> Not reviewed. <a href ="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf">Datasheet</a> +</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Since Version 6.2.2 text objects can contain more than one line, +which will not be processed correctly with this version. + + + diff --git a/eagle/FPGA disk controller/bmowdisk.b#1 b/eagle/FPGA disk controller/bmowdisk.b#1 new file mode 100644 index 0000000..b8a2cf7 --- /dev/null +++ b/eagle/FPGA disk controller/bmowdisk.b#1 @@ -0,0 +1,4034 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +U1 +U2 +U3 +U4 +U5 +U6 +U7 +CON1 +D1 +R1 +J1 +J2 +J3 +J4 +MOSI +MISO +SCLK +CS +3V3 +TDO +GND +TDI +TCK +TMS +R2 +R3 +R4 +R5 +R6 +1 +25 +C13 +C8 +C14 +C15 +C9 +C16 +C10 +C17 +C11 +C18 +C12 +C1 +C2 +C3 +C4 +C5 +C6 +L1 +C20 +C19 +C7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +DISK CONTROLLER +v1.0 + + + + + + + + + + + + + + + + + + + + + +<b>Apple ][ Expansion Card Templates</b> +<br /> +Dimensions are taken from the Apple IIgs Tech Note #28 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +7,87 mm +74.93 mm +2.950" + + + + + + + +<b>Shrink Small Outline Package</b><p> +package type SS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +TQFP 100 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + +<b>Micrel Voltage Regulator</b><p> +Micrel Semiconductor, Inc.<br> +http://www.micrel.com<p> +<author>Created by librarian@cadsoft.de</author> + + +<b>Small Outline Transistor</b> + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + +<b>Hyper CHIPLED Hyper-Bright LED</b><p> +LB R99A<br> +Source: http://www.osram.convergy.de/ ... lb_r99a.pdf + + + + +>NAME +>VALUE + + + + + + + + + +<h3>SparkFun Electronics' preferred foot prints</h3> +In this library you'll find connectors and sockets- basically anything that can be plugged into or onto.<br><br> +We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> CC v3.0 Share-Alike You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage. + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +Generated from <b>retro-usb.sch</b><p> +by exp-lbrs.ulp + + +<b>PIN HEADER</b> + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +>NAME +>VALUE + + + + + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<h3>SparkFun Electronics' preferred foot prints</h3> +In this library you'll find resistors, capacitors, inductors, test points, jumper pads, etc.<br><br> +We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> CC v3.0 Share-Alike You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage. + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + +<b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie fĂĽr +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab. +<b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Since Version 6.2.2 text objects can contain more than one line, +which will not be processed correctly with this version. + + + diff --git a/eagle/FPGA disk controller/bmowdisk.brd b/eagle/FPGA disk controller/bmowdisk.brd new file mode 100644 index 0000000..9728951 --- /dev/null +++ b/eagle/FPGA disk controller/bmowdisk.brd @@ -0,0 +1,2923 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +U1 +U2 +U3 +U4 +U5 +U6 +U7 +CON1 +D1 +R1 +J1 +J2 +J3 +J4 +MOSI +MISO +SCLK +CS +3V3 +TDO +GND +TDI +TCK +TMS +R2 +R3 +R4 +R5 +R6 +1 +25 +C13 +C8 +C14 +C15 +C9 +C16 +C10 +C17 +C11 +C18 +C12 +C1 +C2 +C3 +C4 +C5 +C6 +L1 +C20 +C19 +C7 + + + + + + + + + +FPGA DISK CONTROLLER +ORIGINAL DESIGN BY BIG MESS O' WIRES +v1.0 + + + + + + + + + + + + + + + + + + + + + +<b>Apple ][ Expansion Card Templates</b> +<br /> +Dimensions are taken from the Apple IIgs Tech Note #28 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +7,87 mm +74.93 mm +2.950" + + + + + + + +<b>Shrink Small Outline Package</b><p> +package type SS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +TQFP 100 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + +<b>Micrel Voltage Regulator</b><p> +Micrel Semiconductor, Inc.<br> +http://www.micrel.com<p> +<author>Created by librarian@cadsoft.de</author> + + +<b>Small Outline Transistor</b> + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + +<b>Hyper CHIPLED Hyper-Bright LED</b><p> +LB R99A<br> +Source: http://www.osram.convergy.de/ ... lb_r99a.pdf + + + + +>NAME +>VALUE + + + + + + + + + +<h3>SparkFun Electronics' preferred foot prints</h3> +In this library you'll find connectors and sockets- basically anything that can be plugged into or onto.<br><br> +We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> CC v3.0 Share-Alike You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage. + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +Generated from <b>retro-usb.sch</b><p> +by exp-lbrs.ulp + + +<b>PIN HEADER</b> + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +>NAME +>VALUE + + + + + + +<b>CONNECTOR</b><p> +series 057 contact pc board low profile headers<p> +straight + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<h3>SparkFun Electronics' preferred foot prints</h3> +In this library you'll find resistors, capacitors, inductors, test points, jumper pads, etc.<br><br> +We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> CC v3.0 Share-Alike You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage. + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + +<b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie fĂĽr +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab. +<b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +