Setting log file to 'C:/Users/chamberlin/Documents/Liron/yellowstone_blink/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v (VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/top.v INFO - C:/Users/chamberlin/Documents/Liron/top.v(1,8-1,13) (VERI-1018) compiling module blink INFO - C:/Users/chamberlin/Documents/Liron/top.v(1,1-27,10) (VERI-9000) elaborating module 'blink' INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1' WARNING - C:/Users/chamberlin/Documents/Liron/top.v(8,3-13,5) (VERI-1927) port SEDSTDBY remains unconnected for this instance Done: design load finished with (0) errors, and (1) warnings