<h3>DigitalIC -- ELL-i open source co-op Eagle libraries</h3> <p>In this library you'll find digital ICs, such as MCUs, that are used in the ELL-i boards.</p> <p>Whenever possible, we prefer to use the components from the <a href="https://github.com/Ell-i/SparkFun-Eagle-Libraries">SparkFun Public Eagle PCB Footprints</a>, as they are available from <a href="https://github.com/">GitHub</a>. Whenever possible, we also prefer to push our components to the SparkFun libraries. However, this is not always possible, and therefore we have our own libraries that for the most part contain components that cannot be found in the SparkFun libraries.</p> <h3>24 leads Quad-flat no-leads package (QNF)</h3> <p>4x4 mm, 0.5 mm pitch. See the SparkFun-DigitalIC.lbr for additional QFN24 packages.</p> <ul> <li><a href="https://en.wikipedia.org/wiki/QFN">Wikipedia article on QFNs</a></li> </ul> >NAME >VALUE <h3>24 leads Quad-flat no-leads package (QNF) with a hole</h3> <p>4x4 mm, 0.5 mm pitch, with a central hole. This footprint may be better than the regular one, depending on your process and intentions. See the SparkFun-DigitalIC.lbr for additional QFN24 packages.</p> <ul> <li><a href="https://en.wikipedia.org/wiki/QFN">Wikipedia article on QFNs</a></li> </ul> >NAME >VALUE <h3>144 leads Low Profile Quad Flat Package (LQFP)</h3> <p>20x20 mm, 0.5 mm pitch, 1.5 mm height.</p> <p><b>Note</b> that this package has a "phantom" pad in the middle of it, i.e. a pad whose size is 0.00x0.00 mm, and who is named as NC (not connected). This is needed as the STM32F42x has an extra pin (BYPASS_REG) in the WLCSP143 package, while it does not have it in the LQFP package. This avoids us from having two different devices.</p> <ul> <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> </ul> >NAME >VALUE <h3>144 leads Thin Profile Quad Flat Package (TQFP)</h3> <p>20x20 mm, 0.5 mm pitch, 1 mm height.</p> <ul> <li><a href="https://en.wikipedia.org/wiki/TQFP">Wikipedia article on QFPs</a></li> </ul> >NAME >VALUE <h3>100 leads Low Profile Quad Flat Package (LQFP)</h3> <p>14x14 mm, 0.5 mm pitch.</p> <ul> <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> </ul> >NAME >VALUE <h3>143 balls Wafer Level Chip-Size Package (WLCSP)</h3> <ul> <li><a href="https://en.wikipedia.org/wiki/WLCSP">Wikipedia article</a></li> </ul> <p><b>Not</b> proven in production. Probably faulty, needs at least a review.</p> >NAME >VALUE <h3>48 leads Low Profile Quad Flat Package (LQFP)</h3> <p>7x7 mm, 0.5 mm pitch.</p> <ul> <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> </ul> >NAME >VALUE <h3>64 leads Low Profile Quad Flat Package (LQFP)</h3> <p>10x10 mm, 0.5 mm pitch.</p> <ul> <li><a href="https://en.wikipedia.org/wiki/LQFP">Wikipedia article on QFPs</a></li> </ul> >NAME >VALUE <h3>132 balls chip sized Ball Grid Array (BGA) for Lattice MachXO2 series FPGAs</h3> <p>8x8 mm, 0.5 mm pitch.</p> <p><b>Note</b> that this package has extra non-connected invisible 0.0x0.0 sized pads, in the middle, named NC1-NC7. That facilitates allowing csBGA 132 and TQFP 144 packages to be used with the same device.</p> <p><b>Note</b> that this package extra annotation in the Docu layer, showing which balls form together pin pairs in the FPGA pin assignment.</p> <ul> <li>Lattice <a href="http://www.latticesemi.com/~/media/Documents/DataSheets/PackageDiagrams.pdf">Package Diagrams</a></li> </ul> >NAME >VALUE <h3>132 balls chip sized Ball Grid Array (BGA) for Lattice iCE40 series FPGAs</h3> <p>8x8 mm, 0.5 mm pitch.</p> <ul> <li>Lattice <a href="http://www.latticesemi.com/~/media/Documents/DataSheets/PackageDiagrams.pdf">Package Diagrams</a></li> </ul> >NAME >VALUE <h3>QFN 32-Pin package w/ Thermal Pad</h3> <p><b>Note: Unproven!</b> <p><b>Note</b> that this package has two "phantom" pad in the middle of it, i.e. a pads whose size is 0.00x0.00 mm, and who are named as NC (not connected). This avoids us from having two different ERP symbols.</p> <p>Copied from SparkFun-DigitalIC.lbr</p> >Name >Value * * >NAME >VALUE <p> SOIC-16 package, narrow </p> <p> 10 mm long, 6 mm wide. 150 mil (1.27 mm) pin spacing, 0.65 mm pad width, 1.75 mm pad length. </p> <p> JEDEC MS-012 </p> <p> Not reviewed </p> <p> <a href="http://grabcad.com/library/soic-package-narrow-8-10-14-and-16-pins-1">Possible step model</a> </p> >NAME >VALUE <h3>44-pin TGFP, 0.8 mm pitch, 10*10 mm body</h3> <p>Package drawn from <a href="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf">Datasheet</a> pages 154 and 155. </p> <p> Not reviewed </p> >NAME >VALUE >Name >Value <h3>LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver</h3> <ul> <li><a href="http://media.digikey.com/pdf/Data%20Sheets/SMSC/LAN8720.pdf">Datasheet</a></li> </ul> <p>TODO (perhaps): Replace with a more generic Ethernet PHY symbol</p> >NAME >VALUE <h3>STM32F-series MCU GPIO port A.</h3> <p>This port appears to be available, with all pins exposed, throughout the STM32F-series, from STM32F030 to STM32F439. The TSSOP20 package of the STM32F030 is an exception, exposing only PA0–PA7, PA9–PA10, PA13, and PA14. The alternate functions vary from model to model.</p> >NAME >VALUE <h3>STM32F-series MCU GPIO port B.</h3> <p>This port appears to be available, with at least some pins exposed, throughout the STM32F-series, from STM32F030 to STM32F439. The alternate functions vary from model to model. The most commonly exposed pin is PB1, followed by PB0 and PB3–PB7, and then PB2 and PB8.</p> >NAME >VALUE <h3>STM32F-series MCU GPIO port C.</h3> <p>This port appears to be available, with at least some pins exposed, throughout most of the STM32F-series, from STM32F030 to STM32F439. The alternate functions vary from model to model. In the lowest pin-count packages the port is not exposed. The most commonly exposed pins are PC13–PC15.</p> >NAME >VALUE <h3>STM32F-series MCU GPIO port D.</h3> <p>This port appears to be available, with at least one pin (PD2) exposed, throughout most of the STM32F-series, from STM32F030 to STM32F439. For example, STM32F050 does not have this port at all, and STM32F030 exposes PD2 in the largest LQPF64 package. The alternate functions vary from model to model. In the lowest pin-count packages the port is not exposed. </p> >NAME <h3>STM32F-series MCU GPIO port E.</h3> <p>This port is available only in the higher end models of the STM32F-series. The alternate functions vary from model to model.</p> >NAME <h3>STM32F-series MCU power pads, version 2.</h3> <p>This version has PDR_ON and BYPASS_REG pins.</p> >NAME <h3>STM32F-series MCU control pads, high-end.</h3> <p>This version has OSC_IN and OSC_OUT in PH0 and PH1, respectively, and has VREF+.</p> >NAME <h3>STM32F-series MCU GPIO port F.</h3> <p>This port appears to be available throughout most of the STM32F-series, from STM32F030 to STM32F439. The alternate functions vary from model to model. In the lowest pin-count packages the port is not exposed. The most commonly exposed pins are <tt>PF0</tt>–<tt>PF1</tt>, which are the external oscillator pins in the low-end devices. In high-end devices the oscillator tends to be connected to <tt>PH0</tt>–<tt>PH1</tt> instead. Consequently, if you have a low-end device that exposes only <tt>PF0</tt>–<tt>PF1</tt> as the oscillator, don't include this symbol but only a control symbol with the oscillator pins there.</p> >NAME <h3>STM32F-series MCU GPIO port D pin 2 and F pins 4-7.</h3> <p>Extra pins available in STM32F051 LQFP64 package.</p> >NAME <h3>STM32F-series MCU GPIO port G.</h3> <p>This port is available only in the higher end models of the STM32F-series. The alternate functions vary from model to model.</p> >NAME <h3>STM32F-series MCU power pads.</h3> <p>This version does not have the PDR_ON or BYPASS_REG pins.</p> >NAME >VALUE <h3>STM32F-series MCU control pads, low-end.</h3> <p>This version has OSC_IN and OSC_OUT in PF0 and PF1, respectively, and has no VREF+.</p> >NAME <h3>Lattice MachXO2 Embedded Function Block (EFB) signal pins</h3> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/ApplicationNotes/UsingUserFlashMemoryandHardenedControlFunctionsinMachXO2Devices.pdf">Datasheet</a></li> </ul> >NAME <h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> <p>Additional bottom ports for csBGA 132</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> <p>Top ports in the csBGA 132 package, in addition to those available in QFN32.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> <p>Right ports in the csBGA 132 package, in addition to those available in QFN32.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000</h3> <p>Left ports in the csBGA 132 package, in addition to those available in QFN32.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> </ul> csBGA132 PL 256/640/... <h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> <p>Top ports in the csBGA 132 package, in addition to those available in 256.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> <p>Left ports in the csBGA 132 package, in addition to those available in 256.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> <p>Right ports in the csBGA 132 package, in addition to those available in 256.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000</h3> <p>Bottom ports in the csBGA 132 package, in addition to those available in 256.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV">MachXO2 640 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> <p>Top ports in the csBGA 132 package, in addition to those available in 640.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> <p>Left ports in the csBGA 132 package, in addition to those available in 640.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> <p>Right ports in the csBGA 132 package, in addition to those available in 640.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> <p>Bottom ports in the csBGA 132 package, in addition to those available in 640.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 common power pins for 256 / 640 / 1200 / 2000 / 4000</h3> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> </ul> <h3>Lattice MachXO2 common power pins for QFN32 package</h3> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> </ul> >NAME >VALUE Arduino A0 ETH RMII_REF_CLK ETH RMII_MDIO Arduino D6 Arduino A2 Arduino A3 Arduino D12 / SPI MISO ETH RMII_CRS_DV MCO Arduino D1 / TX Arduino D0 / RX Arduino D3 / CTS Arduino D4 / RTS JTMS / SWDIO JTCK / SWCLK JTDI / Arduino D10 / SPI SS <h3>ELL-i functions for STM32F Port A</h3> <p>STM32F051/030 64-pin TQFP version</p> Arduino A0 ENC28J60 Interrupt Arduino A1 Arduino D6 Arduino A2 Arduino A3 D12 / SPI1_MISO MCO Arduino D1 / TX Arduino D0 / RX Arduino D3 / CTS Arduino D4 / RTS SWDIO SWCLK Arduino D10 Arduino D9 (PWM) Arduino D5 (PWM) -> MachXO2 SN JTDO / Arduino D13 / SPI1_SCK JNRST / JTAGENB Arduino D11 (PWM) / SPI1_MOSI Arduino A5 / I2C_SCL FMC_NL/NADV Arduino D7 Arduino A4 / I2C_SDA ELL-i I2C2_SCL ELL-i I2C2 SDA ELL-i SPI2_SS / CAN2_RX ELL-i SPI2_SCK / CAN2_TX ELL-i SPI2_MISO ELL-i SPI2_MOSI <h3>ELL-i functions for STM32F Port B</h3> <p>STM32F051/030 64-pin TQFP version</p> Arduino D9 (PWM) Arduino D5 (PWM) -> MachXO2 SN* Arduino D13 / SPI_SCK -> MachXO2 JTAGENB Arduino D11 (PWM) / SPI_MOSI Arduino A5 / I2C_SCL Arduino D8 Arduino D7 ARduino A4 / I2C_SDA ELL-i I2C2_SCL ELL-i I2C2 SDA ELL-i SPI2_SS / CAN2_RX ELL-i SPI2_SCK / CAN2_TX ELL-i SPI2_MISO ELL-i SPI2_MOSI FMC_SNDWE ETH MDC FMC_SNDE0 FMC_SDCKE0 ETH RMII_RXD0 ETH RMII_RXD1 ELL-i LVSD 6T ELL-i LVDS 6C ELL-i USART3_TX ELL-i USART3_RX -> MachXO2 CSSPIN TAMP1 OSC32_IN OSC32_OUT -> MachXO2 PROGRAMN -> MachXO2 JTDI <h3>ELL-i functions for STM32F Port C</h3> <p>STM32F051/030 64-pin TQFP version</p> ELL-i LVDS 3T ELL-i LVDS 3C ELL-i LVDS 4T ELL-i LVDS 4C ELL-i LVDS 5T ELL-i LVDS 5C ELL-i LVDS 6T ELL-i LVDS 6C ELL-i USART3_TX (GPIO) ELL-i USART3_RX (GPIO) -> MachXO2CSSPIN TAMP1 OSC32_IN OSC32_OUT -> Mach XO2 PROGRAMN -> Mach XO2 JTDI FMC_D2 FMC_D3 FMC_CLK FMC_NOE FMC_NWE FMC_NWAIT FMC_NE1 FMC_D13 FMC_D14 FMC_D15 FMC_A16 FMC_A17 FMC_A18 FMC_D0 FMC_D1 Arduino D2 FMC_NBL0 FMC_NBL1 FMC_A23 FMC_A19 FMC_A20 FMC_A21 FMC_A22 FMC_D4 FMC_D5 FMC_D6 FMC_D7 FMC_D8 FMC_D9 FMC_D10 FMC_D11 FMC_D12 FMC_A0 FMC_A1 FMC_A2 FMC_A3 FMC_A4 FMC_A5 FMC_SNDRAS FMC_A6 FMC_A7 FMC_A8 FMC_A9 Arduino A1 ELL-i LVDS 2T ELL-i LVDS 1C ELL-i LVDS 1T ELL-i LVDS 2C FMC_A10 FMC_A11 FMC_A12 FMC_A13 FMC_A14 FMC_A15 FMC_SDCLK FMC_NE2 FMC_NE3 ETH RMII_TXEN FMC_NE4 ETH RMII_TXD0 ETH RMII_TXD1 Arduino D8 ELL-i LVDS 5T FMC_SNDCAS <h3>Lattice MachXO2 common I/O pins for 256</h3> <p>Generic pins available in the QFN32 package.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV">MachXO2 256 pinout</a> (CSV)</li> </ul> >NAME <h3>Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000</h3> <p>Ports in the TQFP 144 package for MachXO2 1200, in addition to those available in csBGA 132 package.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV">MachXO2 1200 pinout</a> (CSV)</li> </ul> TQFP144- only pins TQFP144- only pins <h3>ELL-i I/O pins for Lattice MachXO2</h3> <p>Generic pins in the QFN32 package.</p> LVDS 3T LVDS 3C LVDS 1T LVDS 1C LVDS 2T LVDS 2C MCO Arduino D8 <h3>ELL-i I/O pins for Lattice MachXO2</h3> <p>The "QFN32 package" pins for ELL-i when TQFP144 package is used.</p> DDR2 TBD DDR2 TBD Memory CLK Memory NE1 Arduino D5 / JNRST Arduino D6 DDR2 CLK TBD DDR2 CLK TBD Memory AD2 Memory AD3 Memory AD4 Memory AD5 Memory AD6 Memory AD7 Memory AD14 Memory AD15 Memory A18 Memory A19 DDR2 TBD DDR2 TBD Memory AD8 Memory AD9 Memory AD16 Memory AD17 DDR2 TBD DDR2 TBD Memory AD0 Memory AD1 Memory AD10 Memory AD11 DDR2 TBD USART3_TX USART3_RX Memory A22 Memory A23 Memory A21 Memory NL/NADV Arduino D7 Arduino D9 SPI2_SS / CAN2_RX SPI2_SCK / CAN2_TX Memory NBL0 Memory NBL1 Memory NOE Memory NWE Arduino D0 Arduino D1 SPI2 MISO SPI2 MOSI LVDS 1T LVDS 1C DDR2 TBD Memory AD12 Memory AD13 DDR2 CLK TBD DDR2 CLK TBD DDR2 DQn DDR2 DQn DDR2 DQn DDR2 DQn DDR2 DQn DDR2 DQn DDR2 ADDR DDR2 ADDR DDR2 ADDR DDR2 ADDR DDR2 ADDR DDR2 ADDR DDR2 DQ0 DDR2 DQ0 DDR2 DQS0N check! DDR2 DQS0 check! DDR2 ADDR DDR2 ADDR DDR2 DQ0 DDR2 DQ0 DDR2 ADDR DDR2 ADDR DDR2 ADDR DDR2 ADDR LVDS 6T LVDS 6C MCO Arduino D2 LVDS 2T LVDS 2T LVDS 3T LVDS 3C LVDS 5T LVDS 5C Arduino D8 Memory NWAIT I2C2 SCL I2C2 SDA LVDS 4T LVDS 4B <h3>ELL-i functions for STM32F Porta D and F</h3> <p>STM32F051/030 64-pin TQFP version</p> Arduino D2 ELL-i LVDS 1T ELL-i LVDS 1C ELL-i LVDS 2T ELL-i LVDS 2C >NAME >VALUE Quad 2:1 high-speed CMOS TTL-compatible multiplexer <h3>Description</h3> <p> The Fairchild Switch FST3257 is a quad 2:1 high-speed CMOS TTL-compatible multiplexer / demultiplexer bus switch. </p> <p> The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. </p> <p> When /OE is LOW, the select pin connects the A port to the selected B port output. When /OE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports. </p> <p> <a HREF="www.fairchildsemi.com/ds/FS/FST3257.pdf"> Datasheet </a> </p> <p> Not reviewed </p> >NAME >VALUE >NAME >VALUE <b>STM32F-series MCU control pads</b> >NAME >VALUE <b>STM32F1-series MCU Power pads</b> >NAME >VALUE <h3>ENC424J600</h3> <p> The ENC424J600 and ENC624J600 are stand-alone, Fast Ethernet controllers with an industry standard Serial Peripheral Interface (SPI) or a flexible parallel interface. They are designed to serve as an Ethernet network interface for any microcontroller equipped with SPI or a standard parallel port. </p> <p> This is 44 pin version of device, <a href="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf">Datasheet</a> </p> <p> Not reviewed </p> >NAME >VALUE <h3>Small Footprint RMII 10/100 Ethernet Transceiver</h3> <ul> <li><a href="http://media.digikey.com/pdf/Data%20Sheets/SMSC/LAN8720.pdf">Datasheet</a></li> <li>Mouser: <a href="">886-LAN8720AI-CP</a></li> </ul> <h3>STM32F427 / 429 in LQFP144 or WLCSP143 package.</h3> <p>STM32F4-series Cortex-M4 microcontroller in a 144 or 143 lead package.</p> <ul> <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00071990.pdf">Datasheet (DM00071990.pdf)</li>. </ul> <h3>STM32F427 / 429 in LQFP100 package.</h3> <p>STM32F4-series Cortex-M4 microcontroller in a 100 lead package.</p> <ul> <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00071990.pdf">Datasheet (DM00071990.pdf)</li>. </ul> <h3>STM32F051 in LQPF48 package.</h3> <p>STM32F0-series Cortex-M0 microcontroller in a 48 lead package.</p> <ul> <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00039193.pdf">Datasheet</a> (DM00039193.pdf)</li>. </ul> <h3>STM32F051 in LQPF64 package.</h3> <p>STM32F0-series Cortex-M0 microcontroller in 64 lead package.</p> <ul> <li><a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00039193.pdf">Datasheet</a> (DM00039193.pdf)</li>. </ul> <h3> MachXO2-256 in csBGA132 or TQFP144 package.</h3> <p>Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. </ul> <h3> MachXO2-1200 in csBGA132 or TQFP144 package.</h3> <p>Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. </ul> <h3> MachXO2-2000 in csBGA132 or TQFP144 package.</h3> <p>Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. </ul> <h3>STM32F427 / 429 ELL-i functions.</h3> <p>This device contains a number of pseudo-symbols, meant to be used with a real STM32F42x MCU. The pseudo-symbols list the ELL-i project functions for the STM32F4 MCU pins.</p> <ul> <li>TBD (a link to the relevant design document)</li>. </ul> <h3>MachXO2 2000 ELL-i functions.</h3> <p>This device contains a number of pseudo-symbols, meant to be used with a real MachXO2-2000 FPGA. The pseudo-symbols list the ELL-i project functions for the 132/144 pins FPGA package.</p> <ul> <li>TBD (a link to the relevant design document)</li>. </ul> <h3>MachXO2-256 in 32-pin QFN package.</h3> <p>Lattice MachXO2-series FPGA in a 32-pin QFN package, 0.5 mm pitch.</p> <ul> <li><a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf">Datasheet</a> (DS1035)</li>. </ul> <h3>STM32F051/030 ELL-i functions.</h3> <p>This device contains a number of pseudo-symbols, meant to be used with a real STM32F0 MCU. The pseudo-symbols list the ELL-i project functions for the STM32F0 MCU pins in a 64-pin package.</p> <ul> <li>TBD (a link to the relevant design document)</li>. </ul> Stand-Alone 10/100 Ethernet Controller <h3>MachXO2 256 QFN32 ELL-i functions.</h3> <p>This device contains a pseudo-symbols, meant to be used with a corresponding MachXO2-256 FPGA device. The pseudo-symbols list the ELL-i project extra functions for the 32 pins FPGA package. Most of the functions in the QFN32 package are predefined by Lattice, though overrideable by a user design.</p> <ul> <li>TBD (a link to the relevant design document)</li>. </ul> <p> Quad 2:1 Multiplexer / Demultiplexer Bus Switch </p> STM32F103 Medium Density 64pin LQFP <br><br> <a href="http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00161566.pdf">Datasheet</a> STM32F103 Medium Density 64pin LQFP <br><br> <a href="http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00161566.pdf">Datasheet</a> <h3>ENC424J600</h3> <p> The ENC424J600 and ENC624J600 are stand-alone, Fast Ethernet controllers with an industry standard Serial Peripheral Interface (SPI) or a flexible parallel interface. They are designed to serve as an Ethernet network interface for any microcontroller equipped with SPI or a standard parallel port </p> <p> Not reviewed. <a href ="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf">Datasheet</a> </p> Since Version 6.2.2 text objects can contain more than one line, which will not be processed correctly with this version.