/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.0.99.2 */
/* Module Version: 5.4 */
/* Tue Jan 30 17:35:12 2018 */

/* parameterized module instance */
codeROM __ (.Address( ), .OutClock( ), .OutClockEn( ), .Reset( ), .Q( ));