--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.9.0.99.2
Wed Jul 26 13:46:07 2017
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design file: top
Device,speed: LAMXO256C,M
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "fclk_c" 318.066000 MHz ;
10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.281ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/bitCounter_154__i0 (from fclk_c +)
Destination: FF Data in myIwm/bitCounter_154__i0 (to fclk_c +)
Delay: 0.264ns (47.7% logic, 52.3% route), 1 logic levels.
Constraint Details:
0.264ns physical path delay myIwm/SLICE_33 to myIwm/SLICE_33 meets
-0.017ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.017ns) by 0.281ns
Physical Path Details:
Data path myIwm/SLICE_33 to myIwm/SLICE_33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R7C5B.CLK to R7C5B.Q0 myIwm/SLICE_33 (from fclk_c)
ROUTE 4 0.138 R7C5B.Q0 to R7C5B.M0 myIwm/bitCounter_0 (to fclk_c)
--------
0.264 (47.7% logic, 52.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C5B.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C5B.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.281ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/rddataSync_i0 (from fclk_c +)
Destination: FF Data in myIwm/rddataSync_i1 (to fclk_c +)
Delay: 0.264ns (47.7% logic, 52.3% route), 1 logic levels.
Constraint Details:
0.264ns physical path delay myIwm/SLICE_38 to myIwm/SLICE_38 meets
-0.017ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.017ns) by 0.281ns
Physical Path Details:
Data path myIwm/SLICE_38 to myIwm/SLICE_38:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R5C3D.CLK to R5C3D.Q0 myIwm/SLICE_38 (from fclk_c)
ROUTE 7 0.138 R5C3D.Q0 to R5C3D.M1 myIwm/rddataSync_0 (to fclk_c)
--------
0.264 (47.7% logic, 52.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_38:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R5C3D.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_38:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R5C3D.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/bitCounter_154__i2 (from fclk_c +)
Destination: FF Data in myIwm/bitCounter_154__i2 (to fclk_c +)
Delay: 0.331ns (60.4% logic, 39.6% route), 2 logic levels.
Constraint Details:
0.331ns physical path delay myIwm/SLICE_3 to myIwm/SLICE_3 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.008ns) by 0.339ns
Physical Path Details:
Data path myIwm/SLICE_3 to myIwm/SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R7C5A.CLK to R7C5A.Q1 myIwm/SLICE_3 (from fclk_c)
ROUTE 2 0.131 R7C5A.Q1 to R7C5A.A1 myIwm/bitCounter_2
CTOF_DEL --- 0.074 R7C5A.A1 to R7C5A.F1 myIwm/SLICE_3
ROUTE 1 0.000 R7C5A.F1 to R7C5A.DI1 myIwm/n18 (to fclk_c)
--------
0.331 (60.4% logic, 39.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C5A.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C5A.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/bitCounter_154__i1 (from fclk_c +)
Destination: FF Data in myIwm/bitCounter_154__i1 (to fclk_c +)
Delay: 0.331ns (60.4% logic, 39.6% route), 2 logic levels.
Constraint Details:
0.331ns physical path delay myIwm/SLICE_3 to myIwm/SLICE_3 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.008ns) by 0.339ns
Physical Path Details:
Data path myIwm/SLICE_3 to myIwm/SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R7C5A.CLK to R7C5A.Q0 myIwm/SLICE_3 (from fclk_c)
ROUTE 3 0.131 R7C5A.Q0 to R7C5A.A0 myIwm/bitCounter_1
CTOF_DEL --- 0.074 R7C5A.A0 to R7C5A.F0 myIwm/SLICE_3
ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 myIwm/n19 (to fclk_c)
--------
0.331 (60.4% logic, 39.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C5A.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C5A.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.340ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/bitCounter_154__i1 (from fclk_c +)
Destination: FF Data in myIwm/bitCounter_154__i2 (to fclk_c +)
Delay: 0.332ns (60.2% logic, 39.8% route), 2 logic levels.
Constraint Details:
0.332ns physical path delay myIwm/SLICE_3 to myIwm/SLICE_3 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.008ns) by 0.340ns
Physical Path Details:
Data path myIwm/SLICE_3 to myIwm/SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R7C5A.CLK to R7C5A.Q0 myIwm/SLICE_3 (from fclk_c)
ROUTE 3 0.132 R7C5A.Q0 to R7C5A.D1 myIwm/bitCounter_1
CTOF_DEL --- 0.074 R7C5A.D1 to R7C5A.F1 myIwm/SLICE_3
ROUTE 1 0.000 R7C5A.F1 to R7C5A.DI1 myIwm/n18 (to fclk_c)
--------
0.332 (60.2% logic, 39.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C5A.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C5A.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.342ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/bitTimer__i3 (from fclk_c +)
Destination: FF Data in myIwm/bitTimer__i4 (to fclk_c +)
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
Constraint Details:
0.334ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_6 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
Physical Path Details:
Data path myIwm/SLICE_5 to myIwm/SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R7C4A.CLK to R7C4A.Q1 myIwm/SLICE_5 (from fclk_c)
ROUTE 9 0.134 R7C4A.Q1 to R7C4D.D0 myIwm/bitTimer_3
CTOF_DEL --- 0.074 R7C4D.D0 to R7C4D.F0 myIwm/SLICE_6
ROUTE 1 0.000 R7C4D.F0 to R7C4D.DI0 myIwm/n183 (to fclk_c)
--------
0.334 (59.9% logic, 40.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C4A.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C4D.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.342ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/clearBufferTimer_i0_i3 (from fclk_c +)
Destination: FF Data in myIwm/clearBufferTimer_i0_i3 (to fclk_c +)
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
Constraint Details:
0.334ns physical path delay myIwm/SLICE_13 to myIwm/SLICE_13 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
Physical Path Details:
Data path myIwm/SLICE_13 to myIwm/SLICE_13:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R5C2D.CLK to R5C2D.Q0 myIwm/SLICE_13 (from fclk_c)
ROUTE 4 0.134 R5C2D.Q0 to R5C2D.A0 myIwm/clearBufferTimer_3
CTOF_DEL --- 0.074 R5C2D.A0 to R5C2D.F0 myIwm/SLICE_13
ROUTE 1 0.000 R5C2D.F0 to R5C2D.DI0 myIwm/n105 (to fclk_c)
--------
0.334 (59.9% logic, 40.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_13:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R5C2D.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_13:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R5C2D.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.342ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/clearBufferTimer_i0_i2 (from fclk_c +)
Destination: FF Data in myIwm/clearBufferTimer_i0_i2 (to fclk_c +)
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
Constraint Details:
0.334ns physical path delay myIwm/SLICE_12 to myIwm/SLICE_12 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
Physical Path Details:
Data path myIwm/SLICE_12 to myIwm/SLICE_12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R5C2A.CLK to R5C2A.Q1 myIwm/SLICE_12 (from fclk_c)
ROUTE 5 0.134 R5C2A.Q1 to R5C2A.A1 myIwm/clearBufferTimer_2
CTOF_DEL --- 0.074 R5C2A.A1 to R5C2A.F1 myIwm/SLICE_12
ROUTE 1 0.000 R5C2A.F1 to R5C2A.DI1 myIwm/n106 (to fclk_c)
--------
0.334 (59.9% logic, 40.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R5C2A.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R5C2A.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.342ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/bitTimer__i5 (from fclk_c +)
Destination: FF Data in myIwm/bitTimer__i5 (to fclk_c +)
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
Constraint Details:
0.334ns physical path delay myIwm/SLICE_6 to myIwm/SLICE_6 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
Physical Path Details:
Data path myIwm/SLICE_6 to myIwm/SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R7C4D.CLK to R7C4D.Q1 myIwm/SLICE_6 (from fclk_c)
ROUTE 5 0.134 R7C4D.Q1 to R7C4D.D1 myIwm/bitTimer_5
CTOF_DEL --- 0.074 R7C4D.D1 to R7C4D.F1 myIwm/SLICE_6
ROUTE 1 0.000 R7C4D.F1 to R7C4D.DI1 myIwm/n184 (to fclk_c)
--------
0.334 (59.9% logic, 40.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C4D.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R7C4D.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.342ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q myIwm/bitTimer__i1 (from fclk_c +)
Destination: FF Data in myIwm/bitTimer__i1 (to fclk_c +)
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
Constraint Details:
0.334ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_4 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
Physical Path Details:
Data path myIwm/SLICE_4 to myIwm/SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R6C4D.CLK to R6C4D.Q1 myIwm/SLICE_4 (from fclk_c)
ROUTE 8 0.134 R6C4D.Q1 to R6C4D.A1 myIwm/bitTimer_1
CTOF_DEL --- 0.074 R6C4D.A1 to R6C4D.F1 myIwm/SLICE_4
ROUTE 1 0.000 R6C4D.F1 to R6C4D.DI1 myIwm/n180 (to fclk_c)
--------
0.334 (59.9% logic, 40.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path fclk to myIwm/SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R6C4D.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path fclk to myIwm/SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.333 36.PADDI to R6C4D.CLK fclk_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "fclk_c" 318.066000 MHz ; | 0.000 ns| 0.281 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 3 clocks:
Clock Domain: fclk_c Source: fclk.PAD Loads: 24
Covered under: FREQUENCY NET "fclk_c" 318.066000 MHz ;
Data transfers from:
Clock Domain: _devsel_c Source: _devsel.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: _devsel_c Source: _devsel.PAD Loads: 11
No transfer within this clock domain is found
Clock Domain: _iosel_c Source: _iosel.PAD Loads: 2
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 841 paths, 1 nets, and 319 connections (64.84% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 10 (setup), 0 (hold)
Score: 59154 (setup), 0 (hold)
Cumulative negative slack: 59154 (59154+0)