-------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Thu Jul 27 11:14:19 2017 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: codeROM Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 1000.000000 -name clk0 [get_nets OutClock_c] 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets OutClock_c] | -| -| 0 | | | -------------------------------------------------------------------------------- All constraints were met. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 0 paths, 0 nets, and 2 connections (5.6% coverage) Peak memory: 48201728 bytes, TRCE: 1507328 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs