PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Thu Feb 22 10:56:39 2018
C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f liron_fpgatop.p2t
liron_fpgatop_map.ncd liron_fpgatop.dir liron_fpgatop.prf -gui -msgset
C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
Preference file: liron_fpgatop.prf.
Cost Table Summary
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 - - - - 05 Complete
* : Design saved.
Total (real) run time for 1-seed: 5 secs
par done!
Lattice Place and Route Report for Design "liron_fpgatop_map.ncd"
Thu Feb 22 10:56:39 2018
Best Par Run
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF liron_fpgatop_map.ncd liron_fpgatop.dir/5_1.ncd liron_fpgatop.prf
Preference file: liron_fpgatop.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file liron_fpgatop_map.ncd.
Design name: top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 52+4(JTAG)/108 52% used
52+4(JTAG)/80 70% bonded
SLICE 58/640 9% used
GSR 1/1 100% used
EBR 4/7 57% used
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
Number of Signals: 193
Number of Connections: 582
Pin Constraint Summary:
52 out of 52 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
fclk_c (driver: fclk, clk load #: 27)
The following 1 signal is selected to use the secondary clock routing resources:
_devsel_c (driver: _devsel, clk load #: 8, sr load #: 0, ce load #: 0)
Signal n440_c is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 43211.
Finished Placer Phase 1. REAL time: 3 secs
Starting Placer Phase 2.
.
Placer score = 43211
Finished Placer Phase 2. REAL time: 3 secs
Clock Report
Global Clock Resources:
CLK_PIN : 2 out of 8 (25%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Quadrants All (TL, TR, BL, BR) - Global Clocks:
PRIMARY "fclk_c" from comp "fclk" on CLK_PIN site "63 (PR5C)", clk load = 27
SECONDARY "_devsel_c" from comp "_devsel" on CLK_PIN site "34 (PB9A)", clk load = 8, ce load = 0, sr load = 0
PRIMARY : 1 out of 8 (12%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
52 + 4(JTAG) out of 108 (51.9%) PIO sites used.
52 + 4(JTAG) out of 80 (70.0%) bonded PIO sites used.
Number of PIO comps: 52; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 12 / 19 ( 63%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
| 2 | 12 / 20 ( 60%) | 3.3V | - |
| 3 | 8 / 20 ( 40%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 2 secs
Dumping design to file liron_fpgatop.dir/5_1.ncd.
-----------------------------------------------------------------
INFO - par: ASE feature is off due to non timing-driven settings.
-----------------------------------------------------------------
0 connections routed; 582 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 4 secs
Start NBR router at 10:56:43 02/22/18
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 10:56:43 02/22/18
Start NBR section for initial routing at 10:56:43 02/22/18
Level 4, iteration 1
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 10:56:43 02/22/18
Level 4, iteration 1
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
Start NBR section for re-routing at 10:56:43 02/22/18
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
Start NBR section for post-routing at 10:56:43 02/22/18
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : <n/a>
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 3 secs
Total REAL time: 4 secs
Completely routed.
End of route. 582 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file liron_fpgatop.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 3 secs
Total REAL time to completion: 5 secs
par done!
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.