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<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
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--------------------------------------------------------------------------------
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Lattice Synthesis Timing Report, Version
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Thu Oct 05 12:19:47 2017
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Design: blink
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Constraint file:
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Report level: verbose report, limited to 3 items per constraint
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 1000.000000 -name clk0 [get_nets clk]
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241 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 994.476ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK led_timer_9_10__i0 (from clk +)
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Destination: FD1S3AX D led_timer_9_10__i19 (to clk +)
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Delay: 5.364ns (61.2% logic, 38.8% route), 12 logic levels.
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Constraint Details:
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5.364ns data_path led_timer_9_10__i0 to led_timer_9_10__i19 meets
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1000.000ns delay constraint less
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0.160ns L_S requirement (totaling 999.840ns) by 994.476ns
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Path Details: led_timer_9_10__i0 to led_timer_9_10__i19
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q led_timer_9_10__i0 (from clk)
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Route 1 e 0.941 n21
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A1_TO_FCO --- 0.827 A[2] to COUT led_timer_9_10_add_4_1
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Route 1 e 0.020 n135
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_3
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Route 1 e 0.020 n136
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_5
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Route 1 e 0.020 n137
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_7
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Route 1 e 0.020 n138
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_9
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Route 1 e 0.020 n139
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_11
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Route 1 e 0.020 n140
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_13
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Route 1 e 0.020 n141
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_15
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Route 1 e 0.020 n142
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_17
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Route 1 e 0.020 n143
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_19
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Route 1 e 0.020 n144
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FCI_TO_F --- 0.598 CIN to S[2] led_timer_9_10_add_4_21
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Route 1 e 0.941 n91
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--------
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5.364 (61.2% logic, 38.8% route), 12 logic levels.
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Passed: The following path meets requirements by 994.476ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK led_timer_9_10__i0 (from clk +)
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Destination: FD1S3AX D led_timer_9_10__i20 (to clk +)
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Delay: 5.364ns (61.2% logic, 38.8% route), 12 logic levels.
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Constraint Details:
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5.364ns data_path led_timer_9_10__i0 to led_timer_9_10__i20 meets
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1000.000ns delay constraint less
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0.160ns L_S requirement (totaling 999.840ns) by 994.476ns
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Path Details: led_timer_9_10__i0 to led_timer_9_10__i20
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q led_timer_9_10__i0 (from clk)
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Route 1 e 0.941 n21
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A1_TO_FCO --- 0.827 A[2] to COUT led_timer_9_10_add_4_1
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Route 1 e 0.020 n135
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_3
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Route 1 e 0.020 n136
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_5
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Route 1 e 0.020 n137
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_7
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Route 1 e 0.020 n138
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_9
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Route 1 e 0.020 n139
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_11
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Route 1 e 0.020 n140
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_13
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Route 1 e 0.020 n141
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_15
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Route 1 e 0.020 n142
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_17
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Route 1 e 0.020 n143
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_19
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Route 1 e 0.020 n144
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FCI_TO_F --- 0.598 CIN to S[2] led_timer_9_10_add_4_21
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Route 1 e 0.941 n90
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--------
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5.364 (61.2% logic, 38.8% route), 12 logic levels.
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Passed: The following path meets requirements by 994.653ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK led_timer_9_10__i0 (from clk +)
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Destination: FD1S3AX D led_timer_9_10__i17 (to clk +)
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Delay: 5.187ns (60.2% logic, 39.8% route), 11 logic levels.
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Constraint Details:
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5.187ns data_path led_timer_9_10__i0 to led_timer_9_10__i17 meets
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1000.000ns delay constraint less
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0.160ns L_S requirement (totaling 999.840ns) by 994.653ns
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Path Details: led_timer_9_10__i0 to led_timer_9_10__i17
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q led_timer_9_10__i0 (from clk)
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Route 1 e 0.941 n21
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A1_TO_FCO --- 0.827 A[2] to COUT led_timer_9_10_add_4_1
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Route 1 e 0.020 n135
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_3
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Route 1 e 0.020 n136
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_5
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Route 1 e 0.020 n137
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_7
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Route 1 e 0.020 n138
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_9
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Route 1 e 0.020 n139
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_11
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Route 1 e 0.020 n140
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_13
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Route 1 e 0.020 n141
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_15
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Route 1 e 0.020 n142
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FCI_TO_FCO --- 0.157 CIN to COUT led_timer_9_10_add_4_17
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Route 1 e 0.020 n143
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FCI_TO_F --- 0.598 CIN to S[2] led_timer_9_10_add_4_19
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Route 1 e 0.941 n93
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--------
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5.187 (60.2% logic, 39.8% route), 11 logic levels.
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Report: 5.524 ns is the maximum delay for this constraint.
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<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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create_clock -period 1000.000000 -name | | |
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clk0 [get_nets clk] | 1000.000 ns| 5.524 ns| 12
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--------------------------------------------------------------------------------
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All constraints were met.
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<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
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---------------
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Timing errors: 0 Score: 0
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Constraints cover 241 paths, 53 nets, and 73 connections (98.6% coverage)
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Peak memory: 51392512 bytes, TRCE: 1622016 bytes, DLYMAN: 0 bytes
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CPU_TIME_REPORT: 0 secs
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