205 lines
5.2 KiB
Plaintext
205 lines
5.2 KiB
Plaintext
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Lattice Mapping Report File for Design Module 'blink'
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Design Information
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------------------
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Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
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yellowstone_blink_yellowstone_blink.ngd -o
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yellowstone_blink_yellowstone_blink_map.ncd -pr
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yellowstone_blink_yellowstone_blink.prf -mp
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yellowstone_blink_yellowstone_blink.mrp -lpf C:/Users/chamberlin/Documents/
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Liron/yellowstone_blink/yellowstone_blink_yellowstone_blink.lpf -lpf
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C:/Users/chamberlin/Documents/Liron/yellowstone_blink.lpf -c 0 -gui
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Target Vendor: LATTICE
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Target Device: LCMXO2-1200HCTQFP100
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Target Performance: 4
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Mapper: xo2c00, version: Diamond (64-bit) 3.9.0.99.2
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Mapped on: 10/05/17 12:20:37
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Design Summary
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--------------
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Number of registers: 21 out of 1520 (1%)
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PFU registers: 21 out of 1280 (2%)
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PIO registers: 0 out of 240 (0%)
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Number of SLICEs: 12 out of 640 (2%)
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SLICEs as Logic/ROM: 12 out of 640 (2%)
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SLICEs as RAM: 0 out of 480 (0%)
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SLICEs as Carry: 11 out of 640 (2%)
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Number of LUT4s: 23 out of 1280 (2%)
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Number used as logic LUTs: 1
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Number used as distributed RAM: 0
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Number used as ripple logic: 22
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Number used as shift registers: 0
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Number of PIO sites used: 2 + 4(JTAG) out of 80 (8%)
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Number of block RAMs: 0 out of 7 (0%)
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Number of GSRs: 0 out of 1 (0%)
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EFB used : No
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JTAG used : No
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Readback used : No
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Oscillator used : Yes
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Startup used : No
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POR : On
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Bandgap : On
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Number of Power Controller: 0 out of 1 (0%)
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Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
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Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
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Number of DCCA: 0 out of 8 (0%)
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Number of DCMA: 0 out of 2 (0%)
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Number of PLLs: 0 out of 1 (0%)
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Number of DQSDLLs: 0 out of 2 (0%)
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Number of CLKDIVC: 0 out of 4 (0%)
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Number of ECLKSYNCA: 0 out of 4 (0%)
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Number of ECLKBRIDGECS: 0 out of 2 (0%)
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Notes:-
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1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
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distributed RAMs) + 2*(Number of ripple logic)
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2. Number of logic LUT4s does not include count of distributed RAM and
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ripple logic.
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Number of clocks: 1
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Net clk: 11 loads, 11 rising, 0 falling (Driver: internal_oscillator_inst )
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Page 1
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Design: blink Date: 10/05/17 12:20:37
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Design Summary (cont)
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---------------------
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Number of Clock Enables: 0
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Number of LSRs: 0
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Number of nets driven by tri-state buffers: 0
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Top 10 highest fanout non-clock nets:
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Net pin_led_c_20: 2 loads
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Net n143: 1 loads
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Net n144: 1 loads
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Net n2: 1 loads
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Net n3: 1 loads
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Net n4: 1 loads
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Net n90: 1 loads
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Net n91: 1 loads
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Net n93: 1 loads
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Net VCC_net: 1 loads
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Number of warnings: 0
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Number of errors: 0
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Design Errors/Warnings
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----------------------
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No errors or warnings present.
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IO (PIO) Attributes
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-------------------
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+---------------------+-----------+-----------+------------+
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| IO Name | Direction | Levelmode | IO |
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| | | IO_TYPE | Register |
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+---------------------+-----------+-----------+------------+
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| pin_led | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| en_245 | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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Removed logic
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-------------
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Block GSR_INST undriven or does not drive anything - clipped.
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Signal GND_net undriven or does not drive anything - clipped.
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Signal led_timer_9_10_add_4_1/S0 undriven or does not drive anything - clipped.
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Signal led_timer_9_10_add_4_1/CI undriven or does not drive anything - clipped.
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Signal led_timer_9_10_add_4_21/CO undriven or does not drive anything - clipped.
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Block i1 was optimized away.
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Memory Usage
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------------
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Page 2
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Design: blink Date: 10/05/17 12:20:37
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OSC Summary
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-----------
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OSC 1: Pin/Node Value
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OSC Instance Name: internal_oscillator_inst
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OSC Type: OSCH
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STDBY Input: NONE
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OSC Output: NODE clk
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OSC Nominal Frequency (MHz): 2.08
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ASIC Components
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---------------
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Instance Name: internal_oscillator_inst
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Type: OSCH
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Run Time and Memory Usage
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-------------------------
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Total CPU Time: 0 secs
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Total REAL Time: 0 secs
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Peak Memory Usage: 36 MB
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Page 3
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights
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reserved.
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