fpga-disk-controller/yellowstone_blink/yellowstone_blink_yellowsto...

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<HEAD><TITLE>Place & Route Report</TITLE>
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Thu Oct 05 12:20:38 2017
C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f
yellowstone_blink_yellowstone_blink.p2t
yellowstone_blink_yellowstone_blink_map.ncd
yellowstone_blink_yellowstone_blink.dir yellowstone_blink_yellowstone_blink.prf
-gui
Preference file: yellowstone_blink_yellowstone_blink.prf.
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 476.505 0 0.377 0 05 Complete
* : Design saved.
Total (real) run time for 1-seed: 5 secs
par done!
Lattice Place and Route Report for Design &quot;yellowstone_blink_yellowstone_blink_map.ncd&quot;
Thu Oct 05 12:20:38 2017
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF yellowstone_blink_yellowstone_blink_map.ncd yellowstone_blink_yellowstone_blink.dir/5_1.ncd yellowstone_blink_yellowstone_blink.prf
Preference file: yellowstone_blink_yellowstone_blink.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file yellowstone_blink_yellowstone_blink_map.ncd.
Design name: blink
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file &apos;xo2c1200.nph&apos; in environment: C:/lscc/diamond/3.9_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 2+4(JTAG)/108 6% used
2+4(JTAG)/80 8% bonded
SLICE 12/640 1% used
OSC 1/1 100% used
Number of Signals: 54
Number of Connections: 65
Pin Constraint Summary:
2 out of 2 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
clk (driver: internal_oscillator_inst, clk load #: 11)
No signal is selected as secondary clock.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
................
Placer score = 492.
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 382
Finished Placer Phase 2. REAL time: 4 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Quadrants All (TL, TR, BL, BR) - Global Clocks:
PRIMARY &quot;clk&quot; from OSC on comp &quot;internal_oscillator_inst&quot; on site &quot;OSC&quot;, clk load = 11
PRIMARY : 1 out of 8 (12%)
SECONDARY: 0 out of 8 (0%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
2 + 4(JTAG) out of 108 (5.6%) PIO sites used.
2 + 4(JTAG) out of 80 (7.5%) bonded PIO sites used.
Number of PIO comps: 2; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+---------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+---------------+------------+-----------+
| 0 | 0 / 19 ( 0%) | - | - |
| 1 | 0 / 21 ( 0%) | - | - |
| 2 | 1 / 20 ( 5%) | 3.3V | - |
| 3 | 1 / 20 ( 5%) | 3.3V | - |
+----------+---------------+------------+-----------+
Total placer CPU time: 4 secs
Dumping design to file yellowstone_blink_yellowstone_blink.dir/5_1.ncd.
0 connections routed; 65 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 5 secs
Start NBR router at 12:20:43 10/05/17
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 12:20:43 10/05/17
Start NBR section for initial routing at 12:20:43 10/05/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 476.505ns/0.000ns; real time: 5 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 12:20:43 10/05/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 476.505ns/0.000ns; real time: 5 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 12:20:43 10/05/17
Start NBR section for re-routing at 12:20:43 10/05/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 476.505ns/0.000ns; real time: 5 secs
Start NBR section for post-routing at 12:20:43 10/05/17
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : 476.505ns
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 5 secs
Total REAL time: 5 secs
Completely routed.
End of route. 65 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file yellowstone_blink_yellowstone_blink.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 476.505
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.377
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 5 secs
Total REAL time to completion: 5 secs
par done!
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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