fpga-disk-controller/lattice/.spreadsheet_view.ini

77 lines
1.5 KiB
INI

[General]
pin_sort_type=0
pin_sort_ascending=true
sig_sort_type=0
sig_sort_ascending=true
active_Sheet=Port Assignments
[Port%20Assignments]
Name="183,0"
Group%20By="84,1"
Pin="50,2"
BANK="62,3"
IO_TYPE="80,4"
PULLMODE="92,5"
DRIVE="67,9"
SLEWRATE="92,6"
OPENDRAIN="97,10"
Outload%20%28pF%29="103,11"
MaxSkew="87,14"
Clock%20Load%20Only="121,13"
sort_columns="BANK,Ascending"
BANK_VCC="90,7"
VREF="60,8"
CLAMP="71,12"
DIFFRESISTOR="114,15"
DIFFDRIVE="92,16"
HYSTERESIS="101,17"
SwitchingID="100,18"
Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
Power%20plane%20PCB%20noise%20%28mV%29="190,20"
SSO%20Allowance%28%25%29="138,21"
[Pin%20Assignments]
Pin="90,0"
Pad%20Name="89,1"
Dual%20Function="158,2"
Polarity="77,3"
BANK="0,4"
IO_TYPE="80,5"
Signal%20Name="102,6"
Signal%20Type="98,7"
sort_columns="Pin,Ascending"
BANK_VCC="90,8"
[Clock%20Resource]
Clock%20Type="100,ELLIPSIS"
Clock%20Name="100,ELLIPSIS"
Selection="100,ELLIPSIS"
[Global%20Preferences]
Preference%20Name="230,ELLIPSIS"
Preference%20Value="236,ELLIPSIS"
[Cell%20Mapping]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Din\Dout="100,ELLIPSIS"
PIO%20Register="100,ELLIPSIS"
[Route%20Priority]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Prioritize="100,ELLIPSIS"
[Timing%20Preferences]
Preference%20Name="129,ELLIPSIS"
Preference%20Value="104,ELLIPSIS"
Preference%20Unit="98,ELLIPSIS"
[Group]
Group%20Type\Name="134,ELLIPSIS"
Value="38,ELLIPSIS"
[Misc%20Preferences]
Preference%20Name="162,ELLIPSIS"
Preference%20Value="104,ELLIPSIS"