38 lines
1.0 KiB
Verilog
38 lines
1.0 KiB
Verilog
`timescale 1 ns / 1 ps
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module addrDecoder(
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input [11:0] addr,
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//input _devsel, // 16 bytes (for IWM)
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input fclk,
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input _iostrobe, // shared 2K space
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input _iosel, // card-specific 256 bytes
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input _reset,
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output _romoe, // 0 if the card's ROM should drive its output right now
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output reg romExpansionActive // 1 if the Yellowstone card's ROM is the currently selected slot ROM
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);
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wire histrobe = ~_iostrobe & (addr == 12'hFFF);
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/*reg [1:0] histrobeHistory;
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reg [1:0] ioselHistory;
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always @(posedge fclk) begin
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histrobeHistory <= { histrobeHistory[0], histrobe };
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ioselHistory <= { ioselHistory[0], _iosel };
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end*/
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//wire clearActive = histrobe || ~_reset;
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//always @(posedge fclk or posedge clearActive) begin
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always @(posedge fclk) begin
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//if (clearActive)
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//if (histrobeHistory == 2'b11)
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if (histrobe)
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romExpansionActive <= 0;
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//else if (ioselHistory == 2'b00)
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else if (~_iosel)
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romExpansionActive <= 1;
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end
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assign _romoe = ~(~_iosel || (romExpansionActive && ~_iostrobe));
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endmodule
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