52 lines
1.0 KiB
Plaintext
52 lines
1.0 KiB
Plaintext
[Device]
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Family=machxo2
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PartType=LCMXO2-1200HC
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PartName=LCMXO2-1200HC-4TG100C
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SpeedGrade=4
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Package=TQFP100
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OperatingCondition=COM
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Status=S
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[IP]
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VendorName=Lattice Semiconductor Corporation
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CoreType=LPM
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CoreStatus=Demo
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CoreName=ROM
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CoreRevision=5.4
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ModuleName=codeROM
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SourceFormat=Verilog HDL
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ParameterFileVersion=1.0
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Date=01/30/2018
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Time=17:35:12
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[Parameters]
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Verilog=1
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VHDL=0
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EDIF=1
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Destination=Synplicity
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Expression=BusA(0 to 7)
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Order=Big Endian [MSB:LSB]
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IO=0
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Address=4096
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Data=8
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enByte=0
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ByteSize=9
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OutputEn=1
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ClockEn=0
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Optimization=Area
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Reset=Sync
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Reset1=Sync
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Init=0
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MemFile=c:/users/chamberlin/documents/liron/rom-full-4k.mem
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MemFormat=hex
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EnECC=0
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Pipeline=0
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Write=Normal
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init_data=0
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[FilesGenerated]
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c:/users/chamberlin/documents/liron/rom-full-4k.mem=mem
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[Command]
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cmd_line= -w -n codeROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-1200HC -addr_width 12 -data_width 8 -num_words 4096 -outdata REGISTERED -cascade 11 -resetmode SYNC -sync_reset -memfile "c:/users/chamberlin/documents/liron/rom-full-4k.mem" -memformat hex
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