21 lines
6.8 KiB
HTML
21 lines
6.8 KiB
HTML
<HTML> <HEAD><TITLE></TITLE> <STYLE TYPE="text/css"> <!-- body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; } --> </STYLE> </HEAD> <BODY> <PRE>Setting log file to 'C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/hdla_gen_hierarchy.html'.
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Starting: parse design source files
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(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
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(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/lattice/top.v
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(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v
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(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/lattice/iwm.v
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(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v
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INFO - C:/Users/chamberlin/Documents/Liron/lattice/top.v(2,8-2,11) (VERI-1018) compiling module top
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INFO - C:/Users/chamberlin/Documents/Liron/lattice/top.v(2,1-112,10) (VERI-9000) elaborating module 'top'
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INFO - C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v(2,1-37,10) (VERI-9000) elaborating module 'addrDecoder_uniq_1'
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INFO - C:/Users/chamberlin/Documents/Liron/lattice/iwm.v(2,1-296,10) (VERI-9000) elaborating module 'iwm_uniq_1'
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INFO - C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v(8,1-295,10) (VERI-9000) elaborating module 'codeROM_uniq_1'
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INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1'
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INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2'
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INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_3'
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INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_4'
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INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
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INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
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Done: design load finished with (0) errors, and (0) warnings
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</PRE></BODY></HTML> |