fpga-disk-controller/lattice/fpgatop/liron_fpgatop.dir/5_1_par.asd

35 lines
823 B
Common Lisp

[ActiveSupport PAR]
; Global primary clocks
GLOBAL_PRIMARY_USED = 1;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = fclk_c;
GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
GLOBAL_PRIMARY_0_LOADNUM = 27;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 1;
; Global secondary clock #0
GLOBAL_SECONDARY_0_SIGNALNAME = _devsel_c;
GLOBAL_SECONDARY_0_DRIVERTYPE = CLK_PIN;
GLOBAL_SECONDARY_0_LOADNUM = 13;
GLOBAL_SECONDARY_0_SIGTYPE = CLK;
; I/O Bank 0 Usage
BANK_0_USED = 12;
BANK_0_AVAIL = 19;
BANK_0_VCCIO = 3.3V;
BANK_0_VREF1 = NA;
; I/O Bank 1 Usage
BANK_1_USED = 20;
BANK_1_AVAIL = 21;
BANK_1_VCCIO = 3.3V;
BANK_1_VREF1 = NA;
; I/O Bank 2 Usage
BANK_2_USED = 12;
BANK_2_AVAIL = 20;
BANK_2_VCCIO = 3.3V;
BANK_2_VREF1 = NA;
; I/O Bank 3 Usage
BANK_3_USED = 8;
BANK_3_AVAIL = 20;
BANK_3_VCCIO = 3.3V;
BANK_3_VREF1 = NA;