3 lines
305 B
Plaintext
3 lines
305 B
Plaintext
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
|
|
DRC detected 0 errors and 0 warnings.
|