From 65affd5d2554a6dfd425498b50bc1fd935d7b026 Mon Sep 17 00:00:00 2001 From: Christopher RYU Date: Thu, 9 Mar 2023 15:58:32 +0900 Subject: [PATCH 1/7] Add working PLD file and JED file generated therewith. --- gal/ssc-cr-2023030902.jed | 60 +++++++++++++++++++++++++++++++++++++++ gal/ssc_gal_wincupl.pld | 58 +++++++++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+) create mode 100644 gal/ssc-cr-2023030902.jed create mode 100755 gal/ssc_gal_wincupl.pld diff --git a/gal/ssc-cr-2023030902.jed b/gal/ssc-cr-2023030902.jed new file mode 100644 index 0000000..3577816 --- /dev/null +++ b/gal/ssc-cr-2023030902.jed @@ -0,0 +1,60 @@ + +CUPL(WM) 5.0a Serial# 60008009 +Device g22v10 Library DLIB-h-40-1 +Created Thu Mar 09 15:25:03 2023 +Name Simple Serial Card +Partno SSC0001 +Revision 01 +Date 3/9/23 +Designer Chris RYU +Company RyuCats +Assembly None +Location None +*QP24 +*QF5892 +*G0 +*F0 +*L00896 00000000000000000000000000001111 +*L00928 11111111111111111111111111111111 +*L00960 11111111111111111111101111111111 +*L00992 11111111111111111111000000000000 +*L01472 00000000000000000000000011111111 +*L01504 11111111111111111111111111111111 +*L01536 11111111111111111111011111111111 +*L01568 11111111110111110000000000000000 +*L02144 00000000000011111111111111111111 +*L02176 11111111111111111111111111111111 +*L02208 11111111111111111111011111111111 +*L02240 11111111111111111111111111111011 +*L02272 11111111111111110000000000000000 +*L02880 00000000000000000000000011111111 +*L02912 11111111111111111111111111111111 +*L02944 11111111111111111111111111111111 +*L02976 11110111111111111111111111111111 +*L03008 11111111101111111111111111110000 +*L03648 00001111111111111111111111111111 +*L03680 11111111111111111111111111111111 +*L03712 11111111111111111111011111111111 +*L03744 11111111111111111111101111111111 +*L03776 11111111000000000000000000000000 +*L04288 00000000000000000000000011111111 +*L04320 11111111111111111111111111111111 +*L04352 11111111111111110111011111111111 +*L04384 11111111110111110000000000000000 +*L04864 00000000000000000000111111111111 +*L04896 11111111111111111111111111111111 +*L04928 11111111111111110111111111111111 +*L04960 11011111111110111111111111111111 +*L04992 11111111111111111111111111111111 +*L05024 10111111111111111111011101110111 +*L05056 11110000000000000000000000000000 +*L05344 00000000000000000000000011111111 +*L05376 11111111111111111111111111111111 +*L05408 11111111111111111111111111111111 +*L05440 11111101111111111111111101111111 +*L05472 11111111111111111111111111110000 +*L05792 00000000000000000000111111111111 +*L05824 11110101001101010011010000110011 +*L05856 00000011000000110000001100010000 +*C7DCD +*9CA3 \ No newline at end of file diff --git a/gal/ssc_gal_wincupl.pld b/gal/ssc_gal_wincupl.pld new file mode 100755 index 0000000..17400e5 --- /dev/null +++ b/gal/ssc_gal_wincupl.pld @@ -0,0 +1,58 @@ +Name Simple Serial Card; +Partno SSC0001; +Revision 01; +Date 3/9/23; +Designer Chris RYU; +Company RyuCats; +Location None; +Assembly None; +Device g22v10; + +/* Inputs */ + +Pin 1 = reset; +Pin 2 = CTS; +Pin 3 = io_C800; +Pin 4 = slot_select; +Pin 5 = io_slot_access; +Pin 6 = RW; +Pin 7 = A11; +Pin 8 = A10; +Pin 9 = A9; +Pin 10 = A8; +Pin 11 = A3; + +/* Outputs */ + +Pin 14 = rom_c800_enable; +Pin 15 = rom_latch; +Pin 16 = ls245_enable; +Pin 17 = eprom_a8; +Pin 18 = eprom_a9; +Pin 19 = eprom_a10; +Pin 20 = rom_enable; +Pin 21 = PHI2; +Pin 22 = d0; + +/* Latch (RS flip-flop) definition: + Q = (Q & RESET) # !SET; +*/ + +PHI2 = !slot_select; /* per schematic */ + +cf00_access = io_C800 # !A8 # !A9 # !A10; /* CF00 access, pull low */ + +/* + if either reset or cf00 access is pulled low, then rom_latch = 1 + if io_slot_access is 0, then rom_latch = 0 + if io_slot_access is 1, then rom_latch = no change +*/ +rom_latch = (rom_latch & io_slot_access) # !(reset & cf00_access); +rom_c800_enable = rom_latch # io_C800; /* enable if both pulled low */ + +ls245_enable = ( io_slot_access & rom_c800_enable & slot_select); /* c800 ? */ +rom_enable = (io_slot_access & rom_c800_enable); + +eprom_a8 = A8 # !A11; +eprom_a9 = A9 # !A11; +eprom_a10 = A10 # !A11; \ No newline at end of file From 286b063f417626d76775e02afda3527d55d8df72 Mon Sep 17 00:00:00 2001 From: Christopher RYU Date: Fri, 10 Mar 2023 06:38:33 +0900 Subject: [PATCH 2/7] Sync to tested version. --- gal/ssc_gal_wincupl.pld | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/gal/ssc_gal_wincupl.pld b/gal/ssc_gal_wincupl.pld index 17400e5..30e5e7b 100755 --- a/gal/ssc_gal_wincupl.pld +++ b/gal/ssc_gal_wincupl.pld @@ -32,7 +32,7 @@ Pin 18 = eprom_a9; Pin 19 = eprom_a10; Pin 20 = rom_enable; Pin 21 = PHI2; -Pin 22 = d0; + /* Latch (RS flip-flop) definition: Q = (Q & RESET) # !SET; @@ -40,14 +40,17 @@ Pin 22 = d0; PHI2 = !slot_select; /* per schematic */ -cf00_access = io_C800 # !A8 # !A9 # !A10; /* CF00 access, pull low */ +cf00_access = io_C800 # !(A8 & A9 & A10); /* CF00 access, pull low */ /* if either reset or cf00 access is pulled low, then rom_latch = 1 if io_slot_access is 0, then rom_latch = 0 if io_slot_access is 1, then rom_latch = no change */ + +/* Q = ROM_LATCH RESET = io_slot_access SET = (reset & cf00_access) */ rom_latch = (rom_latch & io_slot_access) # !(reset & cf00_access); + rom_c800_enable = rom_latch # io_C800; /* enable if both pulled low */ ls245_enable = ( io_slot_access & rom_c800_enable & slot_select); /* c800 ? */ @@ -55,4 +58,4 @@ rom_enable = (io_slot_access & rom_c800_enable); eprom_a8 = A8 # !A11; eprom_a9 = A9 # !A11; -eprom_a10 = A10 # !A11; \ No newline at end of file +eprom_a10 = A10 # !A11; From 2ef7327b4b858a6924b12c90a645cf281b35c923 Mon Sep 17 00:00:00 2001 From: Christopher RYU Date: Fri, 10 Mar 2023 06:40:10 +0900 Subject: [PATCH 3/7] CMOS logic for the bus transceiver appears to have issues with ROM decode. --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 90bec37..f11c8da 100644 --- a/README.md +++ b/README.md @@ -24,7 +24,7 @@ with what made the layout easier. ## Parts List -* A 74HCT245 octal bus transceiver (U1) +* A 74LS245 octal bus transceiver (non-TTL appears to have issues with the ROM address decode logic) (U1) * A 28C256 EEPROM (U2) * A 1.8432 MHz 5V oscillator (U3) * A 22V10 GAL (any speed or variety should work) (U4) From ff3dda28b0849b45ca3b33ddd21a38c861cef1a5 Mon Sep 17 00:00:00 2001 From: Christopher RYU Date: Fri, 10 Mar 2023 06:42:37 +0900 Subject: [PATCH 4/7] Add latest .jed --- gal/{ssc-cr-2023030902.jed => ssc-cr-2023030903.jed} | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) rename gal/{ssc-cr-2023030902.jed => ssc-cr-2023030903.jed} (95%) diff --git a/gal/ssc-cr-2023030902.jed b/gal/ssc-cr-2023030903.jed similarity index 95% rename from gal/ssc-cr-2023030902.jed rename to gal/ssc-cr-2023030903.jed index 3577816..b56a562 100644 --- a/gal/ssc-cr-2023030902.jed +++ b/gal/ssc-cr-2023030903.jed @@ -1,7 +1,7 @@  CUPL(WM) 5.0a Serial# 60008009 Device g22v10 Library DLIB-h-40-1 -Created Thu Mar 09 15:25:03 2023 +Created Fri Mar 10 06:33:40 2023 Name Simple Serial Card Partno SSC0001 Revision 01 @@ -57,4 +57,4 @@ Location None *L05824 11110101001101010011010000110011 *L05856 00000011000000110000001100010000 *C7DCD -*9CA3 \ No newline at end of file +*9C8B \ No newline at end of file From d5f54183a672a97d3cf61676efba2b9193161e24 Mon Sep 17 00:00:00 2001 From: Christopher RYU Date: Fri, 10 Mar 2023 07:29:55 +0900 Subject: [PATCH 5/7] Add patch mechanism for ROM. --- rom/Makefile | 5 +++++ rom/adtpro-patch-341-0065-B.xdelta | Bin 0 -> 162 bytes 2 files changed, 5 insertions(+) create mode 100644 rom/Makefile create mode 100644 rom/adtpro-patch-341-0065-B.xdelta diff --git a/rom/Makefile b/rom/Makefile new file mode 100644 index 0000000..e462b80 --- /dev/null +++ b/rom/Makefile @@ -0,0 +1,5 @@ +all: adtpro-patch-341-0065-B.bin + +adtpro-patch-341-0065-B.bin: adtpro-patch-341-0065-B.xdelta + xdelta3 -d -s 341-0065-B.bin adtpro-patch-341-0065-B.xdelta \ + adtpro-patch-341-0065-B.bin diff --git a/rom/adtpro-patch-341-0065-B.xdelta b/rom/adtpro-patch-341-0065-B.xdelta new file mode 100644 index 0000000000000000000000000000000000000000..5a62e717d246b0bed86eeafd7287c5c7c2a45d24 GIT binary patch literal 162 zcmcb1_y_|lle)2qp{{{}nW?UmZb4#6az<*3UQ%YBzCJ=6%x9gzz>q(IfsM^rXXf)} z>6PDKt(^Z#{I7XcL=*!9!+)Whj!X=Sj66Vg{|v`Dj0|GJQY_Le!mWj>!9FU+jj67| fO=>E}E!6_JweT~@YPXiOmIVedG-fqvH)#O?F-R_< literal 0 HcmV?d00001 From da10651ff22cb13976fa100dd986088b9bce5218 Mon Sep 17 00:00:00 2001 From: Christopher RYU Date: Sat, 11 Mar 2023 06:46:08 +0900 Subject: [PATCH 6/7] Snarf SSC ROM from mirror for patching. --- rom/Makefile | 19 ++++++++++++++---- ...-B.xdelta => adtpro-patch-341-0065.xdelta} | Bin 2 files changed, 15 insertions(+), 4 deletions(-) rename rom/{adtpro-patch-341-0065-B.xdelta => adtpro-patch-341-0065.xdelta} (100%) diff --git a/rom/Makefile b/rom/Makefile index e462b80..de4501c 100644 --- a/rom/Makefile +++ b/rom/Makefile @@ -1,5 +1,16 @@ -all: adtpro-patch-341-0065-B.bin +# Simple makefile to snarf the Apple SuperSerialCard ROM image and patch it +# for ADTPro bootstrapping -adtpro-patch-341-0065-B.bin: adtpro-patch-341-0065-B.xdelta - xdelta3 -d -s 341-0065-B.bin adtpro-patch-341-0065-B.xdelta \ - adtpro-patch-341-0065-B.bin +ROM_SOURCE = https://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Interface%20Cards/Serial/Apple%20II%20Super%20Serial%20Card/ROM%20Images/Apple%20II%20Super%20Serial%20Card%20ROM%20-%20341-0065-A.bin + +all: 341-0065.bin adtpro-patch-341-0065.bin + +adtpro-patch-341-0065.bin: adtpro-patch-341-0065.xdelta + xdelta3 -d -s 341-0065.bin adtpro-patch-341-0065.xdelta \ + adtpro-patch-341-0065.bin + +341-0065.bin: + curl -o 341-0065.bin $(ROM_SOURCE) + +clean: + rm -f 341-0065.bin adtpro-patch-341-0065.bin diff --git a/rom/adtpro-patch-341-0065-B.xdelta b/rom/adtpro-patch-341-0065.xdelta similarity index 100% rename from rom/adtpro-patch-341-0065-B.xdelta rename to rom/adtpro-patch-341-0065.xdelta From 66ba52f590238e73e7a12361bec6372b4d8ffef4 Mon Sep 17 00:00:00 2001 From: Christopher RYU Date: Sat, 11 Mar 2023 07:42:54 +0900 Subject: [PATCH 7/7] Note that JEDEC EPROMs also work. --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index f11c8da..44568ad 100644 --- a/README.md +++ b/README.md @@ -25,7 +25,7 @@ with what made the layout easier. ## Parts List * A 74LS245 octal bus transceiver (non-TTL appears to have issues with the ROM address decode logic) (U1) -* A 28C256 EEPROM (U2) +* A 28C256 EEPROM (28-pin JEDEC EPROMs such as the 27128 also work) (U2) * A 1.8432 MHz 5V oscillator (U3) * A 22V10 GAL (any speed or variety should work) (U4) * A W65C51N ACIA (U5)