commit 07afc4459e72709ada55e15101f2de32dbe50bb4 Author: Luca Ridarelli Date: Mon Jan 16 18:44:48 2017 +0100 First Commit diff --git a/The_Mill_Daughter_Board/PCB/the_mill.brd b/The_Mill_Daughter_Board/PCB/the_mill.brd new file mode 100644 index 0000000..907c179 --- /dev/null +++ b/The_Mill_Daughter_Board/PCB/the_mill.brd @@ -0,0 +1,616 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +OS9 +OFF + + + + + + + +<b>AVR Devices</b><p> +Configurable logic, microcontrollers, nonvolatile memories<p> +Based on the following sources:<p> +<ul> +<li>www.atmel.com +<li>CD-ROM : Configurable Logic Microcontroller Nonvolatile Memory +<li>CadSoft download site, www.cadsoft.de or www.cadsoftusa.com , file at90smcu_v400.zip +<li>avr.lbr +</ul> +<author>Revised by librarian@cadsoft.de</author> + + +<B>Dual In Line</B> + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<b>IC Packages an Sockets</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>Dual In Line Package</b> + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<b>Pin Header Connectors</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + +<b>PIN HEADER</b> + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + +<b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie für +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab. +<b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/The_Mill_Daughter_Board/PCB/the_mill.pro b/The_Mill_Daughter_Board/PCB/the_mill.pro new file mode 100644 index 0000000..c41d5f7 --- /dev/null +++ b/The_Mill_Daughter_Board/PCB/the_mill.pro @@ -0,0 +1,25 @@ +EAGLE AutoRouter Statistics: + +Job : C:/Users/Luca/Documents/eagle/The_Mill_2/The_Mill/the_mill.brd + +Start at : 17:50:15 (03/04/2016) +End at : 17:50:22 (03/04/2016) +Elapsed time : 00:00:03 + +Signals : 16 RoutingGrid: 9 mil Layers: 1 +Connections : 23 predefined: 17 ( 0 Vias ) + +Router memory : 630120 + +Passname : TopRouter Route Optimize1 Optimize2 Optimize3 Optimize4 + +Time per pass : 00:00:02 00:00:01 00:00:00 00:00:00 00:00:00 00:00:00 +Number of Ripups : 0 5 0 0 0 0 +max. Level : 0 1 0 0 0 0 +max. Total : 0 2 0 0 0 0 + +Routed : 5 6 6 6 6 6 +Vias : 0 0 0 0 0 0 +Resolution : 95.7 % 100.0 % 100.0 % 100.0 % 100.0 % 100.0 % + +Final : 100.0% finished diff --git a/The_Mill_Daughter_Board/PCB/the_mill.sch b/The_Mill_Daughter_Board/PCB/the_mill.sch new file mode 100644 index 0000000..fb77de5 --- /dev/null +++ b/The_Mill_Daughter_Board/PCB/the_mill.sch @@ -0,0 +1,1160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>AVR Devices</b><p> +Configurable logic, microcontrollers, nonvolatile memories<p> +Based on the following sources:<p> +<ul> +<li>www.atmel.com +<li>CD-ROM : Configurable Logic Microcontroller Nonvolatile Memory +<li>CadSoft download site, www.cadsoft.de or www.cadsoftusa.com , file at90smcu_v400.zip +<li>avr.lbr +</ul> +<author>Revised by librarian@cadsoft.de</author> + + +<b>Thin Shrink Small Outline Plastic 20</b><p> +MAX3223-MAX3243.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + +<b>Plastic Leaded Chip Carrier</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + +<B>Dual In Line</B> + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<B>Small Outline Package</B> SOIC 0.300" + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + +<b>High perfomance CMOS (electrically erasable) programmable logic device (PLD)</b><p> +ABLE-Atmel-ABEL - P18V8R, P16V8C, P16V8AS, P17V8<br> +COPL Atmel-WinCUPL - G16V8MS, G16V8MA, G16V8AS, G16V8<br> +LOG/IC - GAL16V8_R, GAL16V8_G7, GAL16V8_C), GAL16V8<br> +Tango-PLD - G16V8R, G16V8C, G16V8AS, G16V8<br> + + +Source: http://www.atmel.com/dyn/resources/prod_documents/DOC0364.PDF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Pin Header Connectors</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + +<b>PIN HEADER</b> + + + + + + + + + +>NAME +>VALUE + + + + + + + + + +>NAME +>VALUE + + + + + + + + + +>NAME +>VALUE + + + + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + + +<b>IC Packages an Sockets</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>Dual In Line Package</b> + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Dual In Line Socket</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + +<b>Dual In Line / Socket</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Supply Symbols</b><p> + GND, VCC, 0V, +5V, -5V, etc.<p> + Please keep in mind, that these devices are necessary for the + automatic wiring of the supply signals.<p> + The pin name defined in the symbol is identical to the net which is to be wired automatically.<p> + In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p> + <author>Created by librarian@cadsoft.de</author> + + + + + + +>VALUE + + + + +>VALUE + + + + + +<b>SUPPLY SYMBOL</b> + + + + + + + + + + + + +<b>SUPPLY SYMBOL</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +A14o +A15o +A12o +A13o +RWo +VSSo +RW +VSS +A13 +A12 +A15 +A14 +A16 +E +E +E + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/The_Mill_Daughter_Board/PCB/the_mill_brd.pdf b/The_Mill_Daughter_Board/PCB/the_mill_brd.pdf new file mode 100644 index 0000000..68b21cd Binary files /dev/null and b/The_Mill_Daughter_Board/PCB/the_mill_brd.pdf differ diff --git a/The_Mill_Daughter_Board/PCB/the_mill_sch.pdf b/The_Mill_Daughter_Board/PCB/the_mill_sch.pdf new file mode 100644 index 0000000..5df10e6 Binary files /dev/null and b/The_Mill_Daughter_Board/PCB/the_mill_sch.pdf differ diff --git a/The_Mill_Daughter_Board/PROM/THEMILL_PROM.PLD b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.PLD new file mode 100644 index 0000000..b726b5c --- /dev/null +++ b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.PLD @@ -0,0 +1,79 @@ +Name THEMILL_PROM ; +PartNo 00 ; +Date 02/04/2016 ; +Revision 01 ; +Designer Luca Ridarelli ; +Company L&R ; +Assembly None ; +Location ; +Device g16v8a ; + +/* *************** INPUT PINS *********************/ +PIN 2 = tristate ; /* */ +PIN 3 = A4 ; /* Switch */ +PIN 4 = A2 ; /* */ +PIN 5 = A3 ; /* */ +PIN 6 = A0 ; /* */ +PIN 7 = A1 ; /* */ +PIN 8 = RW; +PIN 9 = VSS; + +/* *************** OUTPUT PINS *********************/ +/*PIN [14..19] = [Q5..0];*/ + +PIN 15 = Q0; +PIN 14 = Q1; +PIN 17 = Q2; +PIN 16 = Q3; +PIN 18 = Q4; +PIN 19 = Q5; + +PIN 13 = RWO; +PIN 12 = VSSO; + +field address = [A4..0]; +field byte = [Q5..0]; + + byte.oe = !tristate; + RWO.oe = !tristate; + VSSO.oe = !tristate; + + +RWO = RW; +VSSO = VSS; + +table address => byte { +0 => 1; +1 => 2; +2 => 3; +3 => 4; +4 => 5; +5 => 6; +6 => 7; +7 => 8; +8 => d; +9 => e; +a => f; +b => c; +c => 0; +d => 9; +e => a; +f => b; +10 => 0; +11 => 1; +12 => 2; +13 => 3; +14 => 4; +15 => 5; +16 => 6; +17 => 7; +18 => 8; +19 => 9; +1a => a; +1b => b; +1c => c; +1d => d; +1e => e; +1f => f; +} + diff --git a/The_Mill_Daughter_Board/PROM/THEMILL_PROM.abs b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.abs new file mode 100644 index 0000000..38f4234 Binary files /dev/null and b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.abs differ diff --git a/The_Mill_Daughter_Board/PROM/THEMILL_PROM.doc b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.doc new file mode 100644 index 0000000..9370ed5 --- /dev/null +++ b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.doc @@ -0,0 +1,234 @@ + +******************************************************************************* + THEMILL_PROM +******************************************************************************* + +CUPL(WM) 5.0a Serial# 60008009 +Device g16v8ma Library DLIB-h-40-8 +Created Mon Apr 04 20:45:14 2016 +Name THEMILL_PROM +Partno 00 +Revision 01 +Date 02/04/2016 +Designer Luca Ridarelli +Company L&R +Assembly None +Location + +=============================================================================== + Expanded Product Terms +=============================================================================== + +Q0 => + A0 & A4 + # A0 & A2 & A3 + # !A0 & !A2 & !A4 + # !A0 & !A3 & !A4 + +Q0.oe => + !tristate + +Q1 => + !A0 & A1 + # A1 & A4 + # A1 & A2 & A3 + # A0 & !A1 & !A2 & !A4 + # A0 & !A1 & !A3 & !A4 + +Q1.oe => + !tristate + +Q2 => + A2 & A4 + # !A0 & A2 & !A3 + # !A1 & A2 & !A3 + # !A2 & A3 & !A4 + # A0 & A1 & !A2 & !A4 + +Q2.oe => + !tristate + +Q3 => + A0 & A3 + # A1 & A3 + # !A2 & A3 + # A3 & A4 + # A0 & A1 & A2 & !A4 + +Q3.oe => + !tristate + +Q4 => + 0 + +Q4.oe => + !tristate + +Q5 => + 0 + +Q5.oe => + !tristate + +RWO => + RW + +RWO.oe => + !tristate + +VSSO => + VSS + +VSSO.oe => + !tristate + +address => + A4 , A3 , A2 , A1 , A0 + +byte => + Q5 , Q4 , Q3 , Q2 , Q1 , Q0 + + +=============================================================================== + Symbol Table +=============================================================================== + +Pin Variable Pterms Max Min +Pol Name Ext Pin Type Used Pterms Level +--- -------- --- --- ---- ------ ------ ----- + + A0 6 V - - - + A1 7 V - - - + A2 4 V - - - + A3 5 V - - - + A4 3 V - - - + Q0 15 V 4 7 2 + Q0 oe 15 X 1 1 1 + Q1 14 V 5 7 2 + Q1 oe 14 X 1 1 1 + Q2 17 V 5 7 2 + Q2 oe 17 X 1 1 1 + Q3 16 V 5 7 2 + Q3 oe 16 X 1 1 1 + Q4 18 V 1 7 2 + Q4 oe 18 X 1 1 1 + Q5 19 V 1 7 2 + Q5 oe 19 X 1 1 1 + RW 8 V - - - + RWO 13 V 1 7 2 + RWO oe 13 X 1 1 1 + VSS 9 V - - - + VSSO 12 V 1 7 2 + VSSO oe 12 X 1 1 1 + address 0 F - - - + byte 0 F - - - + tristate 2 V - - - + + +LEGEND D : default variable F : field G : group + I : intermediate variable N : node M : extended node + U : undefined V : variable X : extended variable + T : function + + +=============================================================================== + Fuse Plot +=============================================================================== + +Syn 02192 - Ac0 02193 - + +Pin #19 02048 Pol - 02120 Ac1 - + 00000 -x------------------------------ + 00032 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00064 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00096 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +Pin #18 02049 Pol - 02121 Ac1 - + 00256 -x------------------------------ + 00288 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00320 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00352 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00384 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00416 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00448 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00480 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +Pin #17 02050 Pol - 02122 Ac1 - + 00512 -x------------------------------ + 00544 ----x---x----------------------- + 00576 --------x----x---x-------------- + 00608 --------x----x-------x---------- + 00640 -----x---x--x------------------- + 00672 -----x---x------x---x----------- + 00704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00736 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +Pin #16 02051 Pol - 02123 Ac1 - + 00768 -x------------------------------ + 00800 ------------x---x--------------- + 00832 ------------x-------x----------- + 00864 ---------x--x------------------- + 00896 ----x-------x------------------- + 00928 -----x--x-------x---x----------- + 00960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +Pin #15 02052 Pol - 02124 Ac1 - + 01024 -x------------------------------ + 01056 ----x-----------x--------------- + 01088 --------x---x---x--------------- + 01120 -----x---x-------x-------------- + 01152 -----x-------x---x-------------- + 01184 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01248 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +Pin #14 02053 Pol - 02125 Ac1 - + 01280 -x------------------------------ + 01312 -----------------x--x----------- + 01344 ----x---------------x----------- + 01376 --------x---x-------x----------- + 01408 -----x---x------x----x---------- + 01440 -----x-------x--x----x---------- + 01472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +Pin #13 02054 Pol - 02126 Ac1 - + 01536 -x------------------------------ + 01568 ------------------------x------- + 01600 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +Pin #12 02055 Pol - 02127 Ac1 - + 01792 -x------------------------------ + 01824 ----------------------------x--- + 01856 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01888 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01920 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 01984 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 02016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + + +LEGEND X : fuse not blown + - : fuse blown + +=============================================================================== + Chip Diagram +=============================================================================== + + ______________ + | THEMILL_PROM | + x---|1 20|---x Vcc + tristate x---|2 19|---x Q5 + A4 x---|3 18|---x Q4 + A2 x---|4 17|---x Q2 + A3 x---|5 16|---x Q3 + A0 x---|6 15|---x Q0 + A1 x---|7 14|---x Q1 + RW x---|8 13|---x RWO + VSS x---|9 12|---x VSSO + GND x---|10 11|---x + |______________| + diff --git a/The_Mill_Daughter_Board/PROM/THEMILL_PROM.jed b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.jed new file mode 100644 index 0000000..fd72569 --- /dev/null +++ b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.jed @@ -0,0 +1,51 @@ + +CUPL(WM) 5.0a Serial# 60008009 +Device g16v8ma Library DLIB-h-40-8 +Created Mon Apr 04 20:45:14 2016 +Name THEMILL_PROM +Partno 00 +Revision 01 +Date 02/04/2016 +Designer Luca Ridarelli +Company L&R +Assembly None +Location +*QP20 +*QF2194 +*G0 +*F0 +*L00000 10111111111111111111111111111111 +*L00256 10111111111111111111111111111111 +*L00512 10111111111111111111111111111111 +*L00544 11110111011111111111111111111111 +*L00576 11111111011110111011111111111111 +*L00608 11111111011110111111101111111111 +*L00640 11111011101101111111111111111111 +*L00672 11111011101111110111011111111111 +*L00768 10111111111111111111111111111111 +*L00800 11111111111101110111111111111111 +*L00832 11111111111101111111011111111111 +*L00864 11111111101101111111111111111111 +*L00896 11110111111101111111111111111111 +*L00928 11111011011111110111011111111111 +*L01024 10111111111111111111111111111111 +*L01056 11110111111111110111111111111111 +*L01088 11111111011101110111111111111111 +*L01120 11111011101111111011111111111111 +*L01152 11111011111110111011111111111111 +*L01280 10111111111111111111111111111111 +*L01312 11111111111111111011011111111111 +*L01344 11110111111111111111011111111111 +*L01376 11111111011101111111011111111111 +*L01408 11111011101111110111101111111111 +*L01440 11111011111110110111101111111111 +*L01536 10111111111111111111111111111111 +*L01568 11111111111111111111111101111111 +*L01792 10111111111111111111111111111111 +*L01824 11111111111111111111111111110111 +*L02048 11111111001100000011000000100000 +*L02112 00000000111111111111111111111111 +*L02144 11111111111111111111111111111111 +*L02176 111111111111111111 +*C7A91 +*50B4 \ No newline at end of file diff --git a/The_Mill_Daughter_Board/PROM/THEMILL_PROM.pdf b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.pdf new file mode 100644 index 0000000..4957aaa --- /dev/null +++ b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.pdf @@ -0,0 +1,181 @@ +{COMPONENT C:\WINCUPL\WINCUPL\THEMILL_PROM.SYM + + {ENVIRONMENT + {PDIFvrev 3.00} + {Program "CUPL(WM) Version 5.0a"} + {DBtype "Schematic"} + {DBvrev 1.01} + {DBtime "Mon Apr 04 20:45:14 2016 "} + {DBunit "MIL"} + {DBgrid 10} + {Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1 + "PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1 + "DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4 + "CMPNAM" 5 "BORDER" 5} + } + + {USER + {VIEW + {Mode SYMB} + {Nlst OPEN} + {Vw 0 0 2} + {Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0} + {Gs 10 10} + } + } + + {DISPLAY + [Ly "PINNUM"] + [Ls "SOLID"][Wd 0] + [Ts 15][Tj "LC"][Tr 0][Tm "N"] + } + + {SYMBOL + {PIN_DEF + [Ly "PINCON"] + {P TRISTATE {Pt "INPUT"}{Lq 0}{Ploc 100 160}} + {P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 140}} + {P A2 {Pt "INPUT"}{Lq 0}{Ploc 100 120}} + {P A3 {Pt "INPUT"}{Lq 0}{Ploc 100 100}} + {P A0 {Pt "INPUT"}{Lq 0}{Ploc 100 80}} + {P A1 {Pt "INPUT"}{Lq 0}{Ploc 100 60}} + {P RW {Pt "INPUT"}{Lq 0}{Ploc 100 40}} + {P VSS {Pt "INPUT"}{Lq 0}{Ploc 100 20}} + {P VSSO {Pt "I/O"}{Lq 0}{Ploc 320 20}} + {P RWO {Pt "I/O"}{Lq 0}{Ploc 320 40}} + {P Q1 {Pt "I/O"}{Lq 0}{Ploc 320 60}} + {P Q0 {Pt "I/O"}{Lq 0}{Ploc 320 80}} + {P Q3 {Pt "I/O"}{Lq 0}{Ploc 320 100}} + {P Q2 {Pt "I/O"}{Lq 0}{Ploc 320 120}} + {P Q4 {Pt "I/O"}{Lq 0}{Ploc 320 140}} + {P Q5 {Pt "I/O"}{Lq 0}{Ploc 320 160}} + } + + {PKG + [Ly "REFDES"] + [Ts 25][Tj "CB"][Tr 0][Tm "N"] + {Rdl 210 190} + + [Ly "PINNUM"] + [Ts 15][Tj "RC"] + {Pnl 120 170} + {Pnl 120 150} + {Pnl 120 130} + {Pnl 120 110} + {Pnl 120 90} + {Pnl 120 70} + {Pnl 120 50} + {Pnl 120 30} + [Ts 15][Tj "LC"] + {Pnl 300 30} + {Pnl 300 50} + {Pnl 300 70} + {Pnl 300 90} + {Pnl 300 110} + {Pnl 300 130} + {Pnl 300 150} + {Pnl 300 170} + + {Sd A 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19} + } + + {PIC + [Ly "GATE"] + [Ts 15][Tj "LC"][Tr 0][Tm "N"] + {R 130 180 290 0} + {L 130 160 100 160} + {L 130 140 100 140} + {L 130 120 100 120} + {L 130 100 100 100} + {L 130 80 100 80} + {L 130 60 100 60} + {L 130 40 100 40} + {L 130 20 100 20} + {L 290 20 320 20} + {L 290 40 320 40} + {L 290 60 320 60} + {L 290 80 320 80} + {L 290 100 320 100} + {L 290 120 320 120} + {L 290 140 320 140} + {L 290 160 320 160} + [Ly "PINNAM"] + [Tj "LC"] + {T "TRISTATE" 140 160} + {T "A4" 140 140} + {T "A2" 140 120} + {T "A3" 140 100} + {T "A0" 140 80} + {T "A1" 140 60} + {T "RW" 140 40} + {T "VSS" 140 20} + [Tj "RC"] + {T "VSSO" 280 20} + {T "RWO" 280 40} + {T "Q1" 280 60} + {T "Q0" 280 80} + {T "Q3" 280 100} + {T "Q2" 280 120} + {T "Q4" 280 140} + {T "Q5" 280 160} + [Ly "DEVICE"] + [Tj "CT"] + {T "G16V8MA" 210 -10} + } + + {ATR + {IN + {Org 100 20} + {Ty 255} + } + {EX + [Ly "ATTR2"] + [Ts 12][Tj "CT"][Tr 0][Tm "N"] + {At PLD C:\WINCUPL\WINCUPL\THEMILL_PROM 210 180} + } + } + } + + {DETAIL + {ANNOTATE + } + + {NET_DEF + {N TRISTATE + } + {N A4 + } + {N A2 + } + {N A3 + } + {N A0 + } + {N A1 + } + {N RW + } + {N VSS + } + {N VSSO + } + {N RWO + } + {N Q1 + } + {N Q0 + } + {N Q3 + } + {N Q2 + } + {N Q4 + } + {N Q5 + } + } + + {SUBCOMP + } + } +} diff --git a/The_Mill_Daughter_Board/PROM/THEMILL_PROM.sim b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.sim new file mode 100644 index 0000000..87baeca --- /dev/null +++ b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.sim @@ -0,0 +1,89 @@ +%SIGNAL +PIN 6 = A0 +PIN 7 = A1 +PIN 4 = A2 +PIN 5 = A3 +PIN 3 = A4 +PIN 15 = Q0 +PIN 14 = Q1 +PIN 17 = Q2 +PIN 16 = Q3 +PIN 18 = Q4 +PIN 19 = Q5 +PIN 8 = RW +PIN 13 = RWO +PIN 9 = VSS +PIN 12 = VSSO +PIN 2 = tristate +%END + +%FIELD +FIELD address = A4,A3,A2,A1,A0 +FIELD byte = Q5,Q4,Q3,Q2,Q1,Q0 +%END + +%EQUATION +Q0 => + A0 & A4 + # A0 & A2 & A3 + # !A0 & !A2 & !A4 + # !A0 & !A3 & !A4 + +Q0.oe => + !tristate + +Q1 => + !A0 & A1 + # A1 & A4 + # A1 & A2 & A3 + # A0 & !A1 & !A2 & !A4 + # A0 & !A1 & !A3 & !A4 + +Q1.oe => + !tristate + +Q2 => + A2 & A4 + # !A0 & A2 & !A3 + # !A1 & A2 & !A3 + # !A2 & A3 & !A4 + # A0 & A1 & !A2 & !A4 + +Q2.oe => + !tristate + +Q3 => + A0 & A3 + # A1 & A3 + # !A2 & A3 + # A3 & A4 + # A0 & A1 & A2 & !A4 + +Q3.oe => + !tristate + +Q4 => + 0 + +Q4.oe => + !tristate + +Q5 => + 0 + +Q5.oe => + !tristate + +RWO => + RW + +RWO.oe => + !tristate + +VSSO => + VSS + +VSSO.oe => + !tristate + +%END diff --git a/The_Mill_Daughter_Board/PROM/THEMILL_PROM.txt b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.txt new file mode 100644 index 0000000..515a751 --- /dev/null +++ b/The_Mill_Daughter_Board/PROM/THEMILL_PROM.txt @@ -0,0 +1,79 @@ +Name THEMILL_PROM ; +PartNo 00 ; +Date 02/04/2016 ; +Revision 01 ; +Designer Luca Ridarelli ; +Company L&R ; +Assembly None ; +Location ; +Device g16v8a ; + +/* *************** INPUT PINS *********************/ +PIN 2 = tristate ; /* */ +PIN 3 = A4 ; /* Switch */ +PIN 4 = A2 ; /* */ +PIN 5 = A3 ; /* */ +PIN 6 = A0 ; /* */ +PIN 7 = A1 ; /* */ +PIN 8 = RW; +PIN 9 = VSS; + +/* *************** OUTPUT PINS ********************/ +/*PIN [14..19] = [Q5..0];*/ + +PIN 15 = Q0; +PIN 14 = Q1; +PIN 17 = Q2; +PIN 16 = Q3; +PIN 18 = Q4; +PIN 19 = Q5; + +PIN 13 = RWO; +PIN 12 = VSSO; + +field address = [A4..0]; +field byte = [Q5..0]; + + byte.oe = !tristate; + RWO.oe = !tristate; + VSSO.oe = !tristate; + + +RWO = RW; +VSSO = VSS; + +table address => byte { +0 => 1; +1 => 2; +2 => 3; +3 => 4; +4 => 5; +5 => 6; +6 => 7; +7 => 8; +8 => d; +9 => e; +a => f; +b => c; +c => 0; +d => 9; +e => a; +f => b; +10 => 0; +11 => 1; +12 => 2; +13 => 3; +14 => 4; +15 => 5; +16 => 6; +17 => 7; +18 => 8; +19 => 9; +1a => a; +1b => b; +1c => c; +1d => d; +1e => e; +1f => f; +} +