the_mill_daughterboard/The_Mill_Daughter_Board/PROM/THEMILL_PROM.pdf
Luca Ridarelli 07afc4459e First Commit
2017-01-16 18:44:48 +01:00

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3.3 KiB
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{COMPONENT C:\WINCUPL\WINCUPL\THEMILL_PROM.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Mon Apr 04 20:45:14 2016 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P TRISTATE {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
{P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
{P A2 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
{P A3 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
{P A0 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
{P A1 {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
{P RW {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
{P VSS {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
{P VSSO {Pt "I/O"}{Lq 0}{Ploc 320 20}}
{P RWO {Pt "I/O"}{Lq 0}{Ploc 320 40}}
{P Q1 {Pt "I/O"}{Lq 0}{Ploc 320 60}}
{P Q0 {Pt "I/O"}{Lq 0}{Ploc 320 80}}
{P Q3 {Pt "I/O"}{Lq 0}{Ploc 320 100}}
{P Q2 {Pt "I/O"}{Lq 0}{Ploc 320 120}}
{P Q4 {Pt "I/O"}{Lq 0}{Ploc 320 140}}
{P Q5 {Pt "I/O"}{Lq 0}{Ploc 320 160}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 210 190}
[Ly "PINNUM"]
[Ts 15][Tj "RC"]
{Pnl 120 170}
{Pnl 120 150}
{Pnl 120 130}
{Pnl 120 110}
{Pnl 120 90}
{Pnl 120 70}
{Pnl 120 50}
{Pnl 120 30}
[Ts 15][Tj "LC"]
{Pnl 300 30}
{Pnl 300 50}
{Pnl 300 70}
{Pnl 300 90}
{Pnl 300 110}
{Pnl 300 130}
{Pnl 300 150}
{Pnl 300 170}
{Sd A 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 180 290 0}
{L 130 160 100 160}
{L 130 140 100 140}
{L 130 120 100 120}
{L 130 100 100 100}
{L 130 80 100 80}
{L 130 60 100 60}
{L 130 40 100 40}
{L 130 20 100 20}
{L 290 20 320 20}
{L 290 40 320 40}
{L 290 60 320 60}
{L 290 80 320 80}
{L 290 100 320 100}
{L 290 120 320 120}
{L 290 140 320 140}
{L 290 160 320 160}
[Ly "PINNAM"]
[Tj "LC"]
{T "TRISTATE" 140 160}
{T "A4" 140 140}
{T "A2" 140 120}
{T "A3" 140 100}
{T "A0" 140 80}
{T "A1" 140 60}
{T "RW" 140 40}
{T "VSS" 140 20}
[Tj "RC"]
{T "VSSO" 280 20}
{T "RWO" 280 40}
{T "Q1" 280 60}
{T "Q0" 280 80}
{T "Q3" 280 100}
{T "Q2" 280 120}
{T "Q4" 280 140}
{T "Q5" 280 160}
[Ly "DEVICE"]
[Tj "CT"]
{T "G16V8MA" 210 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD C:\WINCUPL\WINCUPL\THEMILL_PROM 210 180}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N TRISTATE
}
{N A4
}
{N A2
}
{N A3
}
{N A0
}
{N A1
}
{N RW
}
{N VSS
}
{N VSSO
}
{N RWO
}
{N Q1
}
{N Q0
}
{N Q3
}
{N Q2
}
{N Q4
}
{N Q5
}
}
{SUBCOMP
}
}
}