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Add Atmega2560-based ASCII interface board
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Dave
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117
hardware/interface-ascii-atmega2560/README.md
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117
hardware/interface-ascii-atmega2560/README.md
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# ASCII Interface - Atmega328p
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This is is a key scanner module with parallel output, and optional serial
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output, supporting keyboards of up to 16 rows X 8 columns.
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The ATMega 328P was selected for the sole reason that it is an architecture
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familiar to many hobbyists, with an accessible programming environment and
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ecosystem, in a DIP format that fits the retro look and is easy to solder for
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most hobbyists. All of the ICs, other than the microcontroller, are only present
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to compensate for the limited number of GPIO lines on this small 28-pin
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microcontroller. Using a bigger chip would greatly simplify the hardware and
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even slightly simplify the hardware layer of the firmware.
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<img alt="Assembly Rendering" src="images/PCB-assembly-rendering.png" height=75% width=75%>
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## Features
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- Parallel or serial output
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- Up to 8 configuration settings via an up-to-8 position DIP switch
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- Apple 1, Apple 2, and SOL-20 compatible outputs. Other configurations can be
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supported by making a custom cable.
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- Can decode arbitrary keyboards up 16 rows by 8 columns.
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- Supports up to 3 keyboard LEDs
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- Supports up to 3 "special" host outputs, such as RESET, SCREEN_CLEAR, BREAK, etc.
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## Overview
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- The keyboard rows are driven by a pair of 74LS138 decoders, allowing 4 GPIO
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lines to drive 16 rows.
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- The columns are read in via an 8-bit shift register, controlled by 3 GPIO lines.
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- One 8-bit port is used for the parallel ASCII output.
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- Three GPIO lines are used to generate special outputs to the host. These could
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be RESET, BREAK, CLEAR, etc. These may be configured as open-collector (Hi-Z
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for HI, GND for LO), or open-emitter (5V for high, Hi-Z for LO).
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- Three GPIO lines are used to control keyboard LEDs.
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- The DIP switch is wired into row 15 (last row) of the matrix. In the future,
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the DIP switch will be moved to row 9 to reduce RAM usage and speed up key scanning.
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- A serial (UART) port is provided. This could be used to provide serial output
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instead or parallel output, to support a bootloader, or even to accept a serial
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input stream from another source to send to the host as parallel ASCII data.
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## Assembly Notes
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1. Solder the surface-mount microcontroller first. Be sure to match pin 1 to the
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dot on the silk-screen layer.
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1. Next, install the surface mount crysta, Y1. The orientation is not important.
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1. Next, solder in the Diodes D1-D3 and D4-D11
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1. Do not populate diodes D12-D27. These diodes are jumpered short. If you are
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using a key matrix with no diodes, then cut the jumpers with an x-acto knife
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and populate the diodes.
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1. Install all the capacitors. These are all 0.1 uF ceramic capacitors with 0.1"
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lead spacing. Many capacitors with 0.2" lead spacing are actually 0.1"
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emerging from the body, bent to 0.2", and can be straightened back to 0.1".
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1. Next, solder in the resitor R1 and Resistor network RN1.
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1. Install DIP switch SW1.
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1. Install connector J7
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1. Install the In-circuit Serial Programming (ISP) header, J6. (right-angle, 2x3
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0.100")
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1. (Optional) If you will be the digital outputs, or if you will be attaching
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switches or other sources of open-collector signals (such as RESET), then
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install connector J4 (right-angle, 1x5 0.100")
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1. (Optional) If you will be using the serial port, install the serial header
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J3. (right angle, 1x4 0.100")
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1. If you will be using the Apple 1 connector, install the DIP socket J1 (16-pin
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dip). If you plan to insert and remove the cable many times, a dual-wipe
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socket may be preferable to machine-pin, since it has a lower insertion
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force, and you will be less likely to bend pins. If you plan to insert the
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cable once and leave it forever, I suggest a machine-pin DIP socket.
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1. If you will be using the Apple 2 connector, install the DIP socket J2 (16-pin
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dip). The note for the Apple 1 connector selection applies here as well.
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1. If you will be using the SOL-20 connector, install connector J5 (vertical
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2x10 0.100")
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configuration or only a serial configuration, then you can jumper these
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resistors with a piece of wire.
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1. Any connectors required.
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## Optional components
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### Diodes D1-D16
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These diodes are intended to prevent conflicts between high and low keyboard
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driver outputs. They allow the row drivers to pull rows low, but not high,
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emulating open collector outputs.
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If you are attaching a keyboard with no diodes, then you only need to populate
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the diodes corresponding to rows on the keyboard. If the keyboard has 8 rows,
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then you may want to install 8 diodes corresponding to those rows.
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Note that the footprints for these diodes include a copper jumper on the TOP
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copper layer. If you install any of these diodes, you should cut the jumpers for
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those diodes. Otherwise the diodes do nothing.
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If you are attaching a keyboard with a diode per key, then the diodes on the keys perform the same function, in addition to preventing "ghosting", so the per-row diodes do not need to be installed.
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### DIP switch and associated diodes
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The DIP switch is optional. If you don't want to be able to set options via the
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DIP switches, you can set all your preferences in the firmware, or just accept
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the default behavior, and skip the DIP switch and Diodes D17-D20 and D24-D27.
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### Second 74LS138 multiplexer (U4)
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Only needed if you have more than 8 rows (including the DIP switch).
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### The 74LS07 hex buffer (U5) and pullup R6
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The 74LS07 is only needed if you are using LED2 or LED3 on the keyboard, or the OUT2 open
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collector output.
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### Diodes D21, D22, D23
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Some keyboards may not wire all keys into the matrix. For example, some other
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interface modules may assign special hardware functions to certain keys. Those
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keys are brought directly to the keyboard connector. For the classic keyboard,
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the POWER key, the '@' key, and the RUBOUT key are not directly wired. This
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module wires them into the matrix via D21, D22, and D23, respectively. For
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keyboards with no separately wired keys, these diodes may be omitted.
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### Resistors R1, R2, R5
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These resistors provide current limiting for up to three keyboard LEDs. If no
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keyboard LEDs are installed, then these resistors can be ommitted.
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Binary file not shown.
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After Width: | Height: | Size: 359 KiB |
6481
hardware/interface-ascii-atmega2560/interface-ascii-2560.kicad_pcb
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6481
hardware/interface-ascii-atmega2560/interface-ascii-2560.kicad_pcb
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Load Diff
281
hardware/interface-ascii-atmega2560/interface-ascii-2560.pro
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281
hardware/interface-ascii-atmega2560/interface-ascii-2560.pro
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@ -0,0 +1,281 @@
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update=Sunday, April 12, 2020 at 08:58:12 PM
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
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||||
NetFmtName=
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_WriteFile=0
|
||||
ERC_TestSimilarLabels=1
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ERC_CheckUniqueGlobalLabels=1
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ERC_CheckBusDriverConflicts=1
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ERC_CheckBusEntryConflicts=1
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ERC_CheckBusToBusConflicts=1
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ERC_CheckBusToNetConflicts=1
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=unikbd.net
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CopperLayerCount=2
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.2
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MinViaDiameter=0.4
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MinViaDrill=0.3
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||||
MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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||||
MinHoleToHole=0.25
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TrackWidth1=0.254
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||||
TrackWidth2=0.254
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||||
TrackWidth3=0.508
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TrackWidth4=1.27
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ViaDiameter1=0.8128
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ViaDrill1=0.4064
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ViaDiameter2=1.27
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ViaDrill2=0.7112
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dPairWidth1=0.2032
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dPairGap1=0.254
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dPairViaGap1=0.25
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SilkLineWidth=0.12
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SilkTextSizeV=1
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SilkTextSizeH=1
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SilkTextSizeThickness=0.15
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.2
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||||
CopperTextSizeV=1.5
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||||
CopperTextSizeH=1.5
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||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
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||||
CopperTextUpright=1
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||||
EdgeCutLineWidth=0.05
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||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
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||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
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||||
OthersTextItalic=0
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||||
OthersTextUpright=1
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||||
SolderMaskClearance=0
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||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
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||||
SolderPasteRatio=-0
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||||
[pcbnew/Layer.F.Cu]
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||||
Name=F.Cu
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||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
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||||
Name=In12.Cu
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||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
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||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.1524
|
||||
TrackWidth=0.254
|
||||
ViaDiameter=0.8128
|
||||
ViaDrill=0.4064
|
||||
uViaDiameter=0.3048
|
||||
uViaDrill=0.1016
|
||||
dPairWidth=0.2032
|
||||
dPairGap=0.254
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=power1
|
||||
Clearance=0.1524
|
||||
TrackWidth=1.27
|
||||
ViaDiameter=1.27
|
||||
ViaDrill=0.7112
|
||||
uViaDiameter=0.3048
|
||||
uViaDrill=0.1016
|
||||
dPairWidth=0.2032
|
||||
dPairGap=0.254
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/2]
|
||||
Name=signal
|
||||
Clearance=0.1524
|
||||
TrackWidth=0.254
|
||||
ViaDiameter=0.8128
|
||||
ViaDrill=0.4064
|
||||
uViaDiameter=0.3048
|
||||
uViaDrill=0.1016
|
||||
dPairWidth=0.2032
|
||||
dPairGap=0.254
|
||||
dPairViaGap=0.25
|
||||
1957
hardware/interface-ascii-atmega2560/interface-ascii-2560.sch
Normal file
1957
hardware/interface-ascii-atmega2560/interface-ascii-2560.sch
Normal file
File diff suppressed because it is too large
Load Diff
194
hardware/interface-ascii-atmega2560/interface-ascii.lib
Normal file
194
hardware/interface-ascii-atmega2560/interface-ascii.lib
Normal file
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@ -0,0 +1,194 @@
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# 74LS166
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#
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DEF 74LS166 U 0 40 Y Y 1 L N
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F0 "U" -300 850 50 H V C CNN
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F1 "74LS166" -300 -850 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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DIP?16*
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$ENDFPLIST
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DRAW
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S -300 800 300 -800 1 1 10 f
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X Ds 1 -500 700 200 R 50 50 1 0 I
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||||
X D3 10 500 200 200 L 50 50 1 0 I
|
||||
X D2 11 500 100 200 L 50 50 1 0 I
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||||
X D1 12 500 0 200 L 50 50 1 0 I
|
||||
X Qh 13 -500 200 200 R 50 50 1 0 O
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||||
X D0 14 500 -100 200 L 50 50 1 0 I
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||||
X SH_~LD 15 -500 50 200 R 50 50 1 0 I
|
||||
X VCC 16 0 1000 200 D 50 50 1 0 W
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X D7 2 500 600 200 L 50 50 1 0 I
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||||
X D6 3 500 500 200 L 50 50 1 0 I
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||||
X D5 4 500 400 200 L 50 50 1 0 I
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X D4 5 500 300 200 L 50 50 1 0 I
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||||
X CK_INH 6 -500 -500 200 R 50 50 1 0 I
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||||
X CLK 7 -500 -100 200 R 50 50 1 0 I C
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X GND 8 0 -1000 200 U 50 50 1 0 W
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X Clr 9 -500 600 200 R 50 50 1 0 I I
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ENDDRAW
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ENDDEF
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||||
#
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# ATmega328P-PU-MCU_Microchip_ATmega
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#
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||||
DEF ATmega328P-PU-MCU_Microchip_ATmega U 0 20 Y Y 1 F N
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||||
F0 "U" -500 1450 50 H V L BNN
|
||||
F1 "ATmega328P-PU-MCU_Microchip_ATmega" 100 -1450 50 H V L TNN
|
||||
F2 "Package_DIP:DIP-28_W7.62mm" 0 0 50 H I C CIN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
DIP*W7.62mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -500 -1400 500 1400 0 1 10 f
|
||||
X ~RESET 1 600 -300 100 L 50 50 1 1 T
|
||||
X PB7 10 600 500 100 L 50 50 1 1 T
|
||||
X PD5 11 600 -1000 100 L 50 50 1 1 T
|
||||
X PD6 12 600 -1100 100 L 50 50 1 1 T
|
||||
X PD7 13 600 -1200 100 L 50 50 1 1 T
|
||||
X PB0 14 600 1200 100 L 50 50 1 1 T
|
||||
X PB1 15 600 1100 100 L 50 50 1 1 T
|
||||
X PB2 16 600 1000 100 L 50 50 1 1 T
|
||||
X MOSI 17 600 900 100 L 50 50 1 1 T
|
||||
X MISO/PB4 18 600 800 100 L 50 50 1 1 T
|
||||
X SCK/PB5 19 600 700 100 L 50 50 1 1 T
|
||||
X PD0 2 600 -500 100 L 50 50 1 1 T
|
||||
X AVCC 20 100 1500 100 D 50 50 1 1 W
|
||||
X AREF 21 -600 1200 100 R 50 50 1 1 P
|
||||
X GND 22 0 -1500 100 U 50 50 1 1 P N
|
||||
X PC0 23 600 300 100 L 50 50 1 1 T
|
||||
X PC1 24 600 200 100 L 50 50 1 1 T
|
||||
X PC2 25 600 100 100 L 50 50 1 1 T
|
||||
X PC3 26 600 0 100 L 50 50 1 1 T
|
||||
X PC4 27 600 -100 100 L 50 50 1 1 T
|
||||
X PC5 28 600 -200 100 L 50 50 1 1 T
|
||||
X PD1 3 600 -600 100 L 50 50 1 1 T
|
||||
X PD2 4 600 -700 100 L 50 50 1 1 T
|
||||
X PD3 5 600 -800 100 L 50 50 1 1 T
|
||||
X PD4 6 600 -900 100 L 50 50 1 1 T
|
||||
X VCC 7 0 1500 100 D 50 50 1 1 W
|
||||
X GND 8 0 -1500 100 U 50 50 1 1 W
|
||||
X PB6 9 600 600 100 L 50 50 1 1 T
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# ATmega640V-8AU
|
||||
#
|
||||
DEF ATmega640V-8AU U 0 20 Y Y 1 F N
|
||||
F0 "U" 0 50 50 H V C BNN
|
||||
F1 "ATmega640V-8AU" 0 -50 50 H V C TNN
|
||||
F2 "Package_QFP:TQFP-100_14x14mm_P0.5mm" 0 550 50 H I C CIN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS ATmega640-16AU ATmega1280V-8AU ATmega1280-16AU ATmega2560V-8AU ATmega2560-16AU
|
||||
$FPLIST
|
||||
TQFP*14x14mm*P0.5mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -650 -3350 650 2750 0 1 10 f
|
||||
X PG5 1 800 -2100 150 L 50 50 1 1 B
|
||||
X VCC 10 100 2900 150 D 50 50 1 1 W
|
||||
X AVCC 100 300 2900 150 D 50 50 1 1 W
|
||||
X GND 11 200 -3500 150 U 50 50 1 1 W
|
||||
X PH0 12 -800 -2200 150 R 50 50 1 1 B
|
||||
X PH1 13 -800 -2300 150 R 50 50 1 1 B
|
||||
X PH2 14 -800 -2400 150 R 50 50 1 1 B
|
||||
X PH3 15 -800 -2500 150 R 50 50 1 1 B
|
||||
X PH4 16 -800 -2600 150 R 50 50 1 1 B
|
||||
X PH5 17 -800 -2700 150 R 50 50 1 1 B
|
||||
X PH6 18 -800 -2800 150 R 50 50 1 1 B
|
||||
X PB0 19 -800 1800 150 R 50 50 1 1 B
|
||||
X RXD0/PE0 2 -800 -1000 150 R 50 50 1 1 B
|
||||
X SCK/PB1 20 -800 1700 150 R 50 50 1 1 B
|
||||
X MOSI/PB2 21 -800 1600 150 R 50 50 1 1 B
|
||||
X MISO/PB3 22 -800 1500 150 R 50 50 1 1 B
|
||||
X PB4 23 -800 1400 150 R 50 50 1 1 B
|
||||
X PB5 24 -800 1300 150 R 50 50 1 1 B
|
||||
X PB6 25 -800 1200 150 R 50 50 1 1 B
|
||||
X PB7 26 -800 1100 150 R 50 50 1 1 B
|
||||
X PH7 27 -800 -2900 150 R 50 50 1 1 B
|
||||
X PG3 28 800 -1900 150 L 50 50 1 1 B
|
||||
X PG4 29 800 -2000 150 L 50 50 1 1 B
|
||||
X TXD0/PE1 3 -800 -1100 150 R 50 50 1 1 B
|
||||
X ~RESET 30 -800 2200 150 R 50 50 1 1 I
|
||||
X VCC 31 0 2900 150 D 50 50 1 1 W
|
||||
X GND 32 100 -3500 150 U 50 50 1 1 W
|
||||
X XTAL2 33 -800 2400 150 R 50 50 1 1 O
|
||||
X XTAL1 34 -800 2600 150 R 50 50 1 1 I
|
||||
X PL0 35 800 -600 150 L 50 50 1 1 B
|
||||
X PL1 36 800 -700 150 L 50 50 1 1 B
|
||||
X PL2 37 800 -800 150 L 50 50 1 1 B
|
||||
X PL3 38 800 -900 150 L 50 50 1 1 B
|
||||
X PL4 39 800 -1000 150 L 50 50 1 1 B
|
||||
X PE2 4 -800 -1200 150 R 50 50 1 1 B
|
||||
X PL5 40 800 -1100 150 L 50 50 1 1 B
|
||||
X PL6 41 800 -1200 150 L 50 50 1 1 B
|
||||
X PL7 42 800 -1300 150 L 50 50 1 1 B
|
||||
X PD0 43 800 -2300 150 L 50 50 1 1 B
|
||||
X PD1 44 800 -2400 150 L 50 50 1 1 B
|
||||
X PD2 45 800 -2500 150 L 50 50 1 1 B
|
||||
X PD3 46 800 -2600 150 L 50 50 1 1 B
|
||||
X PD4 47 800 -2700 150 L 50 50 1 1 B
|
||||
X PD5 48 800 -2800 150 L 50 50 1 1 B
|
||||
X PD6 49 800 -2900 150 L 50 50 1 1 B
|
||||
X PE3 5 -800 -1300 150 R 50 50 1 1 B
|
||||
X PD7 50 800 -3000 150 L 50 50 1 1 B
|
||||
X PG0 51 800 -1600 150 L 50 50 1 1 B
|
||||
X PG1 52 800 -1700 150 L 50 50 1 1 B
|
||||
X PC0 53 800 2400 150 L 50 50 1 1 B
|
||||
X PC1 54 800 2300 150 L 50 50 1 1 B
|
||||
X PC2 55 800 2200 150 L 50 50 1 1 B
|
||||
X PC3 56 800 2100 150 L 50 50 1 1 B
|
||||
X PC4 57 800 2000 150 L 50 50 1 1 B
|
||||
X PC5 58 800 1900 150 L 50 50 1 1 B
|
||||
X PC6 59 800 1800 150 L 50 50 1 1 B
|
||||
X PE4 6 -800 -1400 150 R 50 50 1 1 B
|
||||
X PC7 60 800 1700 150 L 50 50 1 1 B
|
||||
X VCC 61 -100 2900 150 D 50 50 1 1 W
|
||||
X GND 62 0 -3500 150 U 50 50 1 1 W
|
||||
X PJ0 63 800 1400 150 L 50 50 1 1 B
|
||||
X PJ1 64 800 1300 150 L 50 50 1 1 B
|
||||
X PJ2 65 800 1200 150 L 50 50 1 1 B
|
||||
X PJ3 66 800 1100 150 L 50 50 1 1 B
|
||||
X PJ4 67 800 1000 150 L 50 50 1 1 B
|
||||
X PJ5 68 800 900 150 L 50 50 1 1 B
|
||||
X PJ6 69 800 800 150 L 50 50 1 1 B
|
||||
X PE5 7 -800 -1500 150 R 50 50 1 1 B
|
||||
X PG2 70 800 -1800 150 L 50 50 1 1 B
|
||||
X PA7 71 800 -300 150 L 50 50 1 1 B
|
||||
X PA6 72 800 -200 150 L 50 50 1 1 B
|
||||
X PA5 73 800 -100 150 L 50 50 1 1 B
|
||||
X PA4 74 800 0 150 L 50 50 1 1 B
|
||||
X PA3 75 800 100 150 L 50 50 1 1 B
|
||||
X PA2 76 800 200 150 L 50 50 1 1 B
|
||||
X PA1 77 800 300 150 L 50 50 1 1 B
|
||||
X PA0 78 800 400 150 L 50 50 1 1 B
|
||||
X PJ7 79 800 700 150 L 50 50 1 1 B
|
||||
X PE6 8 -800 -1600 150 R 50 50 1 1 B
|
||||
X VCC 80 -200 2900 150 D 50 50 1 1 W
|
||||
X GND 81 -100 -3500 150 U 50 50 1 1 W
|
||||
X PK7 82 -800 200 150 R 50 50 1 1 B
|
||||
X PK6 83 -800 300 150 R 50 50 1 1 B
|
||||
X PK5 84 -800 400 150 R 50 50 1 1 B
|
||||
X PK4 85 -800 500 150 R 50 50 1 1 B
|
||||
X PK3 86 -800 600 150 R 50 50 1 1 B
|
||||
X PK2 87 -800 700 150 R 50 50 1 1 B
|
||||
X PK1 88 -800 800 150 R 50 50 1 1 B
|
||||
X PK0 89 -800 900 150 R 50 50 1 1 B
|
||||
X PE7 9 -800 -1700 150 R 50 50 1 1 B
|
||||
X PF7 90 -800 -700 150 R 50 50 1 1 B
|
||||
X PF6 91 -800 -600 150 R 50 50 1 1 B
|
||||
X PF5 92 -800 -500 150 R 50 50 1 1 B
|
||||
X PF4 93 -800 -400 150 R 50 50 1 1 B
|
||||
X PF3 94 -800 -300 150 R 50 50 1 1 B
|
||||
X PF2 95 -800 -200 150 R 50 50 1 1 B
|
||||
X PF1 96 -800 -100 150 R 50 50 1 1 B
|
||||
X PF0 97 -800 0 150 R 50 50 1 1 B
|
||||
X AREF 98 -800 2000 150 R 50 50 1 1 P
|
||||
X GND 99 -200 -3500 150 U 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
Loading…
Reference in New Issue
Block a user