mirror of
https://github.com/osiweb/unified_retro_keyboard.git
synced 2025-02-19 10:30:26 +00:00
production cleanup for interface-ascii
- Add production package scripts - Configure BOM generation for KiBOM - Add 3D models to path (add kicad 5 path variable to list) - bump version to 3 for compatibility with versioning scheme
This commit is contained in:
Dave
parent
0d0487df42
commit
33e68c6800
124
hardware/interface-ascii/bom.ini
Normal file
124
hardware/interface-ascii/bom.ini
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@ -0,0 +1,124 @@
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[BOM_OPTIONS]
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; General BoM options here
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; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
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ignore_dnf = 0
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; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
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html_generate_dnf = 1
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; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
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use_alt = 1
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; If 'alt_wrap' option is set to and integer N, the references field will wrap after N entries are printed
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alt_wrap = 0
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; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
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number_rows = 1
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; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
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group_connectors = 1
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; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
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test_regex = 1
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; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
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merge_blank_fields = 1
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; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
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output_file_name = %O_bom_%v%V
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; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
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variant_file_name_format = _(%V)
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; Field name used to determine if a particular part is to be fitted
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fit_field = Fitted
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; Make a backup of the bom before generating the new one, using the following template
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make_backup = %O.tmp
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; Default number of boards to produce if none given on CLI with -n
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number_boards = 1
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; Default PCB variant if none given on CLI with -r
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board_variant = ['default']
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; Whether to hide headers from output file
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hide_headers = False
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; Whether to hide PCB info from output file
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hide_pcb_info = False
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[IGNORE_COLUMNS]
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; Any column heading that appears here will be excluded from the Generated BoM
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; Titles are case-insensitive
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Class
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Component Type
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Footprint
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Footprint Lib
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Material
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Number of Pins
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Package Variant
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Part
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Part Lib
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Power Rating
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RoHS China Link
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RoHS Europe Link
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SheetPath
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Standards Version
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Temp (Operating)
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Temp (Soldering)
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Temp (Storage)
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Temp Coeff.
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Tolerance
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Value
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Voltage Rating
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Current Rating
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[COLUMN_ORDER]
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; Columns will apear in the order they are listed here
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; Titles are case-insensitive
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References
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Fitted
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Quantity Per PCB
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Description
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Part Value
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Manufacturer
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Manufacturer PN
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Label
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BOM Comment
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[GROUP_FIELDS]
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; List of fields used for sorting individual components into groups
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; Components which match (comparing *all* fields) will be grouped together
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; Field names are case-insensitive
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Part
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Part Lib
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Value
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Footprint
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Footprint Lib
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[COMPONENT_ALIASES]
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; A series of values which are considered to be equivalent for the part name
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; Each line represents a list of equivalent component name values separated by white space
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; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
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; Aliases are case-insensitive
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c c_small cap capacitor
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r r_small res resistor
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sw switch
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l l_small inductor
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zener zenersmall
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d diode d_small
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[REGEX_INCLUDE]
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; A series of regular expressions used to include parts in the BoM
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; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
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; Column names are case-insensitive
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; Format is: "[ColumName] [Regex]" (white-space separated)
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[REGEX_EXCLUDE]
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; A series of regular expressions used to exclude parts from the BoM
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; If a component matches ANY of these, it will be excluded from the BoM
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; Column names are case-insensitive
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; Format is: "[ColumName] [Regex]" (white-space separated)
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References ^TP[0-9]*
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References ^FID
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Part mount.*hole
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Part solder.*bridge
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Part test.*point
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Footprint test.*point
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Footprint mount.*hole
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Footprint fiducial
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Allow Substitution
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Tracking
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Package
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Manufacturer Link
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Component Value
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Datasheet
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File diff suppressed because it is too large
Load Diff
320
hardware/interface-ascii/production-package/Makefile
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320
hardware/interface-ascii/production-package/Makefile
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@ -0,0 +1,320 @@
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NAME=interface-ascii
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PROJECT_DESC=Unified retro keyboard ASCII interface, ATMega 328P version
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VARIANTNAME=Production
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BOARDREV=3
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BOARDREVMINOR=
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SCHEMATIC_REV=0
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PROJECT_REV=0
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LAYERS=2
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PCBDIR="./PCB_dir"
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PROGRAMMING_DIR=programming_files_dir
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DIAGRAMS_DIR=diagrams_dir
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WORK_INSTR_DIR=work_instructions_dir
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LABELS_DIR=labels_dir
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SUBDIRS=$(PROGRAMMING_DIR) $(DIAGRAMS_DIR) $(WORK_INSTR_DIR) $(LABELS_DIR)
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PCBREV=$(BOARDREV)
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SCHREV=$(BOARDREV).$(SCHEMATIC_REV)
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PRJREV=$(BOARDREV).$(SCHEMATIC_REV).$(PROJECT_REV)
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PCBNAME=$(NAME)-Rev_$(PCBREV)$(BOARDREVMINOR)
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PCBFULLNAME=$(PCBNAME)-$(VARIANTNAME)
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SCHNAME=$(NAME)-Rev_$(SCHREV)-$(VARIANTNAME)
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PRJNAME=$(NAME)-Rev_$(PRJREV)$(BOARDREVMINOR)-$(VARIANTNAME)
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SCHEMATIC_SRC=$(NAME).kicad_sch
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BOARD_SRC=$(NAME).kicad_pcb
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PCBZIPFILE=$(PCBNAME)-pcbfab.zip
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PKGZIPFILE=$(PRJNAME)-package.zip
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GENERATED_BOMFILE = ../$(NAME)_bom_$(SCHREV).csv
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BOMFILE=BOM-$(SCHNAME).csv
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BOMINITFILE=../bom.ini
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BOMINITTEMPLATE=./templates/bom.ini
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#README_STYLE=rst
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README_STYLE=pdf
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READMEFILEBASE=README-$(PRJNAME)
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READMEFILETXT=$(READMEFILEBASE).rst
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READMEFILEPDF=$(READMEFILEBASE).pdf
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READMETARGET=readme$(README_STYLE)
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RENDERFILE_TOP=Renderings-top-$(PCBFULLNAME).jpg
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RENDERFILE_BOTTOM=Renderings-bottom-$(PCBFULLNAME).jpg
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RENDERFILES=$(RENDERFILE_TOP) $(RENDERFILE_BOTTOM)
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DUMMY_RENDERFILES=$(addsuffix _, $(RENDERFILES))
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GENERATED_SCHEMFILE=../$(NAME).pdf
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SCHEMFILE=Schematic-$(PRJNAME).pdf
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STEPFILE=Model-3D-$(PCBNAME)-$(VARIANTNAME).STEP
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DUMMY_STEPFILE="$(STEPFILE)_"
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DUMMY_TARGETS=$(DUMMY_STEPFILE) $(DUMMY_RENDERFILES)
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define MAKEFILE_SWITCHES
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NAME="$(NAME)" PROJECT_DESC="$(PROJECT_DESC)" \
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BOARDREV="$(BOARDREV)" BOARDREVMINOR="$(BOARDREVMINOR)" \
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LAYERS="$(LAYERS)"
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endef
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define README_TEXT
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"$(NAME) Rev $(PRJREV) \($(PROJECT_DESC)\)"\
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|-----------------------------------------------------------------------------------------------|\
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|This is the package for $(NAME) rev $(PRJREV).|\
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|Service Requested\
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|=================|\
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| * Manufacturing and inspection to IPC class 3 standard.\
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| * RoHS compliant\
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| * PCB Material: FR4\
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| * Solder mask color: Green\
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| * Silk screen color: White\
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| * Layers: $(LAYERS)\
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| * Copper thickness: 1 oz all layers\
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| * Finish: HASL|\
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||Programming and labeling of microcontroller\
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|===========================================|\
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|None\
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||Testing\
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|=======\
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| * Test 100% testing of assemblies\
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| * Standard PCB QA (bed of nails, test for shorts and opens)\
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||Tracking\
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|========|\
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|None\
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||Packaging\
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|=========|\
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|Standard Packaging\
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||Production Package\
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|==================|\
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|The ZIP file contains the following files:\
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| $(PCBZIPFILE)\
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|+++A ZIP file containing Gerbers; drill file;\
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|+++readme.txt\
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|++++++readme file containing PCB fabrication directions; fab renderings, etc.\
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|$(READMEFILE)\
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|+++This letter.\
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|$(RENDERFILE_TOP)\
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|+++A JPEG file containing a reference for PCB parts placement, and 3D renderings of the front of the populated board (with components).\
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|$(RENDERFILE_BOTTOM)\
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|+++A JPEG file containing a reference for PCB parts placement, and 3D renderings of the back of the populated board (with components).\
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|$(STEPFILE):\
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|+++An exported 3D STEP file of the PCB with all components fitted.\
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|$(SCHEMFILE)\
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|+++A PDF file containing the schematics for this PCB.\
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|$(BOMFILE)\
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|+++BOM file, csv format\
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|Subdirectory: labels_dir\
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|+++:$(PROJNAME)_labels.doc: Labels for final packaging.\
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|Subdirectory: programming_files_dir\
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|+++empty, not applicable.\
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|Subdirectory containing programming files\
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|+++empty, not applicable\
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|Subdirectory: diagrams_dir\
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|+++empty\
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|Subdirectory containing diagrams or pictures related to production\
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|+++empty\
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|Subdirectory: work_instructions_dir\
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|+++Subdirectory containing work instructions, test procedures, etc.|\
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|.. figure:: ./$(RENDERFILE_TOP)|\
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| TOP side rendering of populated PCB\
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|.. figure:: ./$(RENDERFILE_BOTTOM)|\
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| BOTTOM side rendering of populated PCB
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endef
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define RENDER_TOP_MSG
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|------------------------------------------------------------------------\
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|The assembly rendering \"$(RENDERFILE_TOP)\"\
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|must be manually generated with the following steps:|\
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|1) Bring up the 3D rendering from PCBNEW (ALT-3). Select\
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|the TOP view (RightClick-"View Top").|\
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|2) Perform a screen capture. Save the capture to the\
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|production-package directory. Select the dummy file name|\
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|" \"$(RENDERFILE_TOP)_\""|\
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|and delete the trailing \"_\". Then click Save.
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endef
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define RENDER_BOTTOM_MSG
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|------------------------------------------------------------------------\
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|The assembly rendering \"$(RENDERFILE_BOTTOM)\"\
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|must be manually generated with the following steps:|\
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|1) Bring up the 3D rendering from PCBNEW (ALT-3). Select\
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|the BOTTOM view (RightClick-"View Bottom").|\
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|2) Perform a screen capture. Save the capture to the\
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|production-package directory. Select the dummy file name|\
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|" \"$(RENDERFILE_BOTTOM)_\""|\
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|and delete the trailing \"_\". Then click Save.
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endef
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define BOM_MSG
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|------------------------------------------------------------------------\
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|The BOM file must be manually generated. The BOM file requires the KiBOM plugin.\
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|Please ensure that KiBOM is installed. To generate the BOM file:\
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|1) Copy the file 'bom.ini' in the templates directory to the main directory:\
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|\" cp templates_dir/bom.ini ..\"\
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|2) In EESChema, select Tools->Generate BOM.|\
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|3) Select KIBOM_CLI and click \"Generate\"|
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endef
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define SCHEM_MSG
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|------------------------------------------------------------------------\
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|The Schematic PDF file must be manually generated:\
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|1) In EESChema, select File->Plot to bring up the Plot dialog\
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|2) Select PDF output format.\
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|3) Check "Plot Drawing Sheet"\
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|4) Click "Plot All Pages"
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endef
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define STEPFILE_MSG
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|------------------------------------------------------------------------\
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|The STEP file must be manually generated.\
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|1) From PCBNEW, select File->Export->STEP\
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|2) Check the following boxes:\
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| - Board Center Origin\
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| - Substitute similarly named models\
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| - Overwrite old file\
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|2) Save to the production package directory. Select the placeholder filename:\
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|" $(STEPFILE)_"\
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|3) Remove the trailing \"_\" and click "Save"
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endef
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# KiCad doesn't automate saving of rendering files, which must be
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# screen-captured and saved as JPEG files. The STEP file must similarly be
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# exported manually. the "dummies" target creates filename templates that can be
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# selected and edited (by removing the trailing "_") to help ensure that the
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all: dummies bomfile renderfiles schemfile $(READMETARGET) pkgzip subdirs
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.phony: dummies
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dummies:
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@echo "$(DUMMY_TARGETS)" | xargs -n 1 echo "+++ Creating placeholder: "
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@touch $(DUMMY_TARGETS)
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.Phony: clean
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clean:
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rm -fv *.zip $(DUMMY_TARGETS) *~ *_ makefile.log
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rm -fv *pdf *rst *csv
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(cd PCB_dir; make $(MAKEFILE_SWITCHES) clean)
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.phony: veryclean
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veryclean: clean
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rm -fv $(SCHEMFILE) $(RENDERFILES) $(BOMFILE)
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rm -rfv *.jpg *.JPG *.pdf *.pdf *.png *.PNG
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rm -f README* *rst *pdf *dvi
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(cd PCB_dir; make $(MAKEFILE_SWITCHES) veryclean)
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bominit: $(BOMINITFILE)
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$(BOMINITFILE): $(BOMINITTEMPLATE)
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cp -i $(BOMINITTEMPLATE) $(BOMINITFILE)
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$(BOMFILE):
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@if [ ! -f "$(GENERATED_BOMFILE)" ]; then \
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echo "XXX Didn't find BOM: $(GENERATED_BOMFILE). See makefile.log. . .";\
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echo "|$(BOM_MSG)|"|tr '|' '\n' >> makefile.log;\
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else \
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echo "--> Found BOM: $(GENERATED_BOMFILE). Copying. . .";\
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cp $(GENERATED_BOMFILE) $(BOMFILE);\
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fi
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bomfile: $(BOMFILE)
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$(SCHEMFILE):
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@if [ ! -f "$(GENERATED_SCHEMFILE)" ]; then \
|
||||||
|
echo "XXX Didn't find Schematic PDF: $(GENERATED_SCHEMFILE). See makefile.log";\
|
||||||
|
echo "$(SCHEM_MSG)"|tr '|' '\n' >> makefile.log; \
|
||||||
|
else \
|
||||||
|
echo "--> Found Schematic PDF: $(GENERATED_SCHEMFILE)";\
|
||||||
|
cp $(GENERATED_SCHEMFILE) $(SCHEMFILE);\
|
||||||
|
fi
|
||||||
|
|
||||||
|
schemfile: $(SCHEMFILE)
|
||||||
|
|
||||||
|
$(STEPFILE):
|
||||||
|
@if [ ! -f "$(STEPFILE)" ]; then\
|
||||||
|
echo; \
|
||||||
|
echo "XXX Didn't find assembly STEP file: $(STEPFILE). See makefile.log"; \
|
||||||
|
echo "$(STEPFILE_MSG)"|tr '|' '\n' >> makefile.log; \
|
||||||
|
echo; \
|
||||||
|
else \
|
||||||
|
echo "--> Found assembly STEP file: $(STEPFILE)"; \
|
||||||
|
fi
|
||||||
|
|
||||||
|
.Phony: stepfile
|
||||||
|
stepfile: $(STEPFILE)
|
||||||
|
|
||||||
|
.Phony: renderfiles
|
||||||
|
renderfiles: renderfile_top renderfile_bottom
|
||||||
|
|
||||||
|
.Phony: renderfile_top
|
||||||
|
renderfile_top:
|
||||||
|
@if [ ! -f "$(RENDERFILE_TOP)" ]; then\
|
||||||
|
echo; \
|
||||||
|
echo "XXX Didn't find assembly rendering: $(RENDERFILE_TOP) See makefile.log"; \
|
||||||
|
echo "$(RENDER_BOTTOM_MSG)"|tr '|' '\n' >> makefile.log; \
|
||||||
|
echo; \
|
||||||
|
else \
|
||||||
|
echo "--> Found top assembly rendering: $(RENDERFILE_TOP)"; \
|
||||||
|
fi
|
||||||
|
|
||||||
|
.Phony: renderfile_bottom
|
||||||
|
renderfile_bottom:
|
||||||
|
@if [ ! -f "$(RENDERFILE_BOTTOM)" ]; then\
|
||||||
|
echo; \
|
||||||
|
echo "XXX Didn't find bottom assembly rendering: $(RENDERFILE_BOTTOM) See makefile.log"; \
|
||||||
|
echo "$(RENDER_TOP_MSG)"|tr '|' '\n' >> makefile.log; \
|
||||||
|
echo; \
|
||||||
|
else \
|
||||||
|
echo "--> Found bottom assembly rendering: $(RENDERFILE_BOTTOM)"; \
|
||||||
|
fi
|
||||||
|
|
||||||
|
pcbzip: $(PCBZIPFILE)
|
||||||
|
|
||||||
|
$(PCBZIPFILE):
|
||||||
|
echo "Building PCB Zip file..."; (cd $(PCBDIR); make $(MAKEFILE_SWITCHES) zip)
|
||||||
|
|
||||||
|
renderfiles: renderfile_top renderfile_bottom
|
||||||
|
|
||||||
|
readmetxt: $(READMEFILETXT)
|
||||||
|
|
||||||
|
readmepdf: $(READMEFILEPDF)
|
||||||
|
|
||||||
|
$(READMEFILETXT): Makefile
|
||||||
|
@echo "Creating Readme File $(READMEFILETXT)."; \
|
||||||
|
echo "$(README_TEXT)"|tr '|' '\n' | sed 's/+++/ /g' > $(READMEFILETXT);
|
||||||
|
|
||||||
|
$(READMEFILEPDF): $(READMEFILETXT)
|
||||||
|
@echo "Creating Readme File $(READMEFILEPDF)."; \
|
||||||
|
pandoc -f rst -t pdf -o "$(READMEFILEPDF)" "$(READMEFILETXT)";
|
||||||
|
|
||||||
|
.phony subdirs:
|
||||||
|
@mkdir -p $(SUBDIRS)
|
||||||
|
|
||||||
|
pkgzip: $(PCBZIPFILE) $(BOMFILE) $(RENDERFILES) $(READMEFILE) $(STEPFILE)
|
||||||
|
@echo removing old zip. . .; \
|
||||||
|
rm -rf $(PKGZIPFILE); \
|
||||||
|
echo creating zip. . .; \
|
||||||
|
zip -9r $(PKGZIPFILE) \
|
||||||
|
$(PCBZIPFILE) \
|
||||||
|
$(READMEFILETXT) \
|
||||||
|
$(READMEFILEPDF) \
|
||||||
|
$(SCHEMFILE) \
|
||||||
|
$(RENDERFILES) \
|
||||||
|
$(BOMFILE) \
|
||||||
|
$(STEPFILE) \
|
||||||
|
$(SUBDIRS)
|
||||||
337
hardware/interface-ascii/production-package/PCB_dir/Makefile
Executable file
337
hardware/interface-ascii/production-package/PCB_dir/Makefile
Executable file
@ -0,0 +1,337 @@
|
|||||||
|
PROJECT_DESC="PCB"
|
||||||
|
NAME="PCB"
|
||||||
|
BOARDREV=1
|
||||||
|
BOARDREVMINOR=
|
||||||
|
LAYERS=2
|
||||||
|
SMT=no
|
||||||
|
|
||||||
|
#README_STYLE=rst
|
||||||
|
README_STYLE=pdf
|
||||||
|
|
||||||
|
PCBNAME=$(NAME)-Rev_$(BOARDREV)$(BOARDREVMINOR)
|
||||||
|
|
||||||
|
READMEFILEBASE=README-PCB-$(PCBNAME)
|
||||||
|
READMEFILETXT=$(READMEFILEBASE).rst
|
||||||
|
READMEFILEPDF=$(READMEFILEBASE).pdf
|
||||||
|
READMETARGET=readme$(README_STYLE)
|
||||||
|
|
||||||
|
TOP_SOLDER_EXT = gts
|
||||||
|
TOP_SOLDER_DSC = F_Mask
|
||||||
|
TOP_SOLDER_GBR = "$(PCBNAME)_$(TOP_SOLDER_DSC).$(TOP_SOLDER_EXT)"
|
||||||
|
TOP_COPPER_EXT = gtl
|
||||||
|
TOP_COPPER_DSC = F_Cu
|
||||||
|
TOP_COPPER_GBR = "$(PCBNAME)_$(TOP_COPPER_DSC).$(TOP_COPPER_EXT)"
|
||||||
|
TOP_SILK_EXT = gto
|
||||||
|
TOP_SILK_DSC = F_Silkscreen
|
||||||
|
TOP_SILK_GBR = "$(PCBNAME)_$(TOP_SILK_DSC).$(TOP_SILK_EXT)"
|
||||||
|
BOT_SOLDER_EXT = gbs
|
||||||
|
BOT_SOLDER_DSC = B_Mask
|
||||||
|
BOT_SOLDER_GBR = "$(PCBNAME)_$(BOT_SOLDER_DSC).$(BOT_SOLDER_EXT)"
|
||||||
|
BOT_COPPER_EXT = gbl
|
||||||
|
BOT_COPPER_DSC = B_Cu
|
||||||
|
BOT_COPPER_GBR = "$(PCBNAME)_$(BOT_COPPER_DSC).$(BOT_COPPER_EXT)"
|
||||||
|
BOT_SILK_EXT = gbo
|
||||||
|
BOT_SILK_DSC = B_Silkscreen
|
||||||
|
BOT_SILK_GBR = "$(PCBNAME)_$(BOT_SILK_DSC).$(BOT_SILK_EXT)"
|
||||||
|
OUTLN_EXT = gm1
|
||||||
|
OUTLN_DSC = Edge_Cuts
|
||||||
|
OUTLN_GBR = "$(PCBNAME)_$(OUTLN_DSC).$(OUTLN_EXT)"
|
||||||
|
DRILL_EXT = DRL
|
||||||
|
DRILL_PTH = "$(PCBNAME)-PTH.$(DRILL_EXT)"
|
||||||
|
DRILL_NPTH = "$(PCBNAME)-NPTH.$(DRILL_EXT)"
|
||||||
|
TOP_PASTE_EXT = gtp
|
||||||
|
TOP_PASTE_DSC = F_Paste
|
||||||
|
TOP_PASTE_GBR = "$(PCBNAME)_$(TOP_PASTE_DSC).$(TOP_PASTE_EXT)"
|
||||||
|
BOT_PASTE_EXT = gbp
|
||||||
|
BOT_PASTE_DSC = B_Paste
|
||||||
|
BOT_PASTE_GBR = "$(PCBNAME)_$(BOT_PASTE_DSC).$(BOT_PASTE_EXT)"
|
||||||
|
|
||||||
|
GND1_EXT = g2
|
||||||
|
GND1_DSC = In1_Cu
|
||||||
|
GND1_GBR = "$(PCBNAME)_$(GND1_DSC).$(GND1_EXT)"
|
||||||
|
GND2_EXT = g3
|
||||||
|
GND2_DSC = In2_Cu
|
||||||
|
GND2_GBR = "$(PCBNAME)_$(GND2_DSC).$(GND2_EXT)"
|
||||||
|
|
||||||
|
ifeq ($(SMT),yes)
|
||||||
|
PASTE_LAYERS= $(TOP_PASTE_GBR) $(BOT_PASTE_GBR)
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(LAYERS),4)
|
||||||
|
OUTPUT_EXTS = $(addprefix *., $(TOP_SOLDER_EXT) $(TOP_COPPER_EXT) $(TOP_SILK_EXT) \
|
||||||
|
$(BOT_SOLDER_EXT) $(BOT_COPPER_EXT) $(BOT_SILK_EXT) \
|
||||||
|
$(OUTLN_EXT) $(DRILL_EXT)) \
|
||||||
|
$(TOP_PASTE_EXT) $(BOT_PASTE_EXT) \
|
||||||
|
$(GND1_EXT) $(GND2_EXT)
|
||||||
|
|
||||||
|
define STACKUP_DESC
|
||||||
|
| * Stackup: All tolerances 10%\
|
||||||
|
| 1. Total thickness: 0.062 inch\
|
||||||
|
| 1. top layer 1oz copper\
|
||||||
|
| 1. prepreg 2x2116\
|
||||||
|
| 1. second layer 1oz copper\
|
||||||
|
| 1. core 0.039 inch core\
|
||||||
|
| 1. third layer 1oz copper\
|
||||||
|
| 1. prepreg 2x2116\
|
||||||
|
| 1. bottom layer 1oz copper
|
||||||
|
endef
|
||||||
|
|
||||||
|
define INNER_PLANE_DESC
|
||||||
|
|:INNER_PLANE 1: - :code:\`"$(GND1_GBR)"\`\
|
||||||
|
|:INNER_PLANE 2: - :code:\`"$(GND2_GBR)"\`
|
||||||
|
endef
|
||||||
|
|
||||||
|
INNER_PLANES = $(GND1_GBR) $(GND2_GBR)
|
||||||
|
|
||||||
|
define INNER_LAYERS
|
||||||
|
* In1.Cu\
|
||||||
|
| * In2.Cu
|
||||||
|
endef
|
||||||
|
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(LAYERS),2)
|
||||||
|
OUTPUT_EXTS = $(addprefix *., $(TOP_SOLDER_EXT) $(TOP_COPPER_EXT) $(TOP_SILK_EXT) \
|
||||||
|
$(BOT_SOLDER_EXT) $(BOT_COPPER_EXT) $(BOT_SILK_EXT) \
|
||||||
|
$(OUTLN_EXT) $(DRILL_EXT)) \
|
||||||
|
$(TOP_PASTE_EXT) $(BOT_PASTE_EXT)
|
||||||
|
|
||||||
|
define STACKUP_DESC
|
||||||
|
| * Stackup: All tolerances 10%\
|
||||||
|
| 1. Total thickness: 0.062 inch\
|
||||||
|
| 1. top layer 1oz copper\
|
||||||
|
| 1. core 0.059 inch\
|
||||||
|
| 1. bottom layer 1oz copper
|
||||||
|
endef
|
||||||
|
|
||||||
|
|
||||||
|
endif
|
||||||
|
|
||||||
|
DRILDIR = outputs
|
||||||
|
GERBDIR = outputs
|
||||||
|
FAB_TOP = $(PCBNAME)-render-top-view.jpg
|
||||||
|
FAB_BOTTOM = $(PCBNAME)-render-bottom-view.jpg
|
||||||
|
FAB_FILES = $(FAB_TOP) $(FAB_BOTTOM)
|
||||||
|
FAB_DUMMIES = $(FAB_TOP)_ $(FAB_BOTTOM)_
|
||||||
|
|
||||||
|
DUMMY_TARGETS = $(FAB_DUMMIES)
|
||||||
|
|
||||||
|
ZIPFILE = ../$(PCBNAME)-pcbfab.zip
|
||||||
|
|
||||||
|
define FAB_TOP_MSG
|
||||||
|
|------------------------------------------------------------------------\
|
||||||
|
|The assembly rendering \"$(FAB_TOP)\"\
|
||||||
|
|must be manually generated with the following steps:|\
|
||||||
|
|1) Bring up the 3D rendering from PCBNEW \(ALT-3\).|\
|
||||||
|
|2) Deselect the 3D model visibility for all components.|\
|
||||||
|
|3) Select the TOP view \(RightClick-"View Top"\).|\
|
||||||
|
|2) Perform a screen capture. Save the capture to the\
|
||||||
|
|\"production-package/PCB_dir\" directory. Select the dummy file name|\
|
||||||
|
|" \"$(FAB_TOP)_\""|\
|
||||||
|
|and delete the trailing \"_\". Then click Save.
|
||||||
|
endef
|
||||||
|
|
||||||
|
define FAB_BOTTOM_MSG
|
||||||
|
|------------------------------------------------------------------------\
|
||||||
|
|The assembly rendering \"$(FAB_BOTTOM)\"\
|
||||||
|
|must be manually generated with the following steps:|\
|
||||||
|
|1) Bring up the 3D rendering from PCBNEW \(ALT-3\).|\
|
||||||
|
|2) Deselect the 3D model visibility for all components.|\
|
||||||
|
|3) Select the BOTTOM view \(RightClick-"View Bottom"\).|\
|
||||||
|
|2) Perform a screen capture. Save the capture to the\
|
||||||
|
|\"production-package/PCB_dir\" directory. Select the dummy file name|\
|
||||||
|
|" \"$(FAB_BOTTOM)_\""|\
|
||||||
|
|and delete the trailing \"_\". Then click Save.
|
||||||
|
endef
|
||||||
|
|
||||||
|
define README_TEXT
|
||||||
|
"$(NAME) Rev $(BOARDREV) \($(PROJECT_DESC)\)"\
|
||||||
|
|------------------------------------------------------------------------------------|\
|
||||||
|
||:Board: "$(BASENAME)"\
|
||||||
|
||Service\
|
||||||
|
|=======|\
|
||||||
|
| * Manufacturing and inspection to IPC class 3 standard.\
|
||||||
|
| * PCB Material: FR4\
|
||||||
|
| * Solder mask color: Green\
|
||||||
|
| * Silk screen color: White\
|
||||||
|
| * Layers: $(LAYERS)\
|
||||||
|
| * Copper thickness: 1 oz all layers\
|
||||||
|
| * Finish: HASL|\
|
||||||
|
$(STACKUP_DESC)\
|
||||||
|
|\
|
||||||
|
|Files\
|
||||||
|
|=====|\
|
||||||
|
|:BOARD OUTLINE: - :code:\`"$(OUTLN_GBR)"\`\
|
||||||
|
|:TOP LAYER: - :code:\`"$(TOP_COPPER_GBR)"\`\
|
||||||
|
$(INNER_PLANE_DESC)\
|
||||||
|
|:BOTTOM LAYER: - :code:\`"$(BOT_COPPER_GBR)"\`\
|
||||||
|
|:TOP SOLDER MASK: - :code:\`"$(TOP_PASTE_GBR)"\`\
|
||||||
|
|:BOTTOM SOLDER MASK: - :code:\`"$(BOT_PASTE_GBR)"\`\
|
||||||
|
|:TOP PASTE MASK: - :code:\`"$(TOP_PASTE_GBR)"\`\
|
||||||
|
|:BOTTOM PASTE MASK: - :code:\`"$(BOT_PASTE_GBR)"\`\
|
||||||
|
|:TOP SILK SCREEN: - :code:\`"$(TOP_SILK_GBR)"\`\
|
||||||
|
|:BOTTOM SILK SCREEN: - :code:\`"$(BOT_SILK_GBR)"\`\
|
||||||
|
|:EXCELLON DRILL (Plated): - :code:\`"$(DRILL_PTH)"\`\
|
||||||
|
|:EXCELLON DRILL (Non-plated): :code:\`"$(DRILL_NPTH)"\`\
|
||||||
|
||Fab Drawings\
|
||||||
|
|============|\
|
||||||
|
|:$(FAB_TOP): - :code:\`3D rendering of the top of the bare PCB\`\
|
||||||
|
|:$(FAB_BOTTOM): - :code:\`3D rendering of the bottom of the bare PCB\`\
|
||||||
|
|\
|
||||||
|
|.. figure:: ./$(FAB_TOP)||\
|
||||||
|
| TOP side rendering of bare PCB||\
|
||||||
|
|.. figure:: ./$(FAB_BOTTOM)||\
|
||||||
|
| BOTTOM side rendering of bare PCB||\
|
||||||
|
|General Info\
|
||||||
|
|============|\
|
||||||
|
| * This board was developed with Kicad 6\
|
||||||
|
| * The Gerber files are in 2.5 RS274X format.\
|
||||||
|
||Special Instructions\
|
||||||
|
|====================|\
|
||||||
|
| * Please note there are TWO Excellon Drill files, one for plated through holes (PTH), and one for non-plated through holes (NPTH).\
|
||||||
|
| * The board outline is delineated in the Gerber file "$(OUTLN_GBR)"|\
|
||||||
|
|Thanks.
|
||||||
|
endef
|
||||||
|
|
||||||
|
define DRL_FAIL
|
||||||
|
|Missing drill file. To generate the drill files, within PCBNew:|\
|
||||||
|
|- Select File->Plot. Click "Generate Drill Files" at the bottom right side of the dialog.\
|
||||||
|
|- Select the following options:\
|
||||||
|
| * Excellon, \"Use route command\"\
|
||||||
|
| * Drill origin: Absolute\
|
||||||
|
| * Drill units: inches\
|
||||||
|
| * Zeros Format: Decimal format\
|
||||||
|
| * Precision: 2.4\
|
||||||
|
|- Select \"Generate Drill File\"|
|
||||||
|
endef
|
||||||
|
|
||||||
|
define GBR_FAIL
|
||||||
|
|Missing gerber file. To generate the gerber files, within PCBNew:|\
|
||||||
|
|- Select File->Plot. Click "Generate Drill Files" at the bottom right side of the dialog.\
|
||||||
|
|- Select the following layers:\
|
||||||
|
| * F.Cu\
|
||||||
|
| * B.Cu\
|
||||||
|
| * F.Silkscreen\
|
||||||
|
| * B.Silkscreen|\
|
||||||
|
$(INNER_LAYERS)\
|
||||||
|
| * F.Paste\
|
||||||
|
| * B.Paste\
|
||||||
|
| * F.Mask\
|
||||||
|
| * B.Mask\
|
||||||
|
| * Edge.Cuts|
|
||||||
|
endef
|
||||||
|
|
||||||
|
|
||||||
|
all: dummies copy renderfiles $(READMETARGET)
|
||||||
|
|
||||||
|
readmetxt: $(READMEFILETXT)
|
||||||
|
|
||||||
|
readmepdf: $(READMEFILEPDF)
|
||||||
|
|
||||||
|
$(READMEFILETXT): Makefile
|
||||||
|
@echo "Creating Readme File $(READMEFILETXT)."; \
|
||||||
|
echo "$(README_TEXT)"|tr '|' '\n' | sed 's/+++/ /g' > $(READMEFILETXT);
|
||||||
|
|
||||||
|
$(READMEFILEPDF): $(READMEFILETXT)
|
||||||
|
@echo "Creating Readme File $(READMEFILEPDF)."; \
|
||||||
|
pandoc -f rst -t pdf -o "$(READMEFILEPDF)" "$(READMEFILETXT)";
|
||||||
|
|
||||||
|
|
||||||
|
.Phony: renderfiles
|
||||||
|
renderfiles: renderfile_top renderfile_bottom
|
||||||
|
|
||||||
|
.Phony: renderfile_top
|
||||||
|
renderfile_top:
|
||||||
|
@if [ ! -f "$(FAB_TOP)" ]; then\
|
||||||
|
echo; \
|
||||||
|
echo "XXX Didn't find top assembly rendering: $(FAB_TOP). See makefile.log"; \
|
||||||
|
echo "|$(FAB_TOP_MSG)|"|tr '|' '\n' >> makefile.log; \
|
||||||
|
echo; \
|
||||||
|
else \
|
||||||
|
echo "--> Found top assembly rendering: $(FAB_TOP)"; \
|
||||||
|
fi
|
||||||
|
|
||||||
|
.Phony: renderfile_bottom
|
||||||
|
renderfile_bottom:
|
||||||
|
@if [ ! -f "$(FAB_BOTTOM)" ]; then\
|
||||||
|
echo; \
|
||||||
|
echo "XXX Didnt' find assembly rendering $(FAB_BOTTOM). See makefile.log";\
|
||||||
|
echo "|$(FAB_TOP_MSG)|"|tr '|' '\n' >> makefile.log; \
|
||||||
|
echo; \
|
||||||
|
else \
|
||||||
|
echo "--> Found bottom assembly rendering: $(FAB_BOTTOM)"; \
|
||||||
|
fi
|
||||||
|
|
||||||
|
renderfiles: renderfile_top renderfile_bottom
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(OUTPUT_EXTS) *rst *pdf *.zip $(DUMMY_TARGETS) *_
|
||||||
|
rm -f makefile.log
|
||||||
|
|
||||||
|
veryclean:
|
||||||
|
rm -rfv outputs $(PCBNAME)* $(NAME)*
|
||||||
|
rm -rfv *.jpg *.JPG *.pdf *.pdf *.png *.PNG
|
||||||
|
rm -f README* *rst *pdf *dvi
|
||||||
|
|
||||||
|
.PHONY: dummies
|
||||||
|
dummies:
|
||||||
|
@echo "Making placeholder filenames:"
|
||||||
|
@echo "$(DUMMY_TARGETS)" | xargs -n 1 echo +++
|
||||||
|
@touch $(DUMMY_TARGETS)
|
||||||
|
|
||||||
|
|
||||||
|
gvp: gvp_template.gvp
|
||||||
|
sed -e "s/@@NAME@@/$(PCBNAME)/" < $< > $(PCBNAME).gvp
|
||||||
|
|
||||||
|
copy:
|
||||||
|
cp $(DRILDIR)/$(NAME)-PTH.$(DRILL_EXT) $(DRILL_PTH) || echo "$(DRILL_FAIL)"|tr '|' '\n'
|
||||||
|
cp $(DRILDIR)/$(NAME)-NPTH.$(DRILL_EXT) $(DRILL_NPTH) || echo "$(DRILL_FAIL)"|tr '|' '\n'
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(TOP_SOLDER_DSC).$(TOP_SOLDER_EXT) $(TOP_SOLDER_GBR) || echo "$(GBR_FAIL)" | tr '|' '\n'
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(TOP_COPPER_DSC).$(TOP_COPPER_EXT) ./$(TOP_COPPER_GBR)
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(TOP_SILK_DSC).$(TOP_SILK_EXT) ./$(TOP_SILK_GBR)
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(BOT_SILK_DSC).$(BOT_SILK_EXT) ./$(BOT_SILK_GBR)
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(BOT_SOLDER_DSC).$(BOT_SOLDER_EXT) ./$(BOT_SOLDER_GBR)
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(BOT_COPPER_DSC).$(BOT_COPPER_EXT) ./$(BOT_COPPER_GBR)
|
||||||
|
ifeq ($(SMT),yes)
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(TOP_PASTE_DSC).$(TOP_PASTE_EXT) ./$(TOP_PASTE_GBR)
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(BOT_PASTE_DSC).$(BOT_PASTE_EXT) ./$(BOT_PASTE_GBR)
|
||||||
|
endif
|
||||||
|
ifeq ($(LAYERS),4)
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(GND1_DSC).$(GND1_EXT) ./$(GND1_GBR)
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(GND2_DSC).$(GND2_EXT) ./$(GND2_GBR)
|
||||||
|
endif
|
||||||
|
cp $(GERBDIR)/$(NAME)-$(OUTLN_DSC).$(OUTLN_EXT) ./$(OUTLN_GBR)
|
||||||
|
|
||||||
|
gerbv:
|
||||||
|
gerbv \
|
||||||
|
$(OUTLN_GBR) \
|
||||||
|
$(DRILL_PTH) \
|
||||||
|
$(DRILL_NPTH) \
|
||||||
|
$(TOP_SOLDER_GBR) \
|
||||||
|
$(TOP_COPPER_GBR) \
|
||||||
|
$(PASTE_LAYERS) \
|
||||||
|
$(TOP_SILK_GBR) \
|
||||||
|
$(BOT_SILK_GBR) \
|
||||||
|
$(BOT_SOLDER_GBR) \
|
||||||
|
$(BOT_COPPER_GBR) \
|
||||||
|
$(INNER_PLANES) \
|
||||||
|
$(BOT_SILK_GBR)
|
||||||
|
|
||||||
|
|
||||||
|
zip: all
|
||||||
|
rm -f $(ZIPFILE)
|
||||||
|
zip -9 $(ZIPFILE) \
|
||||||
|
$(OUTLN_GBR) \
|
||||||
|
$(DRILL_PTH) \
|
||||||
|
$(DRILL_NPTH) \
|
||||||
|
$(TOP_SOLDER_GBR) \
|
||||||
|
$(TOP_COPPER_GBR) \
|
||||||
|
$(PASTE_LAYERS) \
|
||||||
|
$(TOP_SILK_GBR) \
|
||||||
|
$(BOT_SOLDER_GBR) \
|
||||||
|
$(BOT_COPPER_GBR) \
|
||||||
|
$(BOT_SILK_GBR) \
|
||||||
|
$(INNER_PLANES) \
|
||||||
|
$(FAB_FILES) \
|
||||||
|
$(READMEFILEPDF) \
|
||||||
|
$(READMEFILETXT)
|
||||||
Binary file not shown.
@ -0,0 +1,4 @@
|
|||||||
|
Firmware Downloads
|
||||||
|
==================
|
||||||
|
|
||||||
|
Download the latest release of the firmware [here](https://osiweb.github.io/unified_retro_keyboard)
|
||||||
@ -0,0 +1,124 @@
|
|||||||
|
[BOM_OPTIONS]
|
||||||
|
; General BoM options here
|
||||||
|
; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
|
||||||
|
ignore_dnf = 0
|
||||||
|
; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
|
||||||
|
html_generate_dnf = 1
|
||||||
|
; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
|
||||||
|
use_alt = 1
|
||||||
|
; If 'alt_wrap' option is set to and integer N, the references field will wrap after N entries are printed
|
||||||
|
alt_wrap = 0
|
||||||
|
; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
|
||||||
|
number_rows = 1
|
||||||
|
; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
|
||||||
|
group_connectors = 1
|
||||||
|
; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
|
||||||
|
test_regex = 1
|
||||||
|
; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
|
||||||
|
merge_blank_fields = 1
|
||||||
|
; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
|
||||||
|
output_file_name = %O_bom_%v%V
|
||||||
|
; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
|
||||||
|
variant_file_name_format = _(%V)
|
||||||
|
; Field name used to determine if a particular part is to be fitted
|
||||||
|
fit_field = Fitted
|
||||||
|
; Make a backup of the bom before generating the new one, using the following template
|
||||||
|
make_backup = %O.tmp
|
||||||
|
; Default number of boards to produce if none given on CLI with -n
|
||||||
|
number_boards = 1
|
||||||
|
; Default PCB variant if none given on CLI with -r
|
||||||
|
board_variant = ['default']
|
||||||
|
; Whether to hide headers from output file
|
||||||
|
hide_headers = False
|
||||||
|
; Whether to hide PCB info from output file
|
||||||
|
hide_pcb_info = False
|
||||||
|
|
||||||
|
[IGNORE_COLUMNS]
|
||||||
|
; Any column heading that appears here will be excluded from the Generated BoM
|
||||||
|
; Titles are case-insensitive
|
||||||
|
|
||||||
|
Class
|
||||||
|
Component Type
|
||||||
|
Footprint
|
||||||
|
Footprint Lib
|
||||||
|
Material
|
||||||
|
Number of Pins
|
||||||
|
Package Variant
|
||||||
|
Part
|
||||||
|
Part Lib
|
||||||
|
Power Rating
|
||||||
|
RoHS China Link
|
||||||
|
RoHS Europe Link
|
||||||
|
SheetPath
|
||||||
|
Standards Version
|
||||||
|
Temp (Operating)
|
||||||
|
Temp (Soldering)
|
||||||
|
Temp (Storage)
|
||||||
|
Temp Coeff.
|
||||||
|
Tolerance
|
||||||
|
Value
|
||||||
|
Voltage Rating
|
||||||
|
Current Rating
|
||||||
|
|
||||||
|
|
||||||
|
[COLUMN_ORDER]
|
||||||
|
; Columns will apear in the order they are listed here
|
||||||
|
; Titles are case-insensitive
|
||||||
|
References
|
||||||
|
Fitted
|
||||||
|
Quantity Per PCB
|
||||||
|
Description
|
||||||
|
Part Value
|
||||||
|
Manufacturer
|
||||||
|
Manufacturer PN
|
||||||
|
Label
|
||||||
|
BOM Comment
|
||||||
|
|
||||||
|
|
||||||
|
[GROUP_FIELDS]
|
||||||
|
; List of fields used for sorting individual components into groups
|
||||||
|
; Components which match (comparing *all* fields) will be grouped together
|
||||||
|
; Field names are case-insensitive
|
||||||
|
Part
|
||||||
|
Part Lib
|
||||||
|
Value
|
||||||
|
Footprint
|
||||||
|
Footprint Lib
|
||||||
|
|
||||||
|
[COMPONENT_ALIASES]
|
||||||
|
; A series of values which are considered to be equivalent for the part name
|
||||||
|
; Each line represents a list of equivalent component name values separated by white space
|
||||||
|
; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
|
||||||
|
; Aliases are case-insensitive
|
||||||
|
c c_small cap capacitor
|
||||||
|
r r_small res resistor
|
||||||
|
sw switch
|
||||||
|
l l_small inductor
|
||||||
|
zener zenersmall
|
||||||
|
d diode d_small
|
||||||
|
|
||||||
|
[REGEX_INCLUDE]
|
||||||
|
; A series of regular expressions used to include parts in the BoM
|
||||||
|
; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
|
||||||
|
; Column names are case-insensitive
|
||||||
|
; Format is: "[ColumName] [Regex]" (white-space separated)
|
||||||
|
|
||||||
|
[REGEX_EXCLUDE]
|
||||||
|
; A series of regular expressions used to exclude parts from the BoM
|
||||||
|
; If a component matches ANY of these, it will be excluded from the BoM
|
||||||
|
; Column names are case-insensitive
|
||||||
|
; Format is: "[ColumName] [Regex]" (white-space separated)
|
||||||
|
References ^TP[0-9]*
|
||||||
|
References ^FID
|
||||||
|
Part mount.*hole
|
||||||
|
Part solder.*bridge
|
||||||
|
Part test.*point
|
||||||
|
Footprint test.*point
|
||||||
|
Footprint mount.*hole
|
||||||
|
Footprint fiducial
|
||||||
|
Allow Substitution
|
||||||
|
Tracking
|
||||||
|
Package
|
||||||
|
Manufacturer Link
|
||||||
|
Component Value
|
||||||
|
Datasheet
|
||||||
Loading…
x
Reference in New Issue
Block a user