2017-07-05 14:45:19 +00:00
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PR#3
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PREFIX /A2OSX.BUILD
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LOMEM $A00
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INC 1
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AUTO 6
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.LIST OFF
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*--------------------------------------
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2017-11-17 16:16:05 +00:00
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* HLINE X1,X2 at Y1 (XOR,SET,ORA)
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2017-07-05 14:45:19 +00:00
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*--------------------------------------
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2017-11-14 16:57:34 +00:00
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HLINE lda CB.Cache+S.CB.MODE
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2017-07-05 14:45:19 +00:00
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2017-11-14 16:57:34 +00:00
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cmp #S.CB.MODE.MONO
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bne HLINE.C16
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HLINE.MONO >LDYA CB.Cache+S.CB.X1
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jsr LBUF.SetBounds1YA
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>LDYA CB.Cache+S.CB.X2
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jsr LBUF.SetBounds2YA
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2017-07-05 14:45:19 +00:00
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2017-11-14 16:57:34 +00:00
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lda CB.Cache+S.CB.MODE
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2017-07-05 14:45:19 +00:00
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bit #S.CB.MODE.C16
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bne HLINE.C16
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2017-11-15 07:27:12 +00:00
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ldy CB.Cache+S.CB.COLOR
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2017-11-14 16:57:34 +00:00
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beq .1
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2017-07-05 14:45:19 +00:00
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2017-11-15 07:27:12 +00:00
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ldy #%01111111
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2017-07-05 14:45:19 +00:00
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2017-11-15 07:27:12 +00:00
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.1 ldx LBUF.C1
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2017-07-05 14:45:19 +00:00
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2017-11-15 07:27:12 +00:00
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.2 tya
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2017-11-16 07:12:03 +00:00
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sta LBUF.DATA,x
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2017-11-15 07:27:12 +00:00
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cpx LBUF.C2
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2017-11-16 16:46:18 +00:00
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inx
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bcc .2
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2017-07-05 14:45:19 +00:00
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2017-11-14 16:57:34 +00:00
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ldy CB.Cache+S.CB.Y1
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jmp LBUF.DrawAtY
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2017-07-05 14:45:19 +00:00
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2017-11-16 16:46:18 +00:00
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HLINE.C16 lda CB.Cache+S.CB.X1
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2017-11-14 16:57:34 +00:00
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and #%11111100
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tay
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lda CB.Cache+S.CB.X1+1
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2017-07-05 14:45:19 +00:00
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2017-11-14 16:57:34 +00:00
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jsr LBUF.SetBounds1YA
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2017-07-05 14:45:19 +00:00
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2017-11-14 16:57:34 +00:00
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lda CB.Cache+S.CB.X2
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2017-11-16 16:46:18 +00:00
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ora #%00000011
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2017-11-14 16:57:34 +00:00
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tay
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lda CB.Cache+S.CB.X2+1
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2017-07-05 14:45:19 +00:00
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2017-11-14 16:57:34 +00:00
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jsr LBUF.SetBounds2YA
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2017-11-15 07:27:12 +00:00
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lda CB.Cache+S.CB.COLOR
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asl
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asl
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clc
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adc L.Color.Pixels
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sta ZPPalettePtr
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lda L.Color.Pixels+1
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adc #0
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sta ZPPalettePtr+1
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2017-11-16 16:46:18 +00:00
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ldx LBUF.C1
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2017-11-15 07:27:12 +00:00
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.1 txa
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and #3 Compute index in Palette (Mod 4)
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2017-11-14 16:57:34 +00:00
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2017-11-15 07:27:12 +00:00
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tay
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lda (ZPPalettePtr),y
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2017-11-16 07:12:03 +00:00
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sta LBUF.DATA,x
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2017-11-15 07:27:12 +00:00
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cpx LBUF.C2
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2017-11-15 16:29:23 +00:00
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inx
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bcc .1
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2017-11-15 07:27:12 +00:00
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ldy CB.Cache+S.CB.Y1
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jmp LBUF.DrawAtY
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2017-07-05 14:45:19 +00:00
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rts
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*--------------------------------------
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2017-11-17 16:16:05 +00:00
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* VLINE Y1,Y2 at X1 (XOR,SET,ORA)
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2017-07-05 14:45:19 +00:00
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*--------------------------------------
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2017-11-17 16:16:05 +00:00
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VLINE lda CB.Cache+S.CB.MODE
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cmp #S.CB.MODE.MONO
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bne VLINE.C16
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2017-07-05 14:45:19 +00:00
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2017-11-17 16:16:05 +00:00
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VLINE.MONO >LDYA CB.Cache+S.CB.X1
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jsr DIVMOD7YA
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tay
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lda COL.OFS,y
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sta GBYTE Save COL (DIV)
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2017-07-05 14:45:19 +00:00
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2017-11-17 16:16:05 +00:00
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lda COL.BANK,y
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tay
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sta $C000,y Select proper BANK
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2017-07-05 14:45:19 +00:00
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2017-11-17 16:16:05 +00:00
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lda CB.Cache+S.CB.OP
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* cmp #S.CB.OP.XOR
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beq VLINE.MONO.XOR
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2017-07-05 14:45:19 +00:00
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2017-11-17 16:16:05 +00:00
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lda CB.Cache+S.CB.COLOR
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bne VLINE.MONO.WHITE
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2017-07-05 14:45:19 +00:00
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2017-11-17 16:16:05 +00:00
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VLINE.MONO.BLACK
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ldy CB.Cache+S.CB.Y1
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clc
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.1 lda BASEL,y
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adc GBYTE
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2017-11-15 07:27:12 +00:00
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sta ZPBasePtr
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2017-11-17 16:16:05 +00:00
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lda BASEH,y
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2017-11-15 07:27:12 +00:00
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sta ZPBasePtr+1
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2017-07-05 14:45:19 +00:00
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2017-11-17 16:16:05 +00:00
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lda (ZPBasePtr)
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and Mono.NMasks,x
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sta (ZPBasePtr)
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cpy CB.Cache+S.CB.Y2
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iny
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2017-07-05 14:45:19 +00:00
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bcc .1
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rts
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2017-11-17 16:16:05 +00:00
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VLINE.MONO.WHITE
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.1 lda BASEL,y
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adc GBYTE
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sta ZPBasePtr
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lda BASEH,y
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sta ZPBasePtr+1
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2017-07-05 14:45:19 +00:00
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2017-11-17 16:16:05 +00:00
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lda (ZPBasePtr)
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ora Mono.Masks,x
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sta (ZPBasePtr)
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cpy CB.Cache+S.CB.Y2
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iny
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bcc .1
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2017-07-05 14:45:19 +00:00
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2017-11-17 16:16:05 +00:00
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rts
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VLINE.MONO.XOR
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.1 lda BASEL,y
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adc GBYTE
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2017-11-15 07:27:12 +00:00
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sta ZPBasePtr
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2017-11-17 16:16:05 +00:00
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lda BASEH,y
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2017-11-15 07:27:12 +00:00
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sta ZPBasePtr+1
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2017-07-05 14:45:19 +00:00
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2017-11-17 16:16:05 +00:00
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lda (ZPBasePtr)
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eor Mono.Masks,x
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sta (ZPBasePtr)
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cpy CB.Cache+S.CB.Y2
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iny
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bcc .1
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2017-07-05 14:45:19 +00:00
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rts
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VLINE.C16 lda CB.Cache+S.CB.X1
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lsr CB.Cache+S.CB.X1+1 divide by 4
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ror
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lsr CB.Cache+S.CB.X1+1
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ror
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tay Y=X/4 (range 0->139)
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lda DIV7.0,y A=X/4/7 (range 0->19)
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asl times 2 (range 0->38)
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ldx CB.Cache+S.CB.Y1
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adc BASEL,x setup line Base Ptr (cc by asl)
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2017-11-15 07:27:12 +00:00
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sta ZPBasePtr ZPBasePtr now point to first of...
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2017-07-05 14:45:19 +00:00
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lda BASEH,x
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2017-11-15 07:27:12 +00:00
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sta ZPBasePtr+1 ...the 4 columns
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2017-07-05 14:45:19 +00:00
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lda MOD7.0,y get MOD
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asl times 4 to compute index in MASK tables
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asl
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tax set in X for Masks,NMasks
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lda CB.Cache+S.CB.COLOR
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asl times 4 to compute index in PIXELS table
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asl
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tay
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lda Color.Masks,x bits in 1st byte to light?
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beq .10
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2017-11-17 16:16:05 +00:00
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2017-07-05 14:45:19 +00:00
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and Color.Pixels,y apply color
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sta GBYTE
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sta SETPAGE2
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2017-11-15 07:27:12 +00:00
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lda (ZPBasePtr)
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2017-07-05 14:45:19 +00:00
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and Color.NMasks,x reset existing pixel,
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ora GBYTE
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2017-11-15 07:27:12 +00:00
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sta (ZPBasePtr)
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2017-07-05 14:45:19 +00:00
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.10 inx
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iny
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lda Color.Masks,x
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beq .11
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2017-11-17 16:16:05 +00:00
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2017-07-05 14:45:19 +00:00
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and Color.Pixels,y apply color
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sta GBYTE
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sta CLRPAGE2
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2017-11-15 07:27:12 +00:00
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lda (ZPBasePtr)
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2017-07-05 14:45:19 +00:00
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and Color.NMasks,x reset existing pixel,
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ora GBYTE
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2017-11-15 07:27:12 +00:00
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sta (ZPBasePtr)
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2017-07-05 14:45:19 +00:00
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2017-11-15 07:27:12 +00:00
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.11 inc ZPBasePtr
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2017-07-05 14:45:19 +00:00
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inx
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iny
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lda Color.Masks,x
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beq .12
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2017-11-17 16:16:05 +00:00
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2017-07-05 14:45:19 +00:00
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and Color.Pixels,y apply color
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sta GBYTE
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sta SETPAGE2
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2017-11-15 07:27:12 +00:00
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lda (ZPBasePtr)
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2017-07-05 14:45:19 +00:00
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and Color.NMasks,x reset existing pixel,
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ora GBYTE
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2017-11-15 07:27:12 +00:00
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sta (ZPBasePtr)
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2017-07-05 14:45:19 +00:00
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.12 inx
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iny
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lda Color.Masks,x
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beq .13
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2017-11-17 16:16:05 +00:00
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2017-07-05 14:45:19 +00:00
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and Color.Pixels,y apply color
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sta GBYTE
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sta CLRPAGE2
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2017-11-15 07:27:12 +00:00
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lda (ZPBasePtr)
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2017-07-05 14:45:19 +00:00
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and Color.NMasks,x reset existing pixel,
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ora GBYTE
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2017-11-15 07:27:12 +00:00
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sta (ZPBasePtr)
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2017-07-05 14:45:19 +00:00
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2017-11-14 16:57:34 +00:00
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.13 rts
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2017-07-05 14:45:19 +00:00
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*--------------------------------------
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MAN
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2017-11-14 16:57:34 +00:00
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SAVE /A2OSX.SRC/DRV/DHGR.DRV.S.LINE
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2017-07-05 14:45:19 +00:00
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LOAD /A2OSX.SRC/DRV/DHGR.DRV.S
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ASM
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