2015-03-14 21:48:35 +00:00
|
|
|
|
PR#3
|
2015-06-03 18:30:57 +00:00
|
|
|
|
PREFIX /A2OSX.SRC
|
2015-03-14 21:48:35 +00:00
|
|
|
|
NEW
|
|
|
|
|
|
INC 1
|
|
|
|
|
|
AUTO 6
|
|
|
|
|
|
.LIST OFF
|
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
|
* Software Switches
|
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
|
KBD .EQ $C000 R
|
|
|
|
|
|
CLR80STORE .EQ $C000 W
|
|
|
|
|
|
SET80STORE .EQ $C001 W
|
|
|
|
|
|
CLRREADAUX .EQ $C002 W
|
|
|
|
|
|
SETREADAUX .EQ $C003 W
|
|
|
|
|
|
CLRWRITEAUX .EQ $C004 W
|
|
|
|
|
|
SETWRITEAUX .EQ $C005 W
|
|
|
|
|
|
CLRCXROM .EQ $C006 W
|
|
|
|
|
|
SETCXROM .EQ $C007 W
|
|
|
|
|
|
CLRALTZP .EQ $C008 W
|
|
|
|
|
|
SETALTZP .EQ $C009 W
|
|
|
|
|
|
CLRC3ROM .EQ $C00A W
|
|
|
|
|
|
SETC3ROM .EQ $C00B W
|
|
|
|
|
|
CLR80DISP .EQ $C00C W
|
|
|
|
|
|
SET80DISP .EQ $C00D W
|
|
|
|
|
|
CLRALTCHAR .EQ $C00E W
|
|
|
|
|
|
SETALTCHAR .EQ $C00F W
|
|
|
|
|
|
KBDSTROBE .EQ $C010 W
|
2016-09-05 16:00:11 +00:00
|
|
|
|
RDLCBNK2 .EQ $C011 R
|
2015-03-14 21:48:35 +00:00
|
|
|
|
RDLCRAM .EQ $C012 R
|
|
|
|
|
|
RDREADAUX .EQ $C013 R
|
|
|
|
|
|
RDWRITEAUX .EQ $C014 R
|
|
|
|
|
|
RDCXROM .EQ $C015 R
|
|
|
|
|
|
RDALTZP .EQ $C016 R
|
|
|
|
|
|
RDC3ROM .EQ $C017 R
|
|
|
|
|
|
RD80STORE .EQ $C018 R
|
|
|
|
|
|
VBL .EQ $C019 R
|
|
|
|
|
|
RDTEXT .EQ $C01A R
|
|
|
|
|
|
RDMIXED .EQ $C01B R
|
|
|
|
|
|
RDPAGE2 .EQ $C01C R
|
|
|
|
|
|
RDHIRES .EQ $C01D R
|
|
|
|
|
|
RDALTCHAR .EQ $C01E R
|
|
|
|
|
|
RD80DISP .EQ $C01F R
|
|
|
|
|
|
TAPEOUT .EQ $C020 W
|
|
|
|
|
|
SPEAKER .EQ $C030 W, toggle speaker diaphragm
|
|
|
|
|
|
STROBE .EQ $C040 R, generate .5 uS low pulse @ Game pin 5
|
|
|
|
|
|
|
|
|
|
|
|
EMUBYTE .EQ $C04F WRR, Write once then Read EMUL, Read Version
|
|
|
|
|
|
|
|
|
|
|
|
CLRTEXT .EQ $C050 W
|
|
|
|
|
|
SETTEXT .EQ $C051 W
|
|
|
|
|
|
CLRMIXED .EQ $C052 W
|
|
|
|
|
|
SETMIXED .EQ $C053 W
|
|
|
|
|
|
CLRPAGE2 .EQ $C054 W
|
|
|
|
|
|
SETPAGE2 .EQ $C055 W
|
|
|
|
|
|
CLRHIRES .EQ $C056 W
|
|
|
|
|
|
SETHIRES .EQ $C057 W
|
|
|
|
|
|
|
|
|
|
|
|
SETAN0 .EQ $C058 W, Set annunciator-0 output to 0
|
|
|
|
|
|
CLRAN0 .EQ $C059 W, Set annunciator-0 output to 1
|
|
|
|
|
|
SETAN1 .EQ $C05A W, Set annunciator-1 output to 0
|
2016-02-24 20:02:55 +00:00
|
|
|
|
CLRAN1 .EQ $C05B W, Set annunciator-1 output to 1
|
|
|
|
|
|
ENBVBLIIC .EQ $C05B W, Enable VBL switch (IIc)
|
2015-03-14 21:48:35 +00:00
|
|
|
|
SETAN2 .EQ $C05C W, Set annunciator-2 output to 0
|
|
|
|
|
|
CLRAN2 .EQ $C05D W, Set annunciator-2 output to 1
|
|
|
|
|
|
SETAN3 .EQ $C05E W, Set annunciator-3 output to 0
|
|
|
|
|
|
SETDHIRES .EQ $C05E W, if IOUDIS Set, turn on double-hires
|
|
|
|
|
|
CLRAN3 .EQ $C05F W, Set annunciator-3 output to 1
|
|
|
|
|
|
CLRDHIRES .EQ $C05F W, if IOUDIS Set, turn off double-hires
|
|
|
|
|
|
|
|
|
|
|
|
TAPEIN .EQ $C060 R
|
|
|
|
|
|
|
|
|
|
|
|
OPENAPPLE .EQ $C061 R
|
|
|
|
|
|
SOLIDAPPLE .EQ $C062 R
|
|
|
|
|
|
PB2 .EQ $C063 R
|
|
|
|
|
|
|
|
|
|
|
|
PADDLE0 .EQ $C064 R, bit 7 = status of pdl-0 timer
|
|
|
|
|
|
PADDLE1 .EQ $C065 R, bit 7 = status of pdl-1 timer
|
|
|
|
|
|
PADDLE2 .EQ $C066 R, bit 7 = status of pdl-2 timer
|
|
|
|
|
|
PADDLE3 .EQ $C067 R, bit 7 = status of pdl-3 timer
|
|
|
|
|
|
PDLTRIG .EQ $C070 W, trigger paddles
|
|
|
|
|
|
|
|
|
|
|
|
SETIOUDIS .EQ $C07E W, enable DHIRES & disable $C058-5F
|
2016-02-24 20:02:55 +00:00
|
|
|
|
RDIOUDIS .EQ $C07E R, bit 7 = IOUDIS status
|
2015-03-14 21:48:35 +00:00
|
|
|
|
CLRIOUDIS .EQ $C07F W, disable DHIRES & enable $C058-5F
|
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
|
RRAMBNK2 .EQ $C080 R
|
|
|
|
|
|
RROMWRAMBNK2 .EQ $C081 RR
|
|
|
|
|
|
RROMBNK2 .EQ $C082 R
|
|
|
|
|
|
RRAMWRAMBNK2 .EQ $C083 RR
|
|
|
|
|
|
RRAMBNK1 .EQ $C088 R
|
|
|
|
|
|
RROMWRAMBNK1 .EQ $C089 RR
|
|
|
|
|
|
RROMBNK1 .EQ $C08A R
|
|
|
|
|
|
RRAMWRAMBNK1 .EQ $C08B RR
|
2016-09-05 16:00:11 +00:00
|
|
|
|
*--------------------------------------
|
|
|
|
|
|
CLRC8ROM .EQ $CFFF R, Release C800-CFFF Rom Space for all cards
|
2015-03-14 21:48:35 +00:00
|
|
|
|
MAN
|
|
|
|
|
|
SAVE INC/IO.I
|
