A2osX/DRV/DHGR.DRV.S.txt

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2017-12-22 21:24:30 +00:00
NEW
2019-07-25 15:10:59 +00:00
AUTO 3,1
.LIST OFF
2015-03-14 21:48:35 +00:00
.OP 65C02
.OR $2000
2019-12-04 06:56:03 +00:00
.TF drv/dhgr.drv
2015-03-14 21:48:35 +00:00
*--------------------------------------
2020-06-09 13:40:21 +00:00
.INB inc/macros.i
.INB inc/a2osx.i
.INB inc/mli.i
.INB inc/mli.e.i
.INB inc/io.i
.INB inc/gfx.i
.INB inc/gfx.eve.i
2021-06-05 15:48:54 +00:00
*--------------------------------------
.MA X2PageY
txa
lsr
ldy #SETPAGE2 col 0,2,4...in AUX mem
bcc :1 col 1,3,5...in MAIN mem
dey CLRPAGE2
:1 sta $C000,y
tay
.EM
2015-03-14 21:48:35 +00:00
*--------------------------------------
2020-07-01 15:40:32 +00:00
ZPPtr1 .EQ ZPBIN
ZPPtr2 .EQ ZPBIN+2
ZPPtr3 .EQ ZPBIN+4
2019-01-10 16:26:58 +00:00
*--------------------------------------
2015-06-03 18:30:57 +00:00
* File Header (16 Bytes)
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*--------------------------------------
CS.START cld
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jmp Dev.Detect cld,jmp abs=DRV
.DA #$61 6502,Level 1 (65c02)
.DA #1 DRV Layout Version 1
.DA 0
.DA CS.END-CS.START Code Length
2018-12-19 07:12:58 +00:00
.DA 0
.DA 0
.DA 0
2015-06-03 18:30:57 +00:00
*--------------------------------------
* Relocation Table
*--------------------------------------
L.MSG.DETECT .DA MSG.DETECT
L.MSG.DETECT.IIC .DA MSG.DETECT.IIC
L.MSG.DETECT.EVE .DA MSG.DETECT.EVE
L.MSG.DETECT.80C .DA MSG.DETECT.80C
2018-12-19 07:12:58 +00:00
L.DRV.CS.START .DA DRV.CS.START
L.FD.DEV .DA FD.DEV
L.FD.DEV.NAME .DA FD.DEV.NAME
2020-06-09 13:40:21 +00:00
*--------------------------------------
2020-07-02 06:11:15 +00:00
L.OSD .DA OSD
2015-06-03 18:30:57 +00:00
.DA 0 End Of Reloc Table
*--------------------------------------
Dev.Detect >LDYA L.MSG.DETECT
2020-02-28 07:21:46 +00:00
>SYSCALL PutS
2021-03-26 17:30:56 +00:00
lda A2osX.HWType
cmp #A2osX.HWType.IIc
bcc .1
2020-07-02 06:11:15 +00:00
2019-08-26 06:29:18 +00:00
* stz DCB+S.DCB.GFX.S //c : 80c Mode
>LDYA L.MSG.DETECT.IIC
bra .3
2020-07-02 06:11:15 +00:00
.1 php
sei
2019-01-10 16:26:58 +00:00
sta SET80STORE
sta SETPAGE2
ldx $400 Save Aux $400
lda #$ff Make sure !=1 for comparing later
sta $400
sta CLRPAGE2
ldy $400 Save Main $400
lda #$01 Select Foreground/BKgrnd Colors
sta TXT16.ON Activate 16 color mode
sta $400 Store something in Main
sta SETPAGE2
eor $400 read back AUX, If EVE, must be F/BG colors
bne .2
dec
2018-12-19 07:12:58 +00:00
sta DCB+S.DCB.GFX.S 0=80C,$ff=EVE
.2 stx $400 Set back Aux $400
sta CLRPAGE2
sty $400 Set back Main $400
2019-08-26 06:29:18 +00:00
sta TXT16.OFF
plp
>LDYA L.MSG.DETECT.EVE
2018-12-19 07:12:58 +00:00
bit DCB+S.DCB.GFX.S
bmi .3
2020-07-02 14:14:30 +00:00
>LDYA L.MSG.DETECT.80C
.3 >SYSCALL PutS
2018-12-19 07:12:58 +00:00
>PUSHWI DRV.END
2019-07-22 06:31:01 +00:00
>PUSHWI DRV.CS.END-DRV.CS.START
2018-12-19 07:12:58 +00:00
>PUSHWI DRV.CS.START
>LDYA L.DRV.CS.START
>SYSCALL InsDrv
bcs .9
2020-03-16 06:50:15 +00:00
2018-12-19 07:12:58 +00:00
>STYA FD.DEV+S.FD.DEV.DRVPTR
2020-03-16 06:50:15 +00:00
2020-07-01 15:40:32 +00:00
jsr DrvReloc
2020-03-16 06:50:15 +00:00
>PUSHW L.FD.DEV
2018-12-19 07:12:58 +00:00
>PUSHW L.FD.DEV.NAME
2020-08-25 14:54:30 +00:00
>SYSCALL MKDev
2019-01-10 16:26:58 +00:00
bcs .9
2020-06-09 13:40:21 +00:00
2019-01-10 16:26:58 +00:00
php
sei
>LDYAI $4000
>STYA $800
sta SETWRITEAUX
>STYA $800
sta CLRWRITEAUX
2020-07-02 14:14:30 +00:00
2020-09-05 13:38:04 +00:00
jsr ClrScr
2020-07-01 15:40:32 +00:00
jsr OSD.install
2019-01-11 16:06:05 +00:00
plp
.9 rts
*--------------------------------------
2020-06-09 13:40:21 +00:00
DrvReloc lda FD.DEV+S.FD.DEV.DRVPTR
sec
sbc #DRV.CS.START
2020-07-01 15:40:32 +00:00
sta ZPPtr1
2020-06-09 13:40:21 +00:00
lda FD.DEV+S.FD.DEV.DRVPTR+1
sbc /DRV.CS.START
2020-07-01 15:40:32 +00:00
sta ZPPtr1+1
lda ZPPtr1
clc
adc #Shift.L.LO
sta ZPPtr2
lda ZPPtr1+1
adc /Shift.L.LO+1
sta ZPPtr2+1
lda ZPPtr1
clc
adc #Shift.L.HI
sta ZPPtr3
lda ZPPtr1+1
adc /Shift.L.HI+1
sta ZPPtr3+1
2020-06-09 13:40:21 +00:00
2021-06-04 17:14:36 +00:00
ldy #5
2020-06-09 13:40:21 +00:00
2020-07-01 15:40:32 +00:00
.1 lda (ZPPtr2),y
2020-06-09 13:40:21 +00:00
clc
2020-07-01 15:40:32 +00:00
adc ZPPtr1
sta (ZPPtr2),y
2020-07-01 15:40:32 +00:00
lda (ZPPtr3),y
adc ZPPtr1+1
sta (ZPPtr3),y
2021-06-04 17:14:36 +00:00
dey
bpl .1
2020-06-09 13:40:21 +00:00
2020-07-01 15:40:32 +00:00
lda ZPPtr1
clc
adc #Shift.R.LO
sta ZPPtr2
2020-06-09 13:40:21 +00:00
2020-07-01 15:40:32 +00:00
lda ZPPtr1+1
adc /Shift.R.LO+1
sta ZPPtr2+1
lda ZPPtr1
2020-06-09 13:40:21 +00:00
clc
2020-07-01 15:40:32 +00:00
adc #Shift.R.HI
sta ZPPtr3
lda ZPPtr1+1
adc /Shift.R.HI+1
sta ZPPtr3+1
2020-06-09 13:40:21 +00:00
2021-06-04 17:14:36 +00:00
ldy #5
2020-07-01 15:40:32 +00:00
.2 lda (ZPPtr2),y
clc
adc ZPPtr1
sta (ZPPtr2),y
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lda (ZPPtr3),y
adc ZPPtr1+1
sta (ZPPtr3),y
2021-06-04 17:14:36 +00:00
dey
bpl .2
2020-06-09 13:40:21 +00:00
rts
*--------------------------------------
2020-07-02 06:11:15 +00:00
OSD.install >LDYA L.OSD
2020-07-01 15:40:32 +00:00
>STYA ZPPtr1
2020-07-02 06:11:15 +00:00
2020-07-01 15:40:32 +00:00
>LDYAI X.OSD
>STYA ZPPtr2
2020-07-02 06:11:15 +00:00
2020-07-01 15:40:32 +00:00
lda /X.OSD.LEN
eor #$ff
pha
2020-07-02 06:11:15 +00:00
lda #X.OSD.LEN
2020-07-01 15:40:32 +00:00
eor #$ff
tax
2020-07-01 15:40:32 +00:00
ldy #0
2020-07-01 15:40:32 +00:00
sta SETWRITEAUX
2020-07-01 15:40:32 +00:00
.1 inx
bne .2
2020-07-01 15:40:32 +00:00
pla
inc
2020-07-02 06:11:15 +00:00
beq .3
2020-07-01 15:40:32 +00:00
pha
2020-07-01 15:40:32 +00:00
.2 lda (ZPPtr1),y
sta (ZPPtr2),y
2020-07-01 15:40:32 +00:00
iny
bne .1
2020-07-02 06:11:15 +00:00
inc ZPPtr1+1
inc ZPPtr2+1
2020-07-01 15:40:32 +00:00
bra .1
2020-07-02 14:14:30 +00:00
.3 sta CLRWRITEAUX
2020-07-01 15:40:32 +00:00
rts
*--------------------------------------
2020-09-02 15:47:23 +00:00
ClrScr lda #$55
ldx #0
2020-09-05 13:38:04 +00:00
sta SETHIRES
sta SET80STORE
2020-07-02 14:14:30 +00:00
2019-07-30 15:35:42 +00:00
.1 ldy BASEL,x
2020-07-01 15:40:32 +00:00
sty ZPPtr1
2019-01-10 16:26:58 +00:00
ldy BASEH,x
2020-07-01 15:40:32 +00:00
sty ZPPtr1+1
2020-07-02 14:14:30 +00:00
2019-01-10 16:26:58 +00:00
sta SETPAGE2
2019-07-30 15:35:42 +00:00
jsr .2
2020-07-02 14:14:30 +00:00
2020-09-02 15:47:23 +00:00
eor #$7F
2019-01-10 16:26:58 +00:00
sta CLRPAGE2
2019-07-30 15:35:42 +00:00
jsr .2
2020-07-02 14:14:30 +00:00
2019-07-30 15:35:42 +00:00
inx
cpx #192
bne .1
rts
.2 ldy #39
2020-07-02 14:14:30 +00:00
2020-07-01 15:40:32 +00:00
.3 sta (ZPPtr1),y
2019-01-10 16:26:58 +00:00
dey
2019-07-30 15:35:42 +00:00
bpl .3
2020-07-02 14:14:30 +00:00
2019-01-11 16:06:05 +00:00
rts
2017-11-14 16:57:34 +00:00
*--------------------------------------
2015-06-03 18:30:57 +00:00
CS.END
2018-08-22 15:23:27 +00:00
MSG.DETECT .AZ "Apple IIe/IIc DHGR Driver."
2021-03-26 17:30:56 +00:00
MSG.DETECT.IIC .AZ "Apple //c,IIgs : 'LCM Feline/80c' Mode."
2019-08-26 06:29:18 +00:00
MSG.DETECT.EVE .AZ "Apple //e : 'LCM Eve' Board Detected."
MSG.DETECT.80C .AZ "No Specific H/W Found, 'Video7 80c' Mode."
2015-06-03 18:30:57 +00:00
*--------------------------------------
* Device Header (16 Bytes)
*--------------------------------------
2018-12-19 07:12:58 +00:00
FD.DEV .DA #S.FD.T.CDEV
.DA #0 HANDLER
.DA #0 BUSID
.DA #0 DEVID
.DA 0 BUSPTR
.BS 2 DRVPTR
.DA 0 DCBPTR
.DA 0 BUFPTR
2020-07-01 05:48:31 +00:00
FD.DEV.NAME .AZ "gfx"
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*--------------------------------------
* Driver Code
*--------------------------------------
2018-12-19 07:12:58 +00:00
ZPIOCTL .EQ ZPDRV
ZPBasePtr .EQ ZPDRV+2
ZPBMShiftPtr .EQ ZPDRV+4
ZPScrShiftPtr .EQ ZPDRV+6
ZPBMDataPtr .EQ ZPDRV+8
ZPBMMaskPtr .EQ ZPDRV+10
ZPBMSavePtr .EQ ZPDRV+12
*--------------------------------------
ZPTmpWord .EQ ZPDRV+14
*--------------------------------------
LBUF.C1 .EQ ZPDRV+16
LBUF.C1.MASK .EQ ZPDRV+17 Bits to CLR in VMEM : 11100000 00000000 00111111
LBUF.C1.DATA .EQ ZPDRV+18 Bits to SET/ORA/XOR : 000ccccc cccccccc cc000000
LBUF.C2 .EQ ZPDRV+19 C1 C2
LBUF.C2.MASK .EQ ZPDRV+20
LBUF.C2.DATA .EQ ZPDRV+21
*--------------------------------------
BLT.BMMaskPtr .EQ ZPDRV+22
BLT.BMDataPtr .EQ ZPDRV+24
BLT.BMBitOfs .EQ ZPDRV+26
BLT.BMBitOfsL .EQ ZPDRV+27
BLT.ScrBitOfs .EQ ZPDRV+28
BLT.ScrColIdx .EQ ZPDRV+29
BLT.CMASK .EQ ZPDRV+30
*--------------------------------------
ZPTmpByte .EQ ZPDRV+31
*--------------------------------------
DRV.CS.START cld
jmp (.1,x)
.1 .DA STATUS
.DA A2osX.BADCALL
.DA A2osX.BADCALL
.DA A2osX.BADCALL
.DA CONTROL
.DA A2osX.BADCALL
.DA OPEN
2015-03-14 21:48:35 +00:00
.DA CLOSE
.DA A2osX.BADCALL
2017-11-14 16:57:34 +00:00
.DA WRITE
*--------------------------------------
2017-11-14 16:57:34 +00:00
J.Cmds .DA SETPIXEL
2015-03-14 21:48:35 +00:00
.DA GETPIXEL
.DA HLINE
.DA VLINE
.DA FILLRECT
2015-03-14 21:48:35 +00:00
.DA BITBLT
.DA GETRECTBUFSIZE
*--------------------------------------
2020-10-12 06:04:19 +00:00
J.LBUF.DrawAtY .DA $ffff
.DA LBUF.DrawAtY.XOR
.DA LBUF.DrawAtY.SET
.DA LBUF.DrawAtY.ORA
.DA $ffff
.DA LBUF.DrawAtY.AND.XOR
.DA LBUF.DrawAtY.AND.SET
.DA LBUF.DrawAtY.AND.ORA
2019-10-03 06:25:27 +00:00
L.Color.Pixels .DA Color.Pixels
2015-03-14 21:48:35 +00:00
.DA 0 end or relocation
*--------------------------------------
2018-12-19 07:12:58 +00:00
STATUS >STYA ZPIOCTL
2019-01-09 16:42:20 +00:00
ldy #S.IOCTL.BUFPTR
lda (ZPIOCTL),y
sta ZPBasePtr
iny
2019-01-09 16:42:20 +00:00
lda (ZPIOCTL),y
sta ZPBasePtr+1
2021-05-04 17:31:21 +00:00
ldy #S.IOCTL.S
2018-12-19 07:12:58 +00:00
lda (ZPIOCTL),y
beq .1
2021-05-04 17:31:21 +00:00
cmp #S.IOCTL.S.GETDIB
2018-12-19 07:12:58 +00:00
bne STATUS.DCB
2019-01-09 16:42:20 +00:00
ldy #S.DIB-1
2018-12-19 07:12:58 +00:00
.HS 2C bit abs
2019-01-09 16:42:20 +00:00
.1 ldy #3
.2 lda DIB,y
sta (ZPBasePtr),y
dey
2018-12-19 07:12:58 +00:00
bpl .2
clc
rts
2018-12-19 07:12:58 +00:00
2021-05-04 17:31:21 +00:00
STATUS.DCB cmp #S.IOCTL.S.GETDCB
2019-01-09 16:42:20 +00:00
bne STATUS.9
ldy #S.DCB.GFX-1
.2 lda DCB,y
sta (ZPBasePtr),y
dey
bpl .2
clc
rts
2020-06-09 13:40:21 +00:00
2018-12-19 07:12:58 +00:00
STATUS.9 lda #MLI.E.BADCTL
sec
rts
*--------------------------------------
2019-08-02 14:36:49 +00:00
OPEN tax DEV.ID in A
2019-08-02 14:36:49 +00:00
lda #S.DIB.S.OPENED
bit DIB+S.DIB.S
bne CLOSE.IOE
2020-03-12 07:46:43 +00:00
lda A2osX.SCRNDEVS+9
2020-06-09 13:40:21 +00:00
beq .1
2018-12-20 16:23:43 +00:00
lda #E.OOH
sec
rts
2020-06-09 13:40:21 +00:00
.1 stx A2osX.SCRNDEVS+9
2020-03-12 07:46:43 +00:00
stx DCB+S.DCB.GFX.DEVID
2019-01-09 16:42:20 +00:00
2018-12-20 16:23:43 +00:00
lda #S.DIB.S.OPENED
tsb DIB+S.DIB.S
2015-03-14 21:48:35 +00:00
*--------------------------------------
2019-01-09 16:42:20 +00:00
CONTROL lda DCB+S.DCB.GFX.DEVID NON STANDARD
2019-01-08 16:29:26 +00:00
cmp A2osX.ASCREEN
beq .8
2019-01-08 16:29:26 +00:00
sta A2osX.ASCREEN
2020-03-12 07:46:43 +00:00
2019-01-08 16:29:26 +00:00
ldy #0
2019-08-26 06:29:18 +00:00
2018-12-19 07:12:58 +00:00
bit DCB+S.DCB.GFX.S
2019-08-26 06:29:18 +00:00
bpl .1 //c,EVE mode
2020-03-12 07:46:43 +00:00
2019-08-26 06:29:18 +00:00
ldy #CONTROL.EVE-CONTROL.80C
2020-03-12 07:46:43 +00:00
2019-08-26 06:29:18 +00:00
.1 ldx CONTROL.80C,y
beq .8 Ending 0
sta $C000,x
iny
bra .1
2019-08-02 14:36:49 +00:00
.8 clc
rts
2020-03-12 07:46:43 +00:00
2019-08-02 14:36:49 +00:00
CLOSE.IOE lda #MLI.E.IO
sec
rts
2016-06-07 06:10:18 +00:00
*--------------------------------------
2019-08-02 14:36:49 +00:00
CLOSE lda #S.DIB.S.OPENED
bit DIB+S.DIB.S
beq CLOSE.IOE
2019-08-02 14:36:49 +00:00
trb DIB+S.DIB.S
2020-03-12 07:46:43 +00:00
stz A2osX.SCRNDEVS+9
2019-08-02 14:36:49 +00:00
clc
rts
2017-11-14 16:57:34 +00:00
*--------------------------------------
2018-12-20 16:23:43 +00:00
WRITE >STYA ZPIOCTL NON STANDARD
2020-07-04 19:00:47 +00:00
2018-12-19 07:12:58 +00:00
lda (ZPIOCTL) Get Cmd
2020-07-02 06:11:15 +00:00
bmi .2
2020-07-02 06:11:15 +00:00
pha
2020-09-02 15:47:23 +00:00
lsr
tax
ldy CB.CmdLen-1,x
2020-07-02 06:11:15 +00:00
.1 lda (ZPIOCTL),y
2017-11-14 16:57:34 +00:00
sta CB.Cache,y
dey
2020-07-02 06:11:15 +00:00
bpl .1
2020-07-02 06:11:15 +00:00
plx
2020-09-02 15:47:23 +00:00
jmp (J.Cmds-2,x)
2020-06-09 13:40:21 +00:00
2020-07-02 06:11:15 +00:00
.2 sta SETWRITEAUX
2020-09-03 06:24:36 +00:00
2020-07-02 06:11:15 +00:00
and #$7f
2020-09-02 15:47:23 +00:00
sta CBX.Cache
lsr
2020-07-02 06:11:15 +00:00
tax
2020-09-02 15:47:23 +00:00
ldy CB.CmdLen-1,x
2020-07-02 06:11:15 +00:00
.3 lda (ZPIOCTL),y
sta CBX.Cache,y
dey
2020-09-02 15:47:23 +00:00
bne .3
2020-07-01 15:40:32 +00:00
sta SETREADAUX
2020-07-02 06:11:15 +00:00
jsr X.OSD
sta CLRREADAUX
sta CLRWRITEAUX
rts
2017-11-14 16:57:34 +00:00
*--------------------------------------
* IN:
* Y = LO
2017-11-14 16:57:34 +00:00
* A = HI
* OUT:
* A = DIV
* X = MOD
*--------------------------------------
2017-11-14 16:57:34 +00:00
DIVMOD7YA dec
bmi .2
2020-06-09 13:40:21 +00:00
clc
beq .1
2020-06-09 13:40:21 +00:00
lda DIV7.512,y
adc #$49
ldx MOD7.512,y
rts
.1 lda DIV7.256,y
adc #$24
ldx MOD7.256,y
rts
2020-06-09 13:40:21 +00:00
.2 lda DIV7.0,y
ldx MOD7.0,y
2019-10-03 06:25:27 +00:00
rts
2015-03-14 21:48:35 +00:00
*--------------------------------------
* IN:
* Y,A = num1 (16)
* X = num2 (8)
* OUT:
* Y,A = (Y,A) * X
*--------------------------------------
YAMultX stx ZPTmpByte
sty ZPTmpWord
sta ZPTmpWord+1
ldy #0 Result LO
tya Result HI
bra .3
.1 pha
tya
clc
adc ZPTmpWord
tay
pla
adc ZPTmpWord+1
.2 asl ZPTmpWord
rol ZPTmpWord+1
2020-06-09 13:40:21 +00:00
.3 lsr ZPTmpByte
bcs .1
2020-06-09 13:40:21 +00:00
bne .2
rts
*--------------------------------------
2020-06-09 13:40:21 +00:00
.INB usr/src/drv/dhgr.drv.s.blt
.INB usr/src/drv/dhgr.drv.s.lbuf
.INB usr/src/drv/dhgr.drv.s.line
.INB usr/src/drv/dhgr.drv.s.pix
.INB usr/src/drv/dhgr.drv.s.rect
*--------------------------------------
2015-06-03 18:30:57 +00:00
DRV.CS.END
*--------------------------------------
2020-06-09 13:40:21 +00:00
.INB usr/src/drv/dhgr.drv.g
*--------------------------------------
2019-08-26 06:29:18 +00:00
CONTROL.80C .DA #SETIOUDIS
.DA #CLRTEXT
2020-07-04 19:00:47 +00:00
* .DA #SETHIRES
2020-09-06 12:24:04 +00:00
.DA #CLR80DISP
2019-08-26 06:29:18 +00:00
.DA #SETAN3
.DA #CLRAN3
.DA #SETAN3
.DA #CLRAN3
.DA #SET80DISP
2019-08-26 06:29:18 +00:00
.DA #SETAN3
.DA #CLRAN3
.DA #SETAN3
2019-08-26 06:29:18 +00:00
.DA #0
2020-06-09 13:40:21 +00:00
2019-08-26 06:29:18 +00:00
CONTROL.EVE .DA #SETIOUDIS
.DA #CLRTEXT
2020-07-04 19:00:47 +00:00
* .DA #SETHIRES
2019-08-26 06:29:18 +00:00
.DA #HR1.OFF
.DA #HR2.ON
.DA #HR3.ON
2020-06-09 13:40:21 +00:00
2019-08-26 06:29:18 +00:00
.DA #0
*--------------------------------------
2020-07-01 15:40:32 +00:00
Shift.L.LO .DA #SHIFT.L1
.DA #SHIFT.L2
.DA #SHIFT.L3
.DA #SHIFT.L4
.DA #SHIFT.L5
.DA #SHIFT.L6
Shift.L.HI .DA /SHIFT.L1
.DA /SHIFT.L2
.DA /SHIFT.L3
.DA /SHIFT.L4
.DA /SHIFT.L5
.DA /SHIFT.L6
Shift.R.LO .DA #SHIFT.L6
.DA #SHIFT.L5
.DA #SHIFT.L4
.DA #SHIFT.L3
.DA #SHIFT.L2
.DA #SHIFT.L1
Shift.R.HI .DA /SHIFT.L6
.DA /SHIFT.L5
.DA /SHIFT.L4
.DA /SHIFT.L3
.DA /SHIFT.L2
.DA /SHIFT.L1
*--------------------------------------
2020-07-02 06:11:15 +00:00
CB.CmdLen .DA #S.CB.Y1+1 SETPIXEL
.DA #S.CB.Y1+1 GETPIXEL
.DA #S.CB.X2+1 HLINE
.DA #S.CB.Y2+1 VLINE
.DA #S.CB.Y2+1 FILLRECT
.DA #S.CB.DstPtr+1 BITBLT
.DA #S.CB.DstPtr+1 GETRECTBUFSIZE
.DA #S.CB.TxtPtr+1 DRAWTEXT
2020-09-04 15:21:15 +00:00
.DA #S.CB.TxtPtr+1 GETTEXTSIZE
2017-11-14 16:57:34 +00:00
*--------------------------------------
CB.Cache .BS S.CB
BM.Cache .BS S.BM
2017-11-14 16:57:34 +00:00
*--------------------------------------
LBUF.MASK .BS 81 81 because of sta LBUF.DATA+1,x!!!
LBUF.DATA .BS 81
*--------------------------------------
2018-12-19 07:12:58 +00:00
DIB .DA #0
.DA #0,#0,#0
.PS "Apple II DHGR"
.BS 3
2018-07-19 15:33:55 +00:00
.DA #S.DIB.T.GFX
.DA #0
.DA #00,#94
*--------------------------------------
2018-12-19 07:12:58 +00:00
DCB .DA #S.DCB.T.GFX
2018-12-20 16:23:43 +00:00
.BS 1 DEV.ID
2019-08-26 06:29:18 +00:00
.DA #0 S.DCB.GFX.S default to 0
2018-12-19 07:12:58 +00:00
.DA #S.CB.M.MONO+S.CB.M.C16 F
.DA 560 W
.DA 192 H
2016-06-22 21:12:09 +00:00
*--------------------------------------
2018-12-19 07:12:58 +00:00
DRV.END
2020-07-01 15:40:32 +00:00
*--------------------------------------
2020-07-02 06:11:15 +00:00
OSD .PH $1000
2020-07-01 15:40:32 +00:00
.INB usr/src/drv/dhgr.drv.s.osd
.EP
*--------------------------------------
2019-01-09 16:42:20 +00:00
.LIST ON
2018-12-20 16:23:43 +00:00
DRV.CS.SIZE .EQ DRV.CS.END-DRV.CS.START
DRV.SIZE .EQ DRV.END-DRV.CS.START
2019-01-09 16:42:20 +00:00
.LIST OFF
2015-03-14 21:48:35 +00:00
MAN
2020-06-09 13:40:21 +00:00
SAVE usr/src/drv/dhgr.drv.s
2015-03-14 21:48:35 +00:00
ASM