2015-03-14 21:48:35 +00:00
|
|
|
|
NEW
|
2019-10-09 10:05:08 +00:00
|
|
|
|
AUTO 3,1
|
2015-03-14 21:48:35 +00:00
|
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|
|
.LIST OFF
|
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|
|
|
.OP 65C02
|
|
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|
|
.OR $2000
|
2020-04-10 11:22:09 +00:00
|
|
|
|
.TF sys/km.ramworks
|
2015-03-14 21:48:35 +00:00
|
|
|
|
*--------------------------------------
|
2021-02-26 20:13:48 +00:00
|
|
|
|
.INB inc/macros.i
|
|
|
|
|
.INB inc/io.i
|
|
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|
.INB inc/monitor.i
|
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|
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|
.INB inc/mli.i
|
|
|
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|
.INB inc/mli.e.i
|
2015-03-14 21:48:35 +00:00
|
|
|
|
*--------------------------------------
|
|
|
|
|
TmpPtr1 .EQ $0
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|
TmpPtr2 .EQ $2
|
2021-09-07 12:32:31 +00:00
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|
Type .EQ $4
|
2015-03-14 21:48:35 +00:00
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|
|
|
*--------------------------------------
|
2017-02-18 22:23:00 +00:00
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|
|
RW.SAVEZP0 .EQ $800
|
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|
|
|
RW.SAVEZP1 .EQ $900
|
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|
|
|
*--------------------------------------
|
|
|
|
|
RW.BLOCK .EQ $A00
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|
|
|
|
*--------------------------------------
|
|
|
|
|
* A2OSX.SYSTEM relocated at $1000 !!!
|
|
|
|
|
*--------------------------------------
|
2021-09-07 12:32:31 +00:00
|
|
|
|
SEBankSelect .EQ $C071
|
2015-03-14 21:48:35 +00:00
|
|
|
|
RWBankSelect .EQ $C073
|
|
|
|
|
*--------------------------------------
|
2018-07-12 15:20:39 +00:00
|
|
|
|
RW.Init >LDYAI RW.MSG
|
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|
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jsr PrintFYA
|
2021-09-07 12:32:31 +00:00
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jsr RW.DetectRAM3
|
2015-03-14 21:48:35 +00:00
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bcs .10
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|
2018-07-12 15:20:39 +00:00
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>LDYAI RW.MSG.OK
|
|
|
|
|
jsr PrintFYA
|
2015-03-14 21:48:35 +00:00
|
|
|
|
rts
|
|
|
|
|
|
2021-09-07 12:32:31 +00:00
|
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|
|
.10 lda #RWBankSelect
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|
jsr RW.DetectHW
|
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bcc .1
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lda #SEBankSelect
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jsr RW.DetectHW
|
2015-03-14 21:48:35 +00:00
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bcc .1
|
2020-07-18 14:04:21 +00:00
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|
|
2018-07-12 15:20:39 +00:00
|
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|
|
>LDYAI RW.MSG.KO1
|
2020-08-07 19:49:24 +00:00
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|
bra .9
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.1 tay save RAM drive pages
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pha
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|
|
lsr divide by 4 to compute KB size
|
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|
ror .12+1
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lsr
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|
ror .12+1
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|
.12 ldx #$00 X,A = RAM drive size
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|
phx Push Kbyte LO
|
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|
pha Push Kbyte HI
|
2020-07-18 14:04:21 +00:00
|
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|
|
2020-08-07 19:49:24 +00:00
|
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|
|
tya
|
|
|
|
|
inc + 1 page AUX mem
|
2021-02-26 20:13:48 +00:00
|
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|
2020-08-07 19:49:24 +00:00
|
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|
|
pha Total page detected
|
2016-12-12 11:05:47 +00:00
|
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|
|
lsr divide by 4 to compute KB size
|
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|
ror .11+1
|
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lsr
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|
ror .11+1
|
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|
2020-08-07 19:49:24 +00:00
|
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|
.11 ldx #$00 X,A = Total KB detected
|
2017-02-19 11:22:00 +00:00
|
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|
phx Push Kbyte LO
|
2017-04-10 08:58:45 +00:00
|
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|
|
pha Push Kbyte HI
|
2016-12-12 11:05:47 +00:00
|
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|
|
2018-07-12 15:20:39 +00:00
|
|
|
|
>LDYAI RW.MSG.OK1
|
|
|
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|
jsr PrintFYA
|
2015-03-14 21:48:35 +00:00
|
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|
|
jsr RW.Install
|
|
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bcc .2
|
|
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|
|
2018-07-12 15:20:39 +00:00
|
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|
|
>LDYAI RW.MSG.KO2
|
2020-08-07 19:49:24 +00:00
|
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|
bra .9
|
2015-03-14 21:48:35 +00:00
|
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|
|
2018-07-12 15:20:39 +00:00
|
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|
.2 >LDYAI RW.MSG.OK2
|
|
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|
jsr PrintFYA
|
2015-03-14 21:48:35 +00:00
|
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|
|
jsr RW.Format
|
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|
bcc .3
|
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|
2018-07-12 15:20:39 +00:00
|
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>LDYAI RW.MSG.KO3
|
2020-08-07 19:49:24 +00:00
|
|
|
|
bra .9
|
2021-02-26 20:13:48 +00:00
|
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|
|
2018-07-12 15:20:39 +00:00
|
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|
.3 >LDYAI RW.MSG.OK3
|
2020-08-07 19:49:24 +00:00
|
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|
.9 jsr PrintFYA
|
2015-03-14 21:48:35 +00:00
|
|
|
|
rts
|
|
|
|
|
*--------------------------------------
|
2021-09-07 12:32:31 +00:00
|
|
|
|
RW.DetectRAM3 jsr MLI
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.DA #MLIONLINE
|
|
|
|
|
.DA RW.ONLINE
|
|
|
|
|
rts
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
RW.ONLINE .DA #2
|
2016-12-12 11:05:47 +00:00
|
|
|
|
.DA #$B0 Slot 3,Drive 2
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.DA RW.ONLINEBUFFER
|
|
|
|
|
RW.ONLINEBUFFER .BS 16
|
|
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|
|
*--------------------------------------
|
2021-09-07 12:32:31 +00:00
|
|
|
|
RW.DetectHW php
|
2015-03-14 21:48:35 +00:00
|
|
|
|
sei
|
2021-09-07 12:32:31 +00:00
|
|
|
|
sta Type
|
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|
sta .1+1
|
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sta .2+1
|
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sta .3+1
|
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sta .6+1
|
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|
|
2015-03-14 21:48:35 +00:00
|
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|
|
sta SETALTZP
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
ldx #0 start detection at page $00
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.1 stx RWBankSelect
|
|
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|
|
lda 0
|
2020-07-18 14:04:21 +00:00
|
|
|
|
sta RW.SAVEZP0,x save Bank 0 $0000 to prevent ALTZP trash
|
2015-03-14 21:48:35 +00:00
|
|
|
|
lda 1
|
|
|
|
|
sta RW.SAVEZP1,x
|
|
|
|
|
inx
|
2017-02-18 22:23:00 +00:00
|
|
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|
bpl .1
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
lda #0
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.2 sta RWBankSelect
|
2016-01-06 18:45:59 +00:00
|
|
|
|
*--------------------------------------
|
2016-03-13 21:46:25 +00:00
|
|
|
|
* Added after David Finnigan from macgui.com testing sessions
|
2021-02-26 20:13:48 +00:00
|
|
|
|
*
|
2016-12-12 11:05:47 +00:00
|
|
|
|
pha
|
|
|
|
|
pla
|
2021-02-26 20:13:48 +00:00
|
|
|
|
*
|
2016-03-13 21:46:25 +00:00
|
|
|
|
* to address possibly a timing issue with Accelerators
|
2016-01-06 18:45:59 +00:00
|
|
|
|
*--------------------------------------
|
2015-03-14 21:48:35 +00:00
|
|
|
|
sta 0
|
|
|
|
|
eor #$FF
|
|
|
|
|
sta 1
|
|
|
|
|
eor #$FF
|
|
|
|
|
inc
|
2017-02-18 22:23:00 +00:00
|
|
|
|
bpl .2
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
ldx #0
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-12-15 13:23:22 +00:00
|
|
|
|
.3 stx RWBankSelect
|
2016-06-23 20:18:29 +00:00
|
|
|
|
*--------------------------------------
|
|
|
|
|
* Added after David Finnigan from macgui.com testing sessions
|
2021-02-26 20:13:48 +00:00
|
|
|
|
*
|
2016-12-12 11:05:47 +00:00
|
|
|
|
pha
|
|
|
|
|
pla
|
2021-02-26 20:13:48 +00:00
|
|
|
|
*
|
2016-06-23 20:18:29 +00:00
|
|
|
|
* to address possibly a timing issue with Accelerators
|
|
|
|
|
*--------------------------------------
|
2020-12-15 13:23:22 +00:00
|
|
|
|
lda 0
|
|
|
|
|
tay
|
|
|
|
|
eor #$ff
|
2015-03-14 21:48:35 +00:00
|
|
|
|
cmp 1
|
|
|
|
|
bne .4
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
inx
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2020-12-15 13:23:22 +00:00
|
|
|
|
cpy #127
|
|
|
|
|
bne .3
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2021-02-26 20:13:48 +00:00
|
|
|
|
.4 ldy #127 X = detected page count
|
2015-03-14 21:48:35 +00:00
|
|
|
|
|
|
|
|
|
.6 sty RWBankSelect
|
2016-03-13 21:46:25 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
lda RW.SAVEZP0,y
|
|
|
|
|
sta 0
|
|
|
|
|
lda RW.SAVEZP1,y
|
|
|
|
|
sta 1
|
|
|
|
|
dey
|
2017-02-18 22:23:00 +00:00
|
|
|
|
bpl .6
|
2015-03-14 21:48:35 +00:00
|
|
|
|
|
|
|
|
|
sta CLRALTZP
|
|
|
|
|
plp
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
|
|
|
|
txa PGCNT > 0 ?
|
|
|
|
|
beq .9
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-08-07 19:49:24 +00:00
|
|
|
|
dec minus 1 for AUX mem
|
|
|
|
|
beq .9
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-08-07 19:49:24 +00:00
|
|
|
|
sta RW.PGCNT PGCNT = last detected page
|
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
clc
|
|
|
|
|
rts
|
2020-07-17 15:18:31 +00:00
|
|
|
|
|
2019-10-03 06:25:27 +00:00
|
|
|
|
.9 sec
|
2015-03-14 21:48:35 +00:00
|
|
|
|
rts
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
RW.Install lda RRAMWRAMBNK1
|
|
|
|
|
lda RRAMWRAMBNK1
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
ldx #RWDRV.SIZE
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.1 lda RWDRV.B.START-1,x
|
|
|
|
|
sta RWDRV.START-1,x
|
|
|
|
|
dex
|
|
|
|
|
bne .1
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
lda RW.PGCNT
|
|
|
|
|
lsr
|
|
|
|
|
sta RWDRV.MAXHI+1
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
lda #0
|
|
|
|
|
ror
|
|
|
|
|
sta RWDRV.MAXLO+1
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2021-09-07 12:32:31 +00:00
|
|
|
|
lda Type
|
|
|
|
|
sta RWDRV.IO1+1
|
|
|
|
|
sta RWDRV.EXIT+1
|
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
lda RROMBNK1
|
2021-09-07 12:32:31 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
sta SETWRITEAUX
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
ldx #RWDRVX.SIZE
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.2 lda RWDRVX.B.START-1,x
|
|
|
|
|
sta RWDRVX.START-1,x
|
|
|
|
|
dex
|
|
|
|
|
bne .2
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2021-09-07 12:32:31 +00:00
|
|
|
|
lda Type
|
|
|
|
|
sta RWDRVX.XM.IO1+1
|
|
|
|
|
sta RWDRVX.XM.IO2+1
|
|
|
|
|
sta RWDRVX.XM.IO3+1
|
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
sta CLRWRITEAUX
|
|
|
|
|
inc DEVCNT
|
|
|
|
|
ldx DEVCNT
|
2016-12-12 11:05:47 +00:00
|
|
|
|
lda #$B0 Slot 3,Drive 2,0=Not Removable, 0=no int, 00=1 Volume
|
2015-03-14 21:48:35 +00:00
|
|
|
|
sta DEVLST,x
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
lda #RWDRV.START
|
2016-12-12 11:05:47 +00:00
|
|
|
|
sta DEVPTRS3D2
|
2015-03-14 21:48:35 +00:00
|
|
|
|
lda /RWDRV.START
|
2016-12-12 11:05:47 +00:00
|
|
|
|
sta DEVPTRS3D2+1
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
clc
|
|
|
|
|
rts
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
RW.Format jsr RW.BLOCK.SET00
|
|
|
|
|
lda RW.PGCNT
|
|
|
|
|
lsr
|
|
|
|
|
sta RW.BLOCK2.TB+1
|
|
|
|
|
lda #0
|
|
|
|
|
ror
|
|
|
|
|
sta RW.BLOCK2.TB
|
|
|
|
|
jsr MLI
|
|
|
|
|
.DA #MLIGETTIME
|
|
|
|
|
.DA 0
|
|
|
|
|
ldx #3
|
2019-10-03 06:25:27 +00:00
|
|
|
|
.1 lda DATELO,x
|
2015-03-14 21:48:35 +00:00
|
|
|
|
sta RW.BLOCK2.CT,x
|
|
|
|
|
dex
|
|
|
|
|
bpl .1
|
|
|
|
|
ldx #RW.BLOCK2.END-RW.BLOCK2
|
|
|
|
|
.2 lda RW.BLOCK2-1,x
|
|
|
|
|
sta RW.BLOCK-1,x
|
|
|
|
|
dex
|
|
|
|
|
bne .2
|
|
|
|
|
|
|
|
|
|
jsr MLI Write Block 2,First VOL directory block
|
|
|
|
|
.DA #MLIWRITEBLOCK
|
|
|
|
|
.DA RW.MLIWRITEBLOCK
|
|
|
|
|
bcc .22
|
|
|
|
|
rts
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
.22 jsr RW.BLOCK.SET00
|
|
|
|
|
|
|
|
|
|
lda #2
|
|
|
|
|
sta RW.BLOCK LO byte of previous block pointer
|
|
|
|
|
|
|
|
|
|
inc RW.MLIWRITEBLOCK.BLK
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jsr MLI Write Block 3,Last VOL directory block
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.DA #MLIWRITEBLOCK
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.DA RW.MLIWRITEBLOCK
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bcc .33
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rts
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*--------------------------------------
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.33 lda RW.PGCNT divide RW.PGCNT by 32 to get how many bitmap
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lsr blocks we need :
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lsr 1 page = 128 blocks = 16 bytes
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lsr 32 pages = 512 bytes = 1 Block
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lsr
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lsr
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sta RW.FBITMAPCNT store FULL bitmap block count needed
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tax
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lda RW.PGCNT
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and #$1F need an extra incomplete bitmap block?
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beq .3
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inx
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.3 stx RW.BITMAPCNT store TOTAL bitmap block needed
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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.4 lda RW.FBITMAPCNT
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beq .49
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dec RW.FBITMAPCNT
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jsr RW.BLOCK.SETFF
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bra .5
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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.49 jsr RW.BLOCK.SET00
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lda RW.PGCNT
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and #$1F compute incomplete bitmap block
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asl
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asl
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asl
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asl times 16 for byte count
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tay
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lda #$FF
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2021-02-26 20:13:48 +00:00
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bcc .42 first half of block only
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2015-03-14 21:48:35 +00:00
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ldx #0
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.40 sta RW.BLOCK,x
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inx
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bne .40
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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cpy #0
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beq .5
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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.41 sta RW.BLOCK+$ff,y
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dey
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bne .41
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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bra .5
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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.42 sta RW.BLOCK-1,y
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dey
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bne .42
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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.5 inc RW.MLIWRITEBLOCK.BLK
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lda RW.MLIWRITEBLOCK.BLK
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cmp #4 Are we writing first volume bitmap ?
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bne .63 no, regular one
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2015-06-03 18:30:57 +00:00
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* lda #$CF Mark Block 0 & 1 free, 2,3 used (vol hdr)
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lda #$0F
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2021-02-26 20:13:48 +00:00
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sta RW.BLOCK
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2015-03-14 21:48:35 +00:00
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ldy #0
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lda #$8 Start a BLOCK 4 (%00001000)
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ldx RW.BITMAPCNT
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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.62 pha
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eor RW.BLOCK,y Mark bitmap blocks as "used"
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sta RW.BLOCK,y
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pla
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dex
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beq .63
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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lsr
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bne .62
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2021-02-26 20:13:48 +00:00
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2019-10-03 06:25:27 +00:00
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lda #$80
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2015-03-14 21:48:35 +00:00
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iny
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bra .62
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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.63 jsr MLI Write Block 4,5...
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.DA #MLIWRITEBLOCK
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.DA RW.MLIWRITEBLOCK
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bcs .9
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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dec RW.BITMAPCNT another bitmap block needed ?
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bne .4
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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clc
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2019-10-03 06:25:27 +00:00
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.9 rts
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2015-03-14 21:48:35 +00:00
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*--------------------------------------
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RW.BLOCK.SETFF lda #$FF
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2021-02-26 20:13:48 +00:00
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.HS 2C BIT ABS
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2015-03-14 21:48:35 +00:00
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RW.BLOCK.SET00 lda #$00
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2021-02-26 20:13:48 +00:00
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ldx #0
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2015-03-14 21:48:35 +00:00
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.1 sta RW.BLOCK,x
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sta RW.BLOCK+$100,x
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inx
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bne .1
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2021-02-26 20:13:48 +00:00
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2015-03-14 21:48:35 +00:00
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rts
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*--------------------------------------
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RW.MLIWRITEBLOCK
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.DA #3
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2016-12-12 11:05:47 +00:00
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.DA #$B0 Slot 3,Drive 2
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2015-03-14 21:48:35 +00:00
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.DA RW.BLOCK
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RW.MLIWRITEBLOCK.BLK
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.DA 2 Start writing block at #2
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*--------------------------------------
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RW.PGCNT .BS 1
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RW.FBITMAPCNT .BS 1
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RW.BITMAPCNT .BS 1
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*--------------------------------------
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RW.BLOCK2 .DA 0 pointer to previous block
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.DA 3 pointer to next block
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2016-12-12 11:05:47 +00:00
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.DA #$F4 $F=Vol Dir Header, 4=name len
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.AS 'RAM3'
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.BS 11 (RAM3 len=4, fill to 15)
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2015-03-14 21:48:35 +00:00
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.HS 0000000000000000
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RW.BLOCK2.CT .BS 4 Creation time
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.HS 0100C3270D version/min version/access/EL/EPB
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.DA 0 File Count
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.DA 4 bitmap pointer (Block 2&3 are Volume directory)
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RW.BLOCK2.TB .BS 2 Total Blocks
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RW.BLOCK2.END .EQ *
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*--------------------------------------
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2021-02-26 20:13:48 +00:00
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.INB usr/src/shared/x.printf.s
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2015-03-14 21:48:35 +00:00
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*--------------------------------------
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2021-09-07 12:32:31 +00:00
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RW.MSG .AZ "SuperExpander E, RAMWorks (I,II,III,z-Ram) Driver For A2osX\n"
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2018-04-11 15:35:51 +00:00
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RW.MSG.OK .AZ "/RAM3 Device Already Installed.\n"
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2020-08-07 19:49:24 +00:00
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RW.MSG.OK1 .AZ "%D KB Detected (%d Pages), %D KB (%d Pages) Available for RamDrive.\n"
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2018-04-11 15:35:51 +00:00
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RW.MSG.KO1 .AZ "Not Detected.\n"
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RW.MSG.OK2 .AZ "RamWorks Driver Installed.\n"
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RW.MSG.KO2 .AZ "RamWorks Driver Install Error.\n"
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RW.MSG.OK3 .AZ "RamWorks Drive Formatted as /RAM3.\n"
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RW.MSG.KO3 .AZ "RamWorks Drive Format Error.\n"
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2015-03-14 21:48:35 +00:00
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*--------------------------------------
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* Driver for Ramworks in main LC
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* $FF00 -> $FF9A (Inclusive)
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* $FF58 MUST BE $60 (RTS)
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2021-02-26 20:13:48 +00:00
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* DO NOT trash DRV.COMMAND...DRV.BLKNUM as ProDOS
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2015-03-14 21:48:35 +00:00
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* reuses it after Block operation
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2021-02-26 20:13:48 +00:00
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* A1,A2 are used by Disk II Driver,
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2015-06-03 18:30:57 +00:00
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* so we use it safely as Tmp Ptr
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2015-03-14 21:48:35 +00:00
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*--------------------------------------
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2015-06-03 18:30:57 +00:00
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DRV.A2L .EQ $3E
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DRV.A2H .EQ $3F
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2015-03-14 21:48:35 +00:00
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DRV.COMMAND .EQ $42
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2021-02-26 20:13:48 +00:00
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DRV.BUFF .EQ $44
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DRV.BLKNUM .EQ $46
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2015-03-14 21:48:35 +00:00
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*--------------------------------------
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2020-07-17 15:18:31 +00:00
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RWDRV.B.START .PH $FF00
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2021-02-26 20:13:48 +00:00
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RWDRV.START ldy DRV.COMMAND 0 = Status ?
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2015-03-14 21:48:35 +00:00
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beq RMDRV.CMDSTATUS
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2020-08-28 17:10:23 +00:00
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2015-03-14 21:48:35 +00:00
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cpy #3
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2020-08-28 15:11:27 +00:00
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2015-03-14 21:48:35 +00:00
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beq RWDRV.EXITOK 3 = Format : nothing to do, exit with no error
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2020-08-28 17:10:23 +00:00
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bcs RWDRV.IOERR > 3 = Invalid OP, IO error
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2015-03-14 21:48:35 +00:00
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2020-07-14 20:17:15 +00:00
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ldx DRV.BLKNUM
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cpx RWDRV.MAXLO+1
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2015-03-14 21:48:35 +00:00
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lda DRV.BLKNUM+1
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sbc RWDRV.MAXHI+1
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bcs RWDRV.IOERR DRV.BLKNUM >= RW.DRV.SIZE, IO error
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2020-07-14 20:17:15 +00:00
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2020-08-28 15:11:27 +00:00
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bit RD80STORE save 80 Store status
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2020-07-18 14:04:21 +00:00
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php Disable IRQ as no vector set in RW Banks
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sei
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2021-02-26 20:13:48 +00:00
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sta CLR80STORE make sure SETREADAUX/SETWRITEAUX effective everywhere
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2020-07-14 20:17:15 +00:00
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txa Get Back DRV.BLKNUM
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2015-06-03 18:30:57 +00:00
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asl compute PAGE = blocknumLO *2
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2015-03-14 21:48:35 +00:00
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pha
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lda DRV.BLKNUM+1 compute BANK = blocknumHI *2
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rol
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inc +1 for skipping Aux BANK 0
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2020-07-18 14:04:21 +00:00
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2015-03-14 21:48:35 +00:00
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plx move page into X
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beq RWDRV.GOAUX move from/to aux page0/1
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2020-07-18 14:04:21 +00:00
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2015-03-14 21:48:35 +00:00
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cpx #$C0
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bcs RWDRV.GOAUX move from/to aux LC
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*--------------------------------------
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* X=Page($02 -> $BF),A=Bank,Y=CMD
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*--------------------------------------
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2021-09-07 12:32:31 +00:00
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RWDRV.IO1 sta RWBankSelect Select RAMWorks Bank
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2015-03-14 21:48:35 +00:00
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2015-06-03 18:30:57 +00:00
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inx second 256 bytes first
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stx DRV.A2H Use DRV.A1L/H for RAM PTR
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stz DRV.A2L
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inc DRV.BUFF+1
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2015-03-14 21:48:35 +00:00
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dey Y=CMD, zero if read
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2015-06-03 18:30:57 +00:00
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bne RWDRV.W non zero, go write
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2019-10-09 10:05:08 +00:00
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2015-03-14 21:48:35 +00:00
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sta SETREADAUX
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2015-06-03 18:30:57 +00:00
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ldx #DRV.A2L READ:copy from RAM to BUFF
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lda #DRV.BUFF
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2015-03-14 21:48:35 +00:00
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bra RWDRV.RW
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2019-10-09 10:05:08 +00:00
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2019-10-03 06:25:27 +00:00
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RWDRV.W sta SETWRITEAUX
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2015-03-14 21:48:35 +00:00
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ldx #DRV.BUFF
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2015-06-03 18:30:57 +00:00
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lda #DRV.A2L WRITE:copy from BUFF to RAM
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dey Make sure Y=0 for main loop below
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2015-03-14 21:48:35 +00:00
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RWDRV.RW stx RWDRV.RW.SRC+1
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2015-06-03 18:30:57 +00:00
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sta RWDRV.RW.DST+1
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2015-03-14 21:48:35 +00:00
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2020-07-20 15:19:32 +00:00
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* clc 2 pages to copy
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.HS B0 BCS
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RWDRV.RW.LOOP sec
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2015-03-14 21:48:35 +00:00
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RWDRV.RW.SRC lda ($FF),y
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RWDRV.RW.DST sta ($FF),y
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iny
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bne RWDRV.RW.SRC
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2015-06-03 18:30:57 +00:00
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dec DRV.BUFF+1
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dec DRV.A2H
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2020-07-20 15:19:32 +00:00
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bcc RWDRV.RW.LOOP
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2015-03-14 21:48:35 +00:00
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2020-08-28 15:11:27 +00:00
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RWDRV.EXIT stz RWBankSelect
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2015-03-14 21:48:35 +00:00
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sta CLRREADAUX
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sta CLRWRITEAUX
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2019-10-09 10:05:08 +00:00
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2020-07-14 20:17:15 +00:00
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plp restore IRQ
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2015-03-14 21:48:35 +00:00
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2020-08-28 15:11:27 +00:00
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bpl RMDRV.CMDSTATUS
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sta SET80STORE
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2020-07-20 15:19:32 +00:00
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2019-10-03 06:25:27 +00:00
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RMDRV.CMDSTATUS
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2015-03-14 21:48:35 +00:00
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RWDRV.MAXLO ldx #$FF return device block count in X,Y...
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RWDRV.MAXHI ldy #$FF
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RWDRV.EXITOK lda #0 make A=0
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clc
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rts
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2020-08-28 17:10:23 +00:00
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RWDRV.IOERR lda #MLI.E.IO Carry already set
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rts
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2015-03-14 21:48:35 +00:00
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*--------------------------------------
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* X=Page(0/1 or LC),A=Bank
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*--------------------------------------
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RWDRV.GOAUX pha save BANK
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2021-02-26 20:13:48 +00:00
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sta SETWRITEAUX
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2015-03-14 21:48:35 +00:00
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ldy #RWDRVX.XM.SIZE Backup begining of $300 to generate move code
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2019-10-09 10:05:08 +00:00
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2015-03-14 21:48:35 +00:00
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.1 lda RWDRV.XM.RUN-1,y
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sta RWDRVX.XM.SAVE-1,y
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dey
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bne .1
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2019-10-09 10:05:08 +00:00
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2015-03-14 21:48:35 +00:00
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pla restore BANK
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2019-10-09 10:05:08 +00:00
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|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
sta SETREADAUX
|
|
|
|
|
jsr RWDRVX.START Setup Code in main mem at $300 for data move
|
|
|
|
|
* returns : CC=WRITE, CS=READ
|
|
|
|
|
sta CLRREADAUX CLRWRITEAUX already triggered by code copy
|
|
|
|
|
jsr RWDRV.XM.RUN Now execute generated code in main memory
|
2020-08-28 15:11:27 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
sta SETREADAUX
|
2020-08-28 15:11:27 +00:00
|
|
|
|
jmp RWDRVX.RESTORE
|
2019-10-09 10:05:08 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
RWDRV.END .EP
|
|
|
|
|
RWDRV.B.END
|
2020-07-20 15:19:32 +00:00
|
|
|
|
.LIST ON
|
2015-03-14 21:48:35 +00:00
|
|
|
|
RWDRV.SIZE .EQ RWDRV.B.END-RWDRV.B.START
|
2020-07-20 15:19:32 +00:00
|
|
|
|
.LIST OFF
|
2015-03-14 21:48:35 +00:00
|
|
|
|
*--------------------------------------
|
|
|
|
|
* Driver for Ramworks in aux memory
|
|
|
|
|
* $0200 -> $02FF TMP buffer for PAGE copy
|
|
|
|
|
* $0300 -> $03FD (Inclusive)
|
|
|
|
|
* do not trash $03FE-$03FF (IRQ Vector)
|
2021-02-26 20:13:48 +00:00
|
|
|
|
* X=Page(0/1 or LC),A=Bank
|
2015-03-14 21:48:35 +00:00
|
|
|
|
*--------------------------------------
|
|
|
|
|
RMDRVX.TMP .EQ $200
|
|
|
|
|
RWDRV.XM.RUN .EQ $300
|
|
|
|
|
*--------------------------------------
|
2021-02-27 14:54:51 +00:00
|
|
|
|
RWDRVX.B.START .PH $0300
|
2015-03-14 21:48:35 +00:00
|
|
|
|
RWDRVX.START sta RWDRVX.XM.BANK+1 setup BANK
|
2021-02-27 14:54:51 +00:00
|
|
|
|
|
|
|
|
|
lda DRV.COMMAND DRV.COMMAND: 1=READ,2=WRITE
|
|
|
|
|
lsr
|
|
|
|
|
php
|
|
|
|
|
|
2021-02-26 20:13:48 +00:00
|
|
|
|
ldy #RRAMWRAMBNK1
|
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
txa
|
|
|
|
|
beq .1 page 0/1, no need to check BANK
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
cmp #$D0 $C0 <= PAGE < $D0 ?
|
2016-05-01 19:53:12 +00:00
|
|
|
|
bcs .1 no, store in BNK1
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
ora #$10 Remap $C0 page to $D0 BNK2
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2021-02-26 20:13:48 +00:00
|
|
|
|
ldy #RRAMWRAMBNK2
|
|
|
|
|
|
|
|
|
|
.1 sty RWDRVX.XM.RWLC+1 Save to select proper RW bank later
|
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
ldy DRV.BUFF
|
|
|
|
|
ldx DRV.BUFF+1
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2021-02-27 14:54:51 +00:00
|
|
|
|
plp
|
2015-03-14 21:48:35 +00:00
|
|
|
|
bcc .2 CC=WRITE, CS=READ
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
stz RWDRVX.XM.SRC+1 READ from src LO = 0
|
|
|
|
|
sta RWDRVX.XM.SRC+2 READ from src HI = PAGE
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
sty RWDRVX.XM.DST+1 WRITE to DRV.BUFF
|
|
|
|
|
stx RWDRVX.XM.DST+2
|
|
|
|
|
bra .3
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.2 sty RWDRVX.XM.SRC+1 READ from DRV.BUFF
|
|
|
|
|
stx RWDRVX.XM.SRC+2
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
stz RWDRVX.XM.DST+1 WRITE to dst LO = 0
|
|
|
|
|
sta RWDRVX.XM.DST+2 WRITE to dst HI = PAGE
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.3 sta CLRWRITEAUX
|
|
|
|
|
|
|
|
|
|
ldy #RWDRVX.XM.SIZE
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.4 lda RWDRVX.XM.START-1,y
|
|
|
|
|
sta RWDRV.XM.RUN-1,y
|
|
|
|
|
dey
|
|
|
|
|
bne .4
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
rts
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
* Called form Main LC after RWDRVX.XM execution
|
|
|
|
|
*--------------------------------------
|
2021-02-26 20:13:48 +00:00
|
|
|
|
RWDRVX.RESTORE ldy #RWDRVX.XM.SIZE Now, restore begining of $300
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
.1 lda RWDRVX.XM.SAVE-1,y
|
|
|
|
|
sta RWDRV.XM.RUN-1,y
|
|
|
|
|
dey
|
|
|
|
|
bne .1
|
2020-07-18 14:04:21 +00:00
|
|
|
|
|
2020-08-28 15:11:27 +00:00
|
|
|
|
jmp RWDRV.EXIT
|
2015-03-14 21:48:35 +00:00
|
|
|
|
*--------------------------------------
|
2020-09-09 12:47:18 +00:00
|
|
|
|
* LC Copy Code, moved from Aux to main $300
|
|
|
|
|
* $0200 -> $02FF TMP buffer for 2 steps move between LCs
|
2015-03-14 21:48:35 +00:00
|
|
|
|
* CC=WRITE :
|
|
|
|
|
* CS=READ :
|
|
|
|
|
*--------------------------------------
|
2020-09-09 12:47:18 +00:00
|
|
|
|
RWDRVX.XM.START ldy #2 2 pages to copy
|
|
|
|
|
|
2020-12-15 13:23:22 +00:00
|
|
|
|
RWDRVX.XM.COPY sta CLRALTZP
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-12-15 13:23:22 +00:00
|
|
|
|
jsr RWDRV.XM.RUN+RWDRVX.XM.SRCLC-RWDRVX.XM.START
|
|
|
|
|
sta $C000,x select proper Main/Aux ZP/LC
|
2021-09-07 12:32:31 +00:00
|
|
|
|
RWDRVX.XM.IO1 sta RWBankSelect
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-09-09 12:47:18 +00:00
|
|
|
|
ldx #0
|
2015-03-14 21:48:35 +00:00
|
|
|
|
|
|
|
|
|
RWDRVX.XM.SRC lda $FFFF,x
|
|
|
|
|
sta RMDRVX.TMP,x
|
|
|
|
|
inx
|
|
|
|
|
bne RWDRVX.XM.SRC
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2020-12-15 13:23:22 +00:00
|
|
|
|
sta CLRALTZP
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-09-09 12:47:18 +00:00
|
|
|
|
jsr RWDRV.XM.RUN+RWDRVX.XM.DSTLC-RWDRVX.XM.START
|
2020-12-15 13:23:22 +00:00
|
|
|
|
sta $C000,x select proper Main/Aux ZP/LC
|
2021-09-07 12:32:31 +00:00
|
|
|
|
RWDRVX.XM.IO2 sta RWBankSelect
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-09-09 12:47:18 +00:00
|
|
|
|
ldx #0
|
2019-10-31 15:59:11 +00:00
|
|
|
|
|
2020-09-09 12:47:18 +00:00
|
|
|
|
RWDRVX.XM.2 lda RMDRVX.TMP,x
|
2015-03-14 21:48:35 +00:00
|
|
|
|
RWDRVX.XM.DST sta $FFFF,x
|
|
|
|
|
inx
|
2020-09-09 12:47:18 +00:00
|
|
|
|
bne RWDRVX.XM.2
|
2015-03-14 21:48:35 +00:00
|
|
|
|
|
|
|
|
|
inc RWDRV.XM.RUN+RWDRVX.XM.SRC+2-RWDRVX.XM.START
|
|
|
|
|
inc RWDRV.XM.RUN+RWDRVX.XM.DST+2-RWDRVX.XM.START
|
|
|
|
|
dey
|
|
|
|
|
bne RWDRVX.XM.COPY
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-09-09 12:47:18 +00:00
|
|
|
|
sta CLRALTZP
|
2021-09-07 12:32:31 +00:00
|
|
|
|
RWDRVX.XM.IO3 stz RWBankSelect
|
2020-09-09 12:47:18 +00:00
|
|
|
|
*--------------------------------------
|
|
|
|
|
RWDRVX.XM.MNLC bit RRAMWRAMBNK1 ProDOS always uses LCBANK1
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-09-09 12:47:18 +00:00
|
|
|
|
lda #0
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-09-09 12:47:18 +00:00
|
|
|
|
ldx #CLRALTZP
|
2019-10-21 14:25:37 +00:00
|
|
|
|
|
2020-09-09 12:47:18 +00:00
|
|
|
|
rts
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
RWDRVX.XM.SRCLC bcc RWDRVX.XM.MNLC CC=WRITE,CS=READ?
|
|
|
|
|
.HS 2C BIT ABS
|
2021-02-26 20:13:48 +00:00
|
|
|
|
RWDRVX.XM.DSTLC bcs RWDRVX.XM.MNLC CC=WRITE,CS=READ?
|
2020-09-09 12:47:18 +00:00
|
|
|
|
*--------------------------------------
|
2021-02-27 14:54:51 +00:00
|
|
|
|
RWDRVX.XM.RWLC bit $C000
|
2019-10-21 14:25:37 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
RWDRVX.XM.BANK lda #$FF
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2020-09-09 12:47:18 +00:00
|
|
|
|
ldx #SETALTZP
|
2021-02-26 20:13:48 +00:00
|
|
|
|
|
2015-03-14 21:48:35 +00:00
|
|
|
|
rts
|
|
|
|
|
*--------------------------------------
|
2020-09-09 12:47:18 +00:00
|
|
|
|
.LIST ON
|
|
|
|
|
RWDRVX.XM.SIZE .EQ *-RWDRVX.XM.START
|
|
|
|
|
.LIST OFF
|
2015-03-14 21:48:35 +00:00
|
|
|
|
*--------------------------------------
|
|
|
|
|
RWDRVX.XM.SAVE .BS RWDRVX.XM.SIZE
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
.EP
|
|
|
|
|
*--------------------------------------
|
2020-09-09 12:47:18 +00:00
|
|
|
|
RWDRVX.B.END .LIST ON
|
2019-10-09 10:05:08 +00:00
|
|
|
|
RWDRVX.SIZE .EQ RWDRVX.B.END-RWDRVX.B.START
|
|
|
|
|
.LIST OFF
|
2015-03-14 21:48:35 +00:00
|
|
|
|
*--------------------------------------
|
|
|
|
|
* CONTROL SECTION :
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
.DO RWDRV.SIZE>$9B
|
|
|
|
|
ERROR:RWDRV.SIZE too big
|
|
|
|
|
.FIN
|
|
|
|
|
.DO RWDRVX.SIZE>$FE
|
|
|
|
|
ERROR:RWDRVX.SIZE too big
|
|
|
|
|
.FIN
|
|
|
|
|
.DO RWDRVX.XM.SIZE>$F0
|
|
|
|
|
ERROR:RWDRVX.XM.SIZE too big
|
|
|
|
|
.FIN
|
|
|
|
|
*--------------------------------------
|
|
|
|
|
MAN
|
2021-02-26 20:13:48 +00:00
|
|
|
|
SAVE usr/src/sys/km.ramworks.s
|
2015-03-14 21:48:35 +00:00
|
|
|
|
ASM
|