2022-03-13 12:58:15 +00:00
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NEW
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AUTO 3,1
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*--------------------------------------
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2022-09-11 19:11:32 +00:00
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GS.Init lda CONF.SLOT
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asl
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asl
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asl
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asl
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sta Slotn0
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tax
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lda #L91C96.0.TCR.FDSE+L91C96.0.TCR.FUDPLX+L91C96.0.TCR.PADEN+L91C96.0.TCR.TXENA
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sta L91C96.0.TCR,x
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lda /L91C96.0.TCR.FDSE+L91C96.0.TCR.FUDPLX+L91C96.0.TCR.PADEN+L91C96.0.TCR.TXENA
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sta L91C96.0.TCR+1,x
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lda #L91C96.0.RCR.NOCRC+L91C96.0.RCR.RXENA+L91C96.0.RCR.ALLMUL
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sta L91C96.0.RCR,x
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lda /L91C96.0.RCR.NOCRC+L91C96.0.RCR.RXENA+L91C96.0.RCR.ALLMUL
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sta L91C96.0.RCR+1,x
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lda #1
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sta L91C96.BSR,x
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lda #L91C96.1.CR.NOWAIT
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sta L91C96.1.CR,x
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lda /L91C96.1.CR.NOWAIT
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sta L91C96.1.CR+1,x
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ldy #0
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.2 lda CONF.SRCMAC,y
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sta L91C96.1.IAR,x
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inx
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iny
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cpy #6
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bne .2
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.3 ldx Slotn0
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lda #L91C96.1.CTR.DEFAULT+L91C96.1.CTR.AUTOREL
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sta L91C96.1.CTR,x
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lda /L91C96.1.CTR.DEFAULT+L91C96.1.CTR.AUTOREL
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sta L91C96.1.CTR+1,x
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clc
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2022-03-13 12:58:15 +00:00
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rts
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*--------------------------------------
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2022-04-19 18:24:34 +00:00
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GS.Read php
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sei
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2022-03-13 12:58:15 +00:00
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2022-04-19 18:24:34 +00:00
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ldx Slotn0
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2022-09-11 19:11:32 +00:00
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lda #2
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sta L91C96.BSR,x
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lda L91C96.2.IST,x
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and #L91C96.2.IST.RCV
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beq GS.READWRITE.9
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.1 lda #L91C96.2.PTR.RCVD+L91C96.2.PTR.AUTOI+L91C96.2.PTR.READ
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sta L91C96.2.PTR,x
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lda /L91C96.2.PTR.RCVD+L91C96.2.PTR.AUTOI+L91C96.2.PTR.READ
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sta L91C96.2.PTR+1,x
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lda L91C96.2.DATA,x Get Frame Status Word (lo)
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lda L91C96.2.DATA,x Get Frame Status Word (HI)
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asl
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asl
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asl #$10 = odd?
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asl if odd, CS
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lda L91C96.2.DATA,x get lo byte count
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sbc #5 compute Size
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sta ZPBufCnt
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eor #$ff
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sta ZPnCnt
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lda L91C96.2.DATA,x get hi byte count
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sbc #0
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sta ZPBufCnt+1
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eor #$ff
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sta ZPnCnt+1
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ldy #0
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.2 inc ZPnCnt
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bne .3
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inc ZPnCnt+1
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beq .4
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.3 lda L91C96.2.DATA,x
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sta (ZPBufPtr),y
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iny
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bne .2
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inc ZPBufPtr+1
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bra .2
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.4 lda #L91C96.2.MMUCR.REMREL
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sta L91C96.2.MMUCR,x
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plp
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clc
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rts
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2022-04-19 18:24:34 +00:00
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*--------------------------------------
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GS.READWRITE.9 plp
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sec
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rts
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*--------------------------------------
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GS.Write php
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sei
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2022-03-13 12:58:15 +00:00
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2022-04-19 18:24:34 +00:00
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ldx Slotn0
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2022-09-11 19:11:32 +00:00
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lda #2
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sta L91C96.BSR,x
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lda ZPBufCnt
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eor #$ff
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sta ZPnCnt
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eor #$ff
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clc
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adc #6 3 WORDs more Status, len & Control
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bne .10
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clc LO byte is 0, no need for an extra empty page
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.10 lda ZPBufCnt+1
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eor #$ff
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sta ZPnCnt+1
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eor #$ff
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adc #0
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.1 ora #L91C96.2.MMUCR.ALLOC
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sta L91C96.2.MMUCR,x
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ldy #0
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.2 lda L91C96.2.IST,x
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and #L91C96.2.IST.ALLOC
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bne .3
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dey
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bne .2
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bra GS.READWRITE.9
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.3 lda L91C96.2.AAR,x
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sta L91C96.2.PNR,x
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lda #L91C96.2.PTR.AUTOI
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sta L91C96.2.PTR,x
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lda /L91C96.2.PTR.AUTOI
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sta L91C96.2.PTR+1,x
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ldy #S.ETH.SRCMAC+5 Add Src MAC Address
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ldx #5
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.4 lda CONF.SRCMAC,x
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sta (ZPBufPtr),y
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dey
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dex
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bpl .4
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ldx Slotn0
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stz L91C96.2.DATA,x write fake status word
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stz L91C96.2.DATA,x
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lda ZPBufCnt
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pha
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eor #$01
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lsr
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pla
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adc #$05 add 5 if odd, 6 if even
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sta L91C96.2.DATA,x
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lda ZPBufCnt+1
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adc #$00
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sta L91C96.2.DATA,x
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ldy #0
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.5 inc ZPnCnt
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bne .51
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inc ZPnCnt+1
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beq .70
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.51 lda (ZPBufPtr),y
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iny
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bne .6
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inc ZPBufPtr+1
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.6 inc ZPnCnt
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bne .61
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inc ZPnCnt+1
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beq .71
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.61 sta L91C96.2.DATA,x
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lda (ZPBufPtr),y
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sta L91C96.2.DATA,x
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iny
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bne .5
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inc ZPBufPtr+1
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bra .5
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.70 lda #0
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sta L91C96.2.DATA,x
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sta L91C96.2.DATA,x
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bra .8
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.71 sta L91C96.2.DATA,x
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lda #%00100000 signal an extra (odd) byte
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sta L91C96.2.DATA,x
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.8 lda #L91C96.2.MMUCR.NQPKT
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sta L91C96.2.MMUCR,x
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2022-04-19 18:24:34 +00:00
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plp
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2022-09-11 19:11:32 +00:00
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clc
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2022-04-19 18:24:34 +00:00
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rts
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*--------------------------------------
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2022-09-17 11:35:52 +00:00
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GS.Name .PS "LanCEgs"
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2022-04-19 18:24:34 +00:00
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*--------------------------------------
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DRV.GS .PH DRV.NIC.START
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2022-09-11 19:11:32 +00:00
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jmp DRV.GS.SendARP
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jmp DRV.GS.SendUDP
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2022-04-19 18:24:34 +00:00
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2022-09-11 19:11:32 +00:00
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DRV.GS.Rcvd php
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2022-04-19 18:24:34 +00:00
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sei
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2022-09-11 19:11:32 +00:00
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ldx DRV.BLK.Slotn0
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lda #2
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sta L91C96.BSR,x
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lda L91C96.2.IST,x
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and #L91C96.2.IST.RCV
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beq DRV.GS.9
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.1 lda #L91C96.2.PTR.RCVD+L91C96.2.PTR.AUTOI+L91C96.2.PTR.READ
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sta L91C96.2.PTR,x
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lda /L91C96.2.PTR.RCVD+L91C96.2.PTR.AUTOI+L91C96.2.PTR.READ
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sta L91C96.2.PTR+1,x
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lda L91C96.2.DATA,x Get Frame Status Word (lo)
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lda L91C96.2.DATA,x Get Frame Status Word (HI)
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asl
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asl
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asl #$10 = odd?
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asl if odd, CS
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lda L91C96.2.DATA,x get lo byte count
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sbc #5 compute Size
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sta DRV.FrameSize
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eor #$ff
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sta DRV.nCnt
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lda L91C96.2.DATA,x get hi byte count
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sbc #0
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sta DRV.FrameSize+1
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eor #$ff
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sta DRV.nCnt+1
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>LDYAI DRV.InBuf
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>STYA DRV.A1L
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ldy #0
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2022-04-19 18:24:34 +00:00
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2022-09-11 19:11:32 +00:00
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.2 inc DRV.nCnt
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bne .3
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inc DRV.nCnt+1
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beq .4
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.3 lda L91C96.2.DATA,x
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sta (DRV.A1L),y
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iny
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bne .2
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2022-04-19 18:24:34 +00:00
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2022-09-11 19:11:32 +00:00
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inc DRV.A1L+1
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bra .2
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.4 lda #L91C96.2.MMUCR.REMREL
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sta L91C96.2.MMUCR,x
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plp
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clc
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rts
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2022-04-19 18:24:34 +00:00
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*--------------------------------------
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DRV.GS.9 plp
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sec
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rts
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*--------------------------------------
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2022-09-11 19:11:32 +00:00
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DRV.GS.SendARP >LDYAI S.ARP
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>STYA DRV.FrameSize
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>LDYAI DRV.ARPBuf
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bra DRV.GS.Send
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*--------------------------------------
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DRV.GS.SendUDP >STYA DRV.FrameSize
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jsr DRV.BLK.IPUDPCheksum
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>LDYAI DRV.UDPBuf
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DRV.GS.Send >STYA DRV.A1L
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php
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2022-04-19 18:24:34 +00:00
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sei
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2022-09-11 19:11:32 +00:00
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ldx DRV.BLK.Slotn0
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lda #2
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sta L91C96.BSR,x
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lda DRV.FrameSize
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eor #$ff
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sta DRV.nCnt
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eor #$ff
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clc
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adc #6 3 WORDs more Status, len & Control
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bne .10
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clc LO byte is 0, no need for an extra empty page
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.10 lda DRV.FrameSize+1
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eor #$ff
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sta DRV.nCnt+1
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eor #$ff
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adc #0
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.1 ora #L91C96.2.MMUCR.ALLOC
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sta L91C96.2.MMUCR,x
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ldy #0
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.2 lda L91C96.2.IST,x
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and #L91C96.2.IST.ALLOC
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bne .3
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dey
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bne .2
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bra DRV.GS.9
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.3 lda L91C96.2.AAR,x
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sta L91C96.2.PNR,x
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lda #L91C96.2.PTR.AUTOI
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sta L91C96.2.PTR,x
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lda /L91C96.2.PTR.AUTOI
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sta L91C96.2.PTR+1,x
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* ldy #S.ETH.SRCMAC+5 Add Src MAC Address
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* ldx #5
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*.4 lda CONF.SRCMAC,x
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* sta (DRV.A1L),y
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* dey
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* dex
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* bpl .4
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ldx DRV.BLK.Slotn0
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stz L91C96.2.DATA,x write fake status word
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stz L91C96.2.DATA,x
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lda DRV.FrameSize
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pha
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eor #$01
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lsr
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pla
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adc #$05 add 5 if odd, 6 if even
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sta L91C96.2.DATA,x
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lda DRV.FrameSize+1
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adc #$00
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sta L91C96.2.DATA,x
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ldy #0
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.5 inc DRV.nCnt
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bne .51
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inc DRV.nCnt+1
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beq .70
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.51 lda (DRV.A1L),y
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iny
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bne .6
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inc DRV.A1L+1
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.6 inc DRV.nCnt
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bne .61
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inc DRV.nCnt+1
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beq .71
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.61 sta L91C96.2.DATA,x
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lda (DRV.A1L),y
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sta L91C96.2.DATA,x
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iny
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bne .5
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inc DRV.A1L+1
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bra .5
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.70 lda #0
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sta L91C96.2.DATA,x
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sta L91C96.2.DATA,x
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bra .8
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.71 sta L91C96.2.DATA,x
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lda #%00100000 signal an extra (odd) byte
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sta L91C96.2.DATA,x
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.8 lda #L91C96.2.MMUCR.NQPKT
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sta L91C96.2.MMUCR,x
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2022-04-19 18:24:34 +00:00
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plp
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2022-09-11 19:11:32 +00:00
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clc
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2022-04-19 18:24:34 +00:00
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rts
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2022-03-13 12:58:15 +00:00
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*--------------------------------------
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.EP
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2022-04-19 18:24:34 +00:00
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.LIST ON
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DRV.GS.SIZE .EQ *-DRV.GS
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.LIST OFF
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2022-03-13 12:58:15 +00:00
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*--------------------------------------
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MAN
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SAVE usr/src/sys/pm.vedrive.s.gs
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LOAD usr/src/sys/pm.vedrive.s
|
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ASM
|