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LANCEGS.DRV:Debugging session #1

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This commit is contained in:
Rémy GIBERT 2016-03-30 08:30:41 +02:00
parent 7f7cd4b6e3
commit 511c0df935
1 changed files with 12 additions and 10 deletions
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22
DRV/LANCEGS.DRV.S.txt
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@ -253,7 +253,7 @@ GETEVENT.RxOK lda #L91C96.2.PTR.RCVD+L91C96.2.PTR.AUTOI+L91C96.2.PTR.READ
sta L91C96.2.PTR+1,x
lda L91C96.2.DATA,x
lda L91C96.2.DATA+1,x
lda L91C96.2.DATA,x
pha
and #$60 Broadcast?
asl
@ -269,7 +269,7 @@ GETEVENT.RxOK lda #L91C96.2.PTR.RCVD+L91C96.2.PTR.AUTOI+L91C96.2.PTR.READ
sbc #3 compute FRAMELEN+2
sta FRAMELEN
tay
lda L91C96.2.DATA+1,x
lda L91C96.2.DATA,x
sta FRAMELEN+1
>PUSHYA FRAMLEN+2
@ -307,7 +307,7 @@ GETEVENT.RxOK lda #L91C96.2.PTR.RCVD+L91C96.2.PTR.AUTOI+L91C96.2.PTR.READ
inc ZPTmpPTR+1
.3 jsr DecFrameLen
beq .8
lda L91C96.2.DATA+1,x
lda L91C96.2.DATA,x
sta (ZPTmpPTR),y
iny
bne .2
@ -410,12 +410,12 @@ SEND >PULLW ZPTmpPTR
.3 lda L91C96.2.AAR,x
sta L91C96.2.PNR,x
lda #L91C96.2.PTR.AUTOI+2 skip status WORD
lda #L91C96.2.PTR.AUTOI
sta L91C96.2.PTR,x
lda /L91C96.2.PTR.AUTOI+2
lda /L91C96.2.PTR.AUTOI
sta L91C96.2.PTR+1,x
ldy #2+6+5 Add Src MAC Address
ldy #S.ETH.SRCMAC+5 Add Src MAC Address
ldx #5
.4 lda MAC,x
sta (ZPTmpPTR),y
@ -424,6 +424,8 @@ SEND >PULLW ZPTmpPTR
bpl .4
ldx DEVSLOTx0
stz L91C96.2.DATA,x write fake statusword
stz L91C96.2.DATA,x
lda FRAMELEN
pha
@ -432,7 +434,7 @@ SEND >PULLW ZPTmpPTR
sbc #$fb add 5 if odd, 6 if even
sta L91C96.2.DATA,x
lda FRAMELEN+1
sta L91C96.2.DATA+1,x
sta L91C96.2.DATA,x
ldy #2
@ -449,7 +451,7 @@ SEND >PULLW ZPTmpPTR
pla
sta L91C96.2.DATA,x
lda (ZPTmpPTR),y
sta L91C96.2.DATA+1,x
sta L91C96.2.DATA,x
iny
bne .5
inc ZPTmpPTR+1
@ -457,13 +459,13 @@ SEND >PULLW ZPTmpPTR
.70 lda #0
sta L91C96.2.DATA,x
sta L91C96.2.DATA+1,x
sta L91C96.2.DATA,x
bra .8
.71 lda #$40 signal an extra (odd) byte
sta L91C96.2.DATA,x
pla
sta L91C96.2.DATA+1,x
sta L91C96.2.DATA,x
.8 lda #L91C96.2.MMUCR.NQPKT
sta L91C96.2.MMUCR,x