UTHERNET2:Work in progress

This commit is contained in:
Rémy GIBERT 2016-01-08 17:41:11 +01:00
parent 90d90a89a6
commit fd62f73dfb

View File

@ -10,6 +10,7 @@ AUTO 6
*-------------------------------------- *--------------------------------------
.INB INC/MACROS.I .INB INC/MACROS.I
.INB INC/A2OSX.I .INB INC/A2OSX.I
.INB INC/LIBTCPIP.I
*-------------------------------------- *--------------------------------------
ZPTmpPTR .EQ ZPDRV ZPTmpPTR .EQ ZPDRV
*-------------------------------------- *--------------------------------------
@ -32,6 +33,7 @@ W5100.AR .EQ $C081 Memory Pointer
W5100.AR.GAR .EQ $0001 W5100.AR.GAR .EQ $0001
W5100.AR.SUBR .EQ $0005 W5100.AR.SUBR .EQ $0005
W5100.AR.SHAR .EQ $0009 W5100.AR.SHAR .EQ $0009
W5100.AR.SIPR .EQ $000F
W5100.AR.IR .EQ $0015 W5100.AR.IR .EQ $0015
W5100.AR.IMR .EQ $0016 W5100.AR.IMR .EQ $0016
W5100.AR.RTR .EQ $0017 W5100.AR.RTR .EQ $0017
@ -232,7 +234,7 @@ OPEN jsr Reset
>AR.SELECT S0.MR >AR.SELECT S0.MR
lda #3 IPRAW lda #3 IPRAW
sta W5100.DR-$81,x for S0.MR sta W5100.DR-$81,x for S0.MR
lda #1 lda #1 OPEN
sta W5100.DR-$81,x for S0.CR sta W5100.DR-$81,x for S0.CR
clc clc
rts rts
@ -331,6 +333,40 @@ SENDPREADY ldy #0
.8 clc .8 clc
rts rts
*-------------------------------------- *--------------------------------------
SETIPCFG >PULLW ZPTmpPTR
>AR.SELECT GAR
ldx DEVSLOTxF
ldy #S.IPCFG.GW
.1 lda (ZPTmpPTR),y
sta W5100.DR-$81,x
iny
cpy #S.IPCFG.GW+4
bne .1
* >AR.SELECT SUBR Implicit, next to GAR
ldy #S.IPCFG.MASK
.2 lda (ZPTmpPTR),y
sta W5100.DR-$81,x
iny
cpy #S.IPCFG.MASK+4
bne .2
>AR.SELECT SIPR
ldy #S.IPCFG.IP
.3 lda (ZPTmpPTR),y
sta W5100.DR-$81,x
iny
cpy #S.IPCFG.IP+4
bne .3
clc
rts
*--------------------------------------
* PRIVATE * PRIVATE
*-------------------------------------- *--------------------------------------
Reset ldx DEVSLOTxF Reset ldx DEVSLOTxF