NEW AUTO 3,1 *-------------------------------------- M16.AND lda #$32 AND (zp) .HS 2C BIT ABS M16.OR lda #$12 ORA (zp) .HS 2C BIT ABS M16.XOR lda #$52 EOR (zp) .HS 2C BIT ABS M16.ADD lda #$72 ADC (zp) .HS 2C BIT ABS M16.SUB lda #$F2 SBC (zp) sta .3 asl CS if SBC, CC if ADC ldy #2 ldx #2 .2 lda (pStack),y .3 adc (pStack) SELF MODIFIED sta (pStack),y inc pStack dex bne .2 rts *-------------------------------------- M16.SHL sec .HS 90 BCC M16.SHR clc lda (pStack) inc pStack inc pStack tax beq .8 ldy #1 bcc .3 .1 lda (pStack) asl sta (pStack) lda (pStack),y rol sta (pStack),y dex bne .1 .8 rts *-------------------------------------- .3 lda (pStack),y lsr sta (pStack),y lda (pStack) ror sta (pStack) dex bne .3 rts *-------------------------------------- M16.L ldx #0 .HS 2C BIT ABS M16.LE ldx #1 .HS 2C BIT ABS M16.G ldx #2 .HS 2C BIT ABS M16.GE ldx #3 .HS 2C BIT ABS M16.E ldx #4 .HS 2C BIT ABS M16.NE ldx #5 *-------------------------------------- M16.CMP lda MATH.CMPT,x sta .3+1 jsr M16.SUB tay A = BYTE 1 bmi .1 ora (pStack) BYTE 0 beq .2 lda #%001 .HS 2C BIT ABS .1 lda #%100 .HS 2C BIT ABS .2 lda #%010 .3 and #$ff SELF MODIFIED bra M16.LOR2 *-------------------------------------- M16.LAND jsr M16.AND bra M16.LOR1 M16.LOR jsr M16.OR M16.LOR1 ldy #1 lda (pStack) ora (pStack),y M16.LOR2 beq .1 lda #1 .1 sta (pStack) lda #0 ldy #1 sta (pStack),y rts *-------------------------------------- M16.UMUL clc .HS B0 BCS M16.IMUL sec php jsr M16.MULDIVMOD jsr M16.MUL plp bcc M16.PutTMP M16.ITMP lda ACC32.Sign eor ARG32.Sign bpl M16.PutTMP *-------------------------------------- * M16.PutnTMP *-------------------------------------- lda #TMP32 .HS 2C BIT ABS *-------------------------------------- M16.PutnARG lda #ARG32 sta .1+1 ldy #0 ldx #3 sec .1 lda $ff,y SELF MODIFIED eor #$ff two's complement of X bytes adc #0 sta (pStack),y iny dex bpl .1 rts *-------------------------------------- M16.uDIV clc .HS B0 BCS M16.IDIV sec clv bra M16.MOD M16.UMOD clc .HS B0 BCS M16.IMOD sec bit M16.RTS $60 M16.MOD php jsr M16.MULDIVMOD jsr M16.DIVMOD plp bcc .3 unsigned bvs M16.ITMP return ITMP lda ACC32.Sign IDIV eor ARG32.Sign bpl M16.PutARG bra M16.PutnARG .3 bvc M16.PutARG DIV *-------------------------------------- M16.PutTMP ldy #TMP32 MOD .HS 2C BIT ABS *-------------------------------------- M16.PutARG ldy #ARG32 lda $0,y sta (pStack) lda $1,y ldy #1 sta (pStack),y M16.RTS rts *-------------------------------------- M16.MULDIVMOD >PULLW ACC32 sta ACC32.Sign lda (pStack) sta ARG32 ldy #1 lda (pStack),y sta ARG32+1 sta ARG32.Sign bcc M16.RTS jsr .1 *-------------------------------------- * M16.ARG32ABS *-------------------------------------- lda ARG32.Sign bmi .2 rts *-------------------------------------- * M16.ACC32ABS *-------------------------------------- .1 lda ACC32.Sign bpl M16.RTS *-------------------------------------- * M16.nACC *-------------------------------------- ldy #ACC32 .HS 2C BIT ABS *-------------------------------------- * M16.nARG32 *-------------------------------------- .2 ldy #ARG32 sec lda $0,y eor #$ff adc #0 sta $0,y lda $1,y eor #$ff adc #0 sta $1,y rts *-------------------------------------- M16.MUL stz TMP32 stz TMP32+1 ldx #16 .1 lsr ARG32+1 ror ARG32 bcc .3 clc .2 lda TMP32 adc ACC32 sta TMP32 lda TMP32+1 adc ACC32+1 sta TMP32+1 .3 asl ACC32 rol ACC32+1 dex bne .1 rts *-------------------------------------- M16.DIVMOD stz TMP32 stz TMP32+1 ldx #16 .1 asl ARG32 rol ARG32+1 rol TMP32 rol TMP32+1 sec lda TMP32 sbc ACC32 tay lda TMP32+1 sbc ACC32+1 bcc .2 sty TMP32 sta TMP32+1 inc ARG32 bit0 always 0 because of .1 asl .2 dex bne .1 rts *-------------------------------------- MAN SAVE usr/src/sys/kernel.s.math16 LOAD usr/src/sys/kernel.s ASM