NEW
PREFIX
AUTO 4,1
				.LIST OFF	
*--------------------------------------
* Uses: 12 ZP
*  M32.ACC		.BS 4
*  M32.ARG		.BS 4
*  M32.TMP		.BS 4
*--------------------------------------
* TODO : Make it SIGNED 32 bits, with OVERVLOW detection
* http://6502.org/source/integers/32muldiv.htm
* http://nparker.llx.com/a2/mult.html
*--------------------------------------
M32.Add			ldx #4
				ldy #0
				
				clc						ARG+ACC->ACC
				
.1				lda M32.ARG,y
				adc M32.ACC,y
				sta M32.ACC,y
				iny
				dex
				bne .1

				clc
				rts						if CS, Overflow
*---------------------------------------
M32.Sub			ldx #4

				ldy #0
				
				sec						ARG-ACC->ACC
		
.1				lda M32.ARG,y
				sbc M32.ACC,y
				sta M32.ACC,y
				iny
				dex
				bne .1
				
				clc
				rts
			
				bcs .8					if CC, Overflow	
				
				sec
				rts
				
.8				clc
				rts
*--------------------------------------
M32.Mul			ldx #3					ARG*ACC->ACC

.1				lda M32.ACC,x
				sta M32.TMP,x
				stz M32.ACC,x
				dex
				bpl .1
				
				ldx #32
				
.2				lsr M32.TMP+3
				ror M32.TMP+2
				ror M32.TMP+1
				ror M32.TMP
				
				bcc .3
				
				clc
				lda M32.ARG
				adc M32.ACC
				sta M32.ACC

				lda M32.ARG+1
				adc M32.ACC+1
				sta M32.ACC+1

				lda M32.ARG+2
				adc M32.ACC+2
				sta M32.ACC+2

				lda M32.ARG+3
				adc M32.ACC+3
				sta M32.ACC+3
				
.3				asl M32.ARG
				rol M32.ARG+1
				rol M32.ARG+2
				rol M32.ARG+3
				
				dex
				bne  .2
				
				clc
				rts
*--------------------------------------
M32.Mod			sec
				.HS 90					BCC
*--------------------------------------
M32.Div			clc
				php

				stz M32.TMP				ARG/ACC->ACC
				stz M32.TMP+1
				stz M32.TMP+2
				stz M32.TMP+3
				
				ldx #32
				
.1				asl M32.ARG
				rol M32.ARG+1
				rol M32.ARG+2
				rol M32.ARG+3
				
				rol M32.TMP
				rol M32.TMP+1
				rol M32.TMP+2
				rol M32.TMP+3
				
				sec 
				
				lda M32.TMP
				sbc M32.ACC
				pha
				lda M32.TMP+1
				sbc M32.ACC+1
				pha
				lda M32.TMP+2
				sbc M32.ACC+2
				pha
				lda M32.TMP+3
				sbc M32.ACC+3
				bcs .2
				
				pla
				pla
				pla
				
				dex
				bne .1
				bra .3
				
.2				sta M32.TMP+3
				pla
				sta M32.TMP+2
				pla
				sta M32.TMP+1
				pla
				sta M32.TMP
				
				inc M32.ARG				bit0 always 0 because of .1 asl

				dex
				bne .1
								
.3				plp
				ldx #3
				
				ldy #M32.ARG+3
				bcc .4
				ldy #M32.TMP+3
				clc
				
.4				lda $0,y
				sta M32.ACC,x
				dey
				dex
				bpl .4
				
				rts
*--------------------------------------
M32.ACC2ARG		ldx #3					ACC->ARG
		
.1				lda M32.ACC,x
				sta M32.ARG,x
				dex
				bpl .1
				
				rts
*--------------------------------------
M32.Cmp			ldx #4
				
				ldy #0
				
				sec

.1				lda M32.ARG,y
				sbc M32.ACC,y
				sta M32.ACC,y
				iny
				dex
				bne .1
				
				bcc .5					CC if ACC < ARG

				lda M32.ACC
				ora M32.ACC+1
				ora M32.ACC+2
				ora M32.ACC+3			Z if ACC = ARG
				
				bne .4
				
				lda #%010				010 ACC = ARG
				rts
				
.4				lda #%100				100 ACC > ARG
				rts
				
.5				lda #%001				001	ACC < ARG
				rts				
*--------------------------------------
MAN
SAVE USR/SRC/X.M32S.S
LOAD USR/SRC/BIN/SH.S
ASM