DIM81    MAC
         _MLIT ]1;WPAR1   
         LDA   ]2         
         STA   WPAR2
         LDA   ]3         
         STA   WPAR3
         LDA   ]4
         STA   BPAR1      
         JSR   ADIM81
         <<<
GET81    MAC
         _AXLIT ]1        
         LDY   ]2         
         JSR   AGET81
         <<<
PUT81    MAC
         _MLIT ]1;WPAR1   
         _MLIT ]2;WPAR2   
         LDA   ]3         
         STA   BPAR1
         JSR   APUT81
         <<<
DIM82    MAC
         _MLIT ]1;WPAR1   
         LDA   ]2         
         STA   WPAR2
         LDA   ]3         
         STA   WPAR3
         LDA   ]4         
         STA   BPAR2
         LDA   ]5         
         STA   BPAR1
         JSR   ADIM82
         <<<
GET82    MAC
         _MLIT ]1;WPAR1
         LDA   ]2         
         STA   BPAR1
         LDA   ]3         
         STA   BPAR2
         JSR   AGET82
         <<<
PUT82    MAC
         _MLIT ]1;WPAR1   
         _MLIT ]2;WPAR2   
         LDA   ]3         
         STA   BPAR1
         LDA   ]4         
         STA   BPAR2
         JSR   APUT82
         <<<
DIM161   MAC
         _MLIT ]1;WPAR1   
         _MLIT ]2;WPAR2   
         LDA   ]3         
         STA   WPAR3
         LDA   ]4         
         STA   BPAR1
         JSR   ADIM161
         <<<
PUT161   MAC
         _MLIT ]1;WPAR1   
         _MLIT ]2;WPAR2   
         _MLIT ]3;WPAR3   
         JSR   APUT161
         <<<
GET161   MAC
         _MLIT ]1;WPAR1   
         _MLIT ]2;WPAR2   
         JSR   AGET161
         <<<
DIM162   MAC
         _MLIT ]1;WPAR3   
         _MLIT ]2;WPAR1   
         _MLIT ]3;WPAR2   
         LDA   ]4         
         STA   BPAR1
         LDA   ]5         
         STA   BPAR2
         JSR   ADIM162
         <<<
PUT162   MAC
         _MLIT ]1;WPAR1   
         _MLIT ]2;WPAR2   
         _MLIT ]3;WPAR3   
         _MLIT ]4;ADDR1   
         JSR   APUT162
         <<<
GET162   MAC
         _MLIT ]1;WPAR1   
         _MLIT ]2;WPAR2   
         _MLIT ]3;WPAR3   
         JSR   AGET162
         <<<
