mirror of
https://github.com/nathanriggs/AppleIIAsm-Collection.git
synced 2024-11-27 12:49:27 +00:00
358 lines
6.2 KiB
Plaintext
358 lines
6.2 KiB
Plaintext
*
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ADDIT16
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*
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PLA
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STA RETADR
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PLA
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STA RETADR+1
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PLA
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STA :ADD2
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PLA
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STA :ADD2+1
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PLA
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STA :ADD1
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PLA
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STA :ADD1+1
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LDA :ADD1
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CLC
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ADC :ADD2
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TAY
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STY RETURN
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LDA :ADD1+1
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ADC :ADD2+1
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TAX
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STX RETURN+1
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LDA #2
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STA RETLEN
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LDA RETADR+1
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PHA
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LDA RETADR
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PHA
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RTS
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:ADD1 DS 2
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:ADD2 DS 2
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*
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SUBT16
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*
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PLA
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STA RETADR
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PLA
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STA RETADR+1
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PLA
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STA :SUBT
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PLA
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STA :SUBT+1
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PLA
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STA :MINU
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PLA
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STA :MINU+1
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LDA :MINU
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SEC
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SBC :SUBT
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TAY
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STY RETURN
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LDA :MINU+1
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SBC :SUBT+1
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TAX
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STX RETURN+1
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LDA #2
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STA RETLEN
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LDA RETADR+1
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PHA
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LDA RETADR
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PHA
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RTS
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:MINU DS 2
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:SUBT DS 2
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*
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MULT16
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*
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PLA
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STA RETADR
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PLA
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STA RETADR+1
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PLA
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STA :MLIER
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PLA
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STA :MLIER+1
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PLA
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STA :MCAND
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PLA
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STA :MCAND+1
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LDA #0
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STA :HPROD
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STA :HPROD+1
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LDX #17
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CLC
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:MULLP
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ROR :HPROD+1
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ROR :HPROD
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ROR :MLIER+1
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ROR :MLIER
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BCC :DECCNT
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CLC
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LDA :MCAND
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ADC :HPROD
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STA :HPROD
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LDA :MCAND+1
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ADC :HPROD+1
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STA :HPROD+1
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:DECCNT
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DEX
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BNE :MULLP
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LDY :HPROD
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LDX :HPROD+1
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LDA :MLIER+1
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TAX
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STX RETURN+1
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LDA :MLIER
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TAY
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STY RETURN
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LDA :HPROD
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STA RETURN+2
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LDA #2
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STA RETLEN
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LDA RETADR+1
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PHA
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LDA RETADR
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PHA
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LDA :HPROD
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RTS
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:MCAND DS 3
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:MLIER DS 3
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:HPROD DS 2
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*
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UDIVD16
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LDA #0
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BEQ UDIVMD
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UREMD16
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LDA #2
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UDIVMD
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STA _RSLTI
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PLA
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STA RETADR
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PLA
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STA RETADR+1
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PLA
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STA _DVSOR
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PLA
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STA _DVSOR+1
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PLA
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STA _DVEND
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PLA
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STA _DVEND+1
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JSR UDIV
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BCC DIVOK
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DIVERR JMP EREXIT
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DIVOK JMP OKEXIT
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SDIVD16
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LDA #0
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BEQ SDIVMD
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SREMD16
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LDA #2
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BNE SDIVMD
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SDIVMD
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STA _RSLTI
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PLA
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STA RETADR
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PLA
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STA RETADR+1
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PLA
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STA _DVSOR
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PLA
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STA _DVSOR+1
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PLA
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STA _DVEND
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PLA
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STA _DVEND+1
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LDA _DVEND+1
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EOR _DVSOR+1
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STA _SQUOT
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LDA _DVEND+1
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STA _SREMD
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LDA _DVSOR+1
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BPL CHKDE
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LDA #0
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SEC
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SBC _DVSOR
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STA _DVSOR
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LDA #0
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SBC _DVSOR+1
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STA _DVSOR+1
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CHKDE
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LDA _DVEND+1
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BPL DODIV
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LDA #0
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SEC
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SBC _DVEND
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STA _DVEND
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LDA #0
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SBC _DVEND+1
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STA _DVEND+1
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DODIV
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JSR UDIV
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BCS EREXIT
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LDA _SQUOT
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BPL DOREM
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LDA #0
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SEC
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SBC _DVEND
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STA _DVEND
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LDA #0
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SBC _DVEND+1
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STA _DVEND+1
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DOREM
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LDA _SREMD
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BPL OKEXIT
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LDA #0
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SEC
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SBC _DVEND+2
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STA _DVEND+2
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LDA #0
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SBC _DVEND+3
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STA _DVEND+3
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JMP OKEXIT
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EREXIT
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LDA #0
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STA _DVEND
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STA _DVEND+1
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STA _DVEND+2
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STA _DVEND+3
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STA RETURN
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STA RETURN+1
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LDA #2
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STA RETLEN
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SEC
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BCS DVEXIT
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OKEXIT
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CLC
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DVEXIT
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LDX _RSLTI
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LDA _DVEND,X
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TAY
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LDA _DVEND+1,X
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TAX
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STY RETURN
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STX RETURN+1
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LDA #2
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STA RETLEN
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LDA RETADR+1
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PHA
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LDA RETADR
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PHA
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*
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RTS
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UDIV
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LDA #0
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STA _DVEND+2
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STA _DVEND+3
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LDA _DVSOR
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ORA _DVSOR+1
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BNE OKUDIV
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SEC
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RTS
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OKUDIV
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LDX #16
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DIVLP
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ROL _DVEND
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ROL _DVEND+1
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ROL _DVEND+2
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ROL _DVEND+3
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CHKLT
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SEC
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LDA _DVEND+2
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SBC _DVSOR
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TAY
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LDA _DVEND+3
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SBC _DVSOR+1
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BCC DECCNT
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STY _DVEND+2
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STA _DVEND+3
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DECCNT
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DEX
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BNE DIVLP
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ROL _DVEND
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ROL _DVEND+1
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CLC
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RTS
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_DVSOR DS 2
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_DVEND DS 4
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_SQUOT DS 1
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_SREMD DS 1
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_RSLTI DS 1
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*
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COMP16
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*
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PLA
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STA RETADR
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PLA
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STA RETADR+1
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PLA
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STA :SUBT
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PLA
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STA :SUBT+1
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PLA
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STA :MINU
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PLA
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STA :MINU+1
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LDA RETADR+1
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PHA
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LDA RETADR
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PHA
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LDA :MINU
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CMP :SUBT
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BEQ :EQUAL
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LDA :MINU+1
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SBC :SUBT+1
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ORA #1
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BVS :OVFLOW
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RTS
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:EQUAL
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LDA :MINU+1
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SBC :SUBT+1
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BVS :OVFLOW
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RTS
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:OVFLOW
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EOR #$80
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ORA #1
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RTS
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:MINU DS 2
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:SUBT DS 2
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*
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RAND16
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*
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LDA RNDL
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STA :SEED
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LDA RNDH
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STA :SEED+1
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LDA :SEED
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BEQ :LOW0
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ASL :SEED
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LDA :SEED+1
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ROL
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BCC :NOEOR
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:DOEOR
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EOR #>$0369
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STA :SEED+1
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LDA :SEED
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EOR #<$0369
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STA :SEED
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JMP :EXIT
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:LOW0
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LDA :SEED+1
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BEQ :DOEOR
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ASL
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BEQ :NOEOR
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BCS :DOEOR
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:NOEOR
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STA :SEED+1
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:EXIT LDX :SEED+1
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LDY :SEED
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STY RETURN
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STX RETURN+1
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LDA #2
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STA RETLEN
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RTS
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:SEED DS 2
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